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EEN1026 Electronics II: Experiment

Experiment EB1: FET Amplifier Frequency Response

Learning Outcome of Subjects

 LO1: · Explain the principles and operation of amplifiers and switching circuits
 LO2: Analyze high and low frequency response of amplifiers
 LO3: · Analyze the operation of power amplifiers and switching circuits.

1.0 Apparatus
Equipment required Components required
Power Supply –1 N-channel JFET 2N5457 –1
Oscilloscope –1 Resistor 10k (1/4W) –2
Digital Multimeter –1 Resistor 3.3k (1/4W) –1
Breadboard –1 Resistor 3.9k (1/4W) –1
Function Generator –1 Resistor 22k (1/4W) –1
Mylar Capacitor 0.47F –2
Mylar Capacitor 0.1F –1
Mylar Capacitor 0.01F –1
50 k potentiometer -- 1

Objectives:

1. Construct and test a voltage amplifier using N-channel JFET device in a common source
configuration
2. Apply the voltage divider biasing method to set the DC operating point (VGSq , IDSq) .
Verify the estimated DC operating point with the measured data.
3. Investigate the effect of frequency changes on the voltage gain of the amplifier, measure
its frequency response and obtain its operating bandwidth.
4. Investigate the capacitance effect on the frequency response of the common source JFET
amplifier

Important Notes

All related calculation questions that does not require experimental data must be
answered before coming to the lab. You are required to show all the calculation steps when
requested by the lab instructor. During the evaluation session, your lab instructor may request
you to demonstrate how the measurement data is obtained and explain your experimental
results.

You are advised to attempt the theoretical questions asked in the lab sheet before
coming to the lab. The lab session is only 3 hours and will be mostly spend on collecting
experiment data, analyzing result and comparing the data with the calculated value. Before
coming to the lab, you will also need to study the related theory from lecture material of
chapter 1 and topics involving JFET device characteristic, JFET biasing and JFET amplifier
from the textbook. This is important so that you know what result will be expected from the
experiment. In order to answer the questions in the lab sheet, you also need to make reading
preparation.
EEN1026 Electronics II: Experiment

2.0 Background Theory

An amplifier is a circuit that increases/decrease the input signal value and in this experiment
the signal to be amplified is the voltage. In this experiment you are going to investigate
frequency response characteristic of a voltage amplifier circuit using the N-channel JFET
device

Most amplifiers have relatively constant gain over a certain range of frequencies. This range
of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier
depends on the circuit component values, the type of active components and the dc operating
point of the active component. When an amplifier is operated within its bandwidth, the
current gain  Ai  , voltage gain  Av  , and power gain  A p  values are referred to as midband
gain values. A simplified frequency-response curve that represents the relationship between
amplifier gain and operating frequency is shown in Figure 1.
Power Gain

Ap drops at lower Ap drops at higher


frequencies frequencies
Mid-band
Ap(mid)

0.5Ap(mid) Bandwidth

fc1 fc2
Figure Frequency
1: A simplified frequency response curve
As the frequency-response curve shows, the power gain of an amplifier remains
relatively constant across a band of frequencies. When the operating frequency starts to go
outside this frequency range, the gain begins to drop. Two frequencies of interest, f c1 and
f c 2 , are the frequencies at which power gain decreases to approximately 50% of A p (mid ) .
The frequencies labeled f c1 and f c 2 are called the lower and upper cutoff frequencies of an
amplifier, respectively. These frequencies are considered to be the bandwidth limits for the
amplifier and thus bandwidth BW is given by

BW  f c 2  f c1 .
The geometric average of f c1 and f c 2 is called the geometric center frequency fo of an
amplifier, given by
f0 
. f c1 f c 2
When the operating frequency is equal to f 0 , the power gain of the amplifier is at its
maximum value.
Frequency response curves and specification sheets often list gain values that are
measured in decibels (dB). The dB power gain of an amplifier is given by
P
A p ( dB )  10 log A p  10 log out .
Pin
EEN1026 Electronics II: Experiment

Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A
+3dB gain caused power to double while a –3dB gain caused power to be cut in half.
v2
2
v out
Using the basic power relationships, Pout  and Pin  in , the power gain may be
RL Rin
rewritten as
P v 2 RL v R
A p ( dB )  10 log out  10 log out  20 log out  10 log in
Pin 2
v in Rin v in RL

The voltage component of the equation is referred to as dB voltage gain. When the amplifier
input and out resistances are equal
v
A p ( dB )  20 log out  Av ( dB ) . ( Rin  RL )
vin
Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the amplifier
also changes by –3dB.

Low Frequency Response of FET Amplifier


In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the
RC combinations formed by the network capacitors and the network resistive parameters that
determine the cutoff frequency. There are three capacitors – two coupling capacitor CG and
C D , and one bypass capacitor, C S . Let us assume that CG , C D and C S are arbitrarily
large and can be represented by short-circuit. The total resistance in series with CG is given
by
RCG  RG  Rin
where Rin  R1 || R2 is the input impedance of the amplifier circuit. The power supplied by
the signal generator is Pin  V gen /( RG  Rin ) . However, the reactance XCG of capacitance CG
2

is not negligible at very low frequencies. The frequency at which Pin is cut in half is when
X CG  RG  Rin . Thus the lower half-power point for gate circuit occurs at frequency
1 1
f LG  
2RCG C G 2  RG  Rin  C G
+VDD

R2 RD CD
RG CG G D

S RL
Vgen
Vin R1 RS CS

Figure 2(a): Schematic diagram of a JFET amplifier


CD

RG CG VG G D

S RD RL
Vgen Vin R1||R2 RS CS
EEN1026 Electronics II: Experiment

Figure 2(b): JFET amplifier low-frequency ac equivalent circuit

VD
D CD
gmVgs RD RL
S

Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of
the JFET drain terminal, rd, is much larger than RD).

When CG and C S are arbitrarily large and can be represented by short-circuit, the drain
circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also
be represented by a short-circuit, the output power to load resistor RL is Pout  V D2 / R L . At low
frequencies where the reactance XCD of capacitance C D is not negligible, Pout is cut in half
when X CD  R L . Thus the lower half-power point for drain circuit occurs at frequency
1
f LD 
2R L C D

At the half-power point, the output voltage reduces to 0.707 times its midband value. The
actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD
(determined by CD).

High Frequency Response of FET Amplifier

The high frequency response of the FET is limited by values of internal capacitance,
as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal
pair of the FET. These capacitances each have a reactance that decreases as frequency
increases. As the reactance of a given terminal capacitance decreases, more and more of the
signal at the terminal is bypassed through the capacitance.

RG
Cout(M) Cds CL RL||RD

Vgen R1||R2 Cgs Cin(M)


EEN1026 Electronics II: Experiment

Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency
response.

+VDD

R2 RD CD
Cgd
RG CG
Cds
RL CL
Cgs
Vgen
R1 RS CS

Figure 3(b): FET amplifier high frequency ac equivalent circuit.

The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure
3(b), including all the terminal capacitance values. C gd is replaced with the Miller
equivalent input and output capacitance values given as
Av  1
Cin( M )  C gd  Av  1 and Cout ( M )  C gd
Av

Cgd

G AV D

G AV D Cin(M) Cout(M)

Figure 4: Miller equivalent circuit for a feedback capacitor.


Note the absence of capacitors CG , C D and C S in Figure 3(b), which are all assumed to be
short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are
given by
EEN1026 Electronics II: Experiment

CG  C gs  Cin (M ) and C D  C out ( M )  C ds  C L

where C L is the input capacitance of the following stage. In general the capacitance C gs is
the largest of the parasitic capacitances, with C ds the smallest. The high cutoff frequencies
for the gate and drain circuits are then given by
1 1
f HG  and f HD 
 CG
2Rin  2R ' L C D

where Rin  RG || Rin and R ' L  RD || RL . At very high frequencies, the effect of CG
 is to
reduce the total impedance of the parallel combination of R1 , R2 and CG  in Figure 3(b).
The result is a reduced level of voltage across the gate-source terminals. Similarly, for the
drain circuit, the capacitive reactance of C D will decrease with frequency and consequently
reduces the total impedance of the output parallel branches of Figure 3(b). It causes the
output voltage to decrease as the reactance becomes smaller.
3.0 Procedures

1. Before connecting the circuit of Figure 5, measure the actual resistance of R1, R2, RD, RS
and RL as accurate as possible with a digital multimeter (set it to the best resistance range)
and record the measured values.
2. Connect the common source JFET amplifier circuit as shown in Figure 5 using a
breadboard (refer to Appendix C). Do not connect the power supply and the function
generator to the circuit yet. Keep the connecting wires on the breadboard as short as
possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit.
3. Set the power supply output to +12V. Connect its output to the circuit and measure its
voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC voltage
VG(cal) using the voltage-divider rule.
4. Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as
possible. Note that the measured VG should be closed to the calculated VG(cal), and VS
should be > VG since VGS must be < 0 V for N-channel JFET.
5. Before connecting the function generator to the circuit, use an oscilloscope to
measure the output voltage of the generator and set it to 200 kHz sine-wave with a
peak-to-peak voltage of 0.1V. Press the attenuation button (ATT) of the generator for
easy adjustment of its output voltage.
6. Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope
(set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the
oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the
oscilloscope to CH2. Adjust +V the =12V
trigger level on the oscilloscope to obtain stable
DD
waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the
calibrated (CAL’D) positions. 0.1F
CH1 RD=3.3k
R =22k
1
(vin) CD=0.01F
Function Generator D

50 G CH2
(vL)
CG=0.47F S RL=10k
Vgen R2 =10k CS=0.47F
RS=3.9k

D
S
G
EEN1026 Electronics II: Experiment

Figure 5: A Common source JFET amplifier

7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope
screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and
the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used.
Note that the input and output waveforms should be approximately 180 o out of
phase.
8. From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages of vL and
vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200 kHz.
Ask the instructor to check all of your results. You must show the oscilloscope
waveforms to the instructor.
9. Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller
frequency steps near the half-power point while larger steps can be used at mid-band
frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate
the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of
the function generator for frequency adjustment.
10. Plot a curve of Av versus frequency.
11. Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the
frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator
frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value in
the mid-band.
12. Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the
generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).
13. Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier
from the above measurements. Ask the instructor to check all of your results. You
must show the oscilloscope waveforms at 550 kHz to the instructor.
14. Design or modify the circuit in Figure 5 in order to measure the parameter of the device,
namely Gate-Source Cutoff Voltage (VGS(off) or Vp ) and Zero-Gate Voltage Current (IDSS).
These two values can be used in the Shockley equation I D = IDSS (1 – VGS/Vp)2 . Hint: You
can use a potentiometer and/or negative power source in the circuit. By solving the
simultaneous equation of the Shockley equation and the load line equation, you can
obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the
measured value.

Report Submission

Submit your report on the same day immediately after the experiment.
EEN1026 Electronics II: Experiment

Appendix A - Designing Voltage-Divider Bias for JFET


Similar to designing a bipolar transistor circuit, a JFET needs to be biased at the correct dc
operating point before it can function properly as an amplifier. There are a number of biasing
configurations available, such as gate bias, self-bias, and voltage-divider bias. The self-bias
and the voltage-divider bias use negative dc feedback to stabilize the operating point of the
JFET against parameter variation of the JFET. DC operating point in this context refers to the
drain-to-source voltage VDS and the drain current ID of the JFET. A stable operating point
means VDS and ID do not change much with temperature and when we change one JFET with
another JFET of similar part number. A voltage-divider bias employing the general purpose
N-channel JFET 2N5457 is shown in Figure A1.

2N5457

Figure A1 – Schematic of the dc bias using voltage-divider bias scheme

A.1 JFET Large Signal Parameters


From the datasheet of 2N5457, the following parameters are given at temperature of 25oC.

Table A1 – Minimum and maximum large signal parameter for 2N5457


Parameter Minimum Maximum
Gate Source Cutoff Voltage -0.5V (VTmin) -6.0V (VTmax)
(VT)
Zero-Gate Voltage Drain 1.0mA (IDSSmin) 5.0mA (IDSSmax)
Current (IDSS)

A.2 Transconductance Curve

When the JFET is biased in its active region, the channel between drain and source terminals
are in “pinched-off” state. The drain current will be largely independent of the drain-source
voltage VDS and will only depend on the gate-source voltage V GS. Thus unlike the bipolar
transistor which is a current controlled device (the collector current I C is a function of base
EEN1026 Electronics II: Experiment

current IB in active region), the JFET or FET in general is a voltage controlled device. The
relationship between VGS and ID in the active region is given by:
2
 V 
I D  I DSS 1  GS  (1)
 VT 

Plotting (1) for the two sets of large signal parameter (VTmin, IDSSmin) and (VTmax, IDSSmax) results
in the curves of Figure A2. These curves are known as transconductance curves because they
relate current to voltage.
0.005
IDSSmax

0.004 Note:
IDmax refers to the
curve when parameter
IDmin Vgs 0.003 is given by (VTmax,
i
IDSSmax) while IDmin
IDmax Vgs
i for parameter (VTmin,
0.002
IDmax IDSSmin).

0.001
IDSSmin
IDmin
0
10 8 6 4 2 0
VGS
Vgs
i
Figure A2 – The transconductance curve for the JFET 2N5457

A.3 Determining the Load Line

R2
From Figure A1, VG  VDD (2)
R1  R2
and VGS  VG  V S (3)
VS
Since I S  I D  (4)
RS
Substituting (3) into (4), we obtain the load line relationship:
VG VGS
ID   (5)
RS RS
Equation (5) is in the form
I D  mVGS  c
So it is a straight line where m is the gradient of slope of the line and c is the intercept point
of the line with the ID axis.

Let us select (ID_max, VGS_max) and (ID_min, VGS_min) to be the two desired operating points on the
maximum and minimum transconductance curves. This is shown in Figure A3. A straight
line can be drawn joining these two points; this line will be our dc load line. The slope and
intercept point of the line will determine the value of biasing resistors R 1, R2 and RS. The
EEN1026 Electronics II: Experiment

value of ID_max and ID_min are selected based on the allowable change in drain current due to
parameter variation in the JFET.
0.005

0.004

IDmax
Required dc
IDmin Vgs 0.003 load line
i

IDmax Vgs
i
0.002 Allowable
change in
(VGS_max,ID_max) drain
0.001 current ID
(VGS_min,ID_min)
due to
parameter
IDmin variation.
0
10 8 6 4 2 0
VGSVgs
i
Figure A3 – Required maximum and minimum operating points and the dc load line

The only requirement for the two operating points would be:

|ID_max| > |ID_min| (6)

A.4 Finding the Values of Bias Resistors


The procedure of designing the voltage-divider bias for JFET is now summarized as follows:

Step 1
Fix ID_max and ID_min, the drain current at the maximum and minimum transconductance curves.
This will determine the allowable change in drain current.

Step 2
Find VGS_max and VGS_min.
 I D _ max 
VGS _ max  1  V max (7a)
 I DSS max 
T

 I D _ min 
VGS _ min  1  V min (7b)
 I DSS min 
T

Step 3
Determine the slope and intercept point for dc load line, from (5).
I D _ max  I D _ min
m (8a)
VGS _ max  VGS _ min

I D _ minVGS _ max  I D _ maxVGS _ min


c (8b)
VGS _ max  VGS _ min
EEN1026 Electronics II: Experiment

1
RS   (9)
m

VG  RS  c (10)

Arbitrary choosing a suitable R2. Then R1 is given by , from (2):


V 
R1  R2  CC  1 (11)
 VG 

Step 4
Choose a suitable value for RD. Find the corresponding drain voltage.
V D _ min  VCC  R D I D _ min (12a)

V D _ max  VCC  RD I D _ max (12b)

Example – For this Lab Experiment

From Figure A3, we would like the dc load line to intercept the maximum and minimum
transconductance curves when VGS is negative. From Equation (6), let us choose:
ID_max = 1.50mA
ID_min = 0.85mA
From (7a) and (7b):
VGS_max = -2.714V
VGS_min = -0.039V
From (8a) and (8b):
m = -2.43010-4
c = 8.40510-4
Hence from (9):
RS = 4.12k .
And from (10):
VG = 3.46V
Finally from choosing R2 = 10.0k :
from (11), R1 = 24.7k
If we choose a drain resistance of RD = 3.3k, from (12a) and (12b)
VD_max = 9.20V
VD_min = 7.05V
Percent error in drain voltage;

Error = (9.20 – 7.05)/ 7.05 = 22.33%

A plot of the load line is shown in Figure A4.


EEN1026 Electronics II: Experiment

0.005

0.004

I D
IDmin Vgs
i 0.003

IDmax Vgs Dc load


i
line
IDload Vgs 0.002
i

0.001

0
10 8 6 4 2 0
VVgs
GS i
Figure A4 – Dc load line with transconductance curves for example

References
1. Rashid, "Microelectronic Circuits: Analysis and Design", PWS Publishing, 1998
2. Millman & Halkias, "Integrated Electronics", 2nd Ed., McGraw-Hill, 1971
3. R.T. Paynter, “Introductory Electronic Devices and Circuits”, 4th Ed., New Jersey:
Prentice Hall, 1989

The Resistor color code chartB


APPENDIX Capacitance

ABC .abc

AB x 10C pF 0.abc F

Potentiometer

A Var B
EEN1026 Electronics II: Experiment

Log Scale
The distance in a decade of the log scale in the figure below is x mm. Since log 101 = 0, it is
used as a refernce point (0 mm) in the linear scale. Then, the reading 10 is located at x mm
and the reading 0.1 is located at –x mm. For a reading F, it is located at [1og10(F)]*x mm.
E.g.:
Reading 0.25 is located at [1og10(0.25)]*x mm = -0.602x mm
Reading 2.5 is loacted at [1og10(2.5)]*x mm = 0.398x mm
Reading 25 is located at [1og10(25)]*x mm = 1.398x mm (not shown in the figure)
Reading 250 is located at [1og10(250)]*x mm = 2.398x mm (not shown)

Conversely, a point at z mm location is read as 10 z / x .


E.g.:
-0.3x mm is read as 10(-0.3x/x) = 0.501
0.6x mm is read as 10(0.6x/x) = 3.98
1.5x mm is read as 10(1.5x/x) = 31.6 (not shown)
2.7x mm is read as 10(2.7x/x) = 501 (not shown)

-0.3x
-x -0.602x 0 0.398x0.6x x
Linear scale
(mm)

Log scale
0.1 0.2 0.3 0.5 1 2 3 4 5 6 78910
0.4 0.6 (unit)
0.25 0.7 0.9 2.5 3.98
0.501 0.8

Balachandran 14 October 2011


EEN1026 Electronics II: Experiment

Appendix C: Breadboard Internal Connections

Internal
Horizontally connected connections Horizontally connected

+VCC

0.1  F

Vertically
connected 8 7 6 5

555

Vertically 1 2 3 4

connected

0V
GND

Internal
connections
General mistakes:
The legs of the resistors and the transistor are shorted
by the breadboard internal connections.
Multimedia University FOE
Balachandran 14 October 2011
EEN1026 Electronics II
Experiment EB1: FET Amplifier Frequency Response
Lab Report
(Submit your report on the same day immediately after the experiment)
(Student who is found copying experimental results, discussions and conclusions from
other group will get zero mark in the overall experiment evaluation.)

Name: ________________________ Student I.D.: _______________ Date: __________

Majoring: ____________________ Group: ____________ Table No.: ____________

1. Table E1: Measured resistance values


R1 R2 RD RS RL

[5 x 1 mark]
3. VDD(meas) = ________ V, VG(cal) = ________ V [2
marks]

4. Table E2: Measured DC voltages


VG VD VS

[3 marks]
7. Graph E1: vin and vL waveforms at 200 kHz

Time base : ______ s/div, CH1 (vin) : ______ V/div, CH2 (vL) : ______ V/div

CH1 & CH2


ground

[5 marks]

VL ( pp )
8. Av   ________ at 200 kHz
Vin ( pp )
[1 mark] Instructor’s Check (after step 8)

Sign : ________ Time : _______

Remarks:
EEN1026 Electronics II Experiment EB1

9. Table E3: Measure VL(pp) and Vin(pp), and calculated AV

f /kHz 1 2 5 10 20 40 60 80 100 200 500 550


VL(pp) /V
Vin(pp) /V
Av (dB)
[6 marks]
10. Graph E2: Av versus frequency

[5 marks]
1
11. f LD ( cal )  = _________ Hz
2  RL  RD  C D
f LD ( meas ) = _________ Hz

12. f HD ( meas ) = _________ kHz

13. BW = fHD – fLD = _________ kHz


fo  f LD f HD = _________ kHz

[5 x 1 mark]

Instructor’s Check (after step 13)

Sign : ________ Time : _______

Remarks:

2
EEN1026 Electronics II Experiment EB1

Questions
1. Identify the sources of error in the calculated VG(cal).
________________________________________________________________________
________________________________________________________________________

2. Calculate the actual DC currents flowing through RD and RS, respectively, IRD and IRS
(calculation steps must be included). Explain why they are the same.
________________________________________________________________________
________________________________________________________________________

3. What is the measured Q-point value (VGSQ, VDSQ, IDQ) of the JFET amplifier circuit?
Analyse and compare this with the calculated one.
________________________________________________________________________
________________________________________________________________________

4. Estimate the lower cutoff frequency of the input circuit, fLG (show your calculation steps).

________________________________________________________________________

5. Estimate the total output capacitance which determines the upper cutoff frequency fHD
________________________________________________________________________

[5 x 3 marks]

Discussion

1. Identify how the vin and vL waveforms in Step 7 are related in terms of positive and
negative peak voltages, waveform shapes and phase shift.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

3
EEN1026 Electronics II Experiment EB1

2. Describe the Av versus frequency characteristic.


________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

3. Explain the difference between the calculated fLD(cal) and the measured fLD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

4. Propose why fHD cannot be calculated and as to what factor determines this fHD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
[4 x 4 marks]

Conclusion
The N-channel JFET amplifier circuit has a lower cutoff frequency of ______________ and
an upper cutoff frequency of ______________. The lower cutoff frequency is mainly caused
by ________________________________________________________________________
___________________________________________________________________________
and the upper cutoff frequency is mainly caused by ______________________________
___________________________________________________________________________
_____________________________________ because ______________________________
___________________________________________________________________________
__________________________________________________________________________.

[7 marks]

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