FFT Verilog

/*
* This source file contains a Verilog description of an IP core

* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 16 complex words per cycle

// Throughput: one transform every 16 cycles
// Latency: 165 cycles
// Resources required:
// 120 multipliers (8 x 8 bit)
// 324 adders (8 x 8 bit)
// 96 RAMs (32 words, 16 bits per word)
// 32 RAMs (8 words, 16 bits per word)
// 24 ROMs (16 words, 8 bits per word)
// Generated on Tue Apr 03 08:08:38 EDT 2018
// Latency: 165 clock cycles

// Throughput: 1 transform every 16 cycles
// We use an interleaved complex data format. X0 represents the

// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the

// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 16 cycles. This means that

// 16 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates

// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 165 cycles. This means that

// the 'next_out' will be asserted 165 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
module dft_testbench();
reg clk, reset, next;
wire next_out;
integer i, j, k, l, m;
reg [15:0] counter;
reg [7:0] in [31:0];
wire [7:0] X0;
wire [7:0] Y0;
wire [7:0] X1;
wire [7:0] Y1;
wire [7:0] X2;
wire [7:0] Y2;
wire [7:0] X3;
wire [7:0] Y3;
wire [7:0] X4;
wire [7:0] Y4;
wire [7:0] X5;
wire [7:0] Y5;
wire [7:0] X6;
wire [7:0] Y6;
wire [7:0] X7;
wire [7:0] Y7;
wire [7:0] X8;
wire [7:0] Y8;
wire [7:0] X9;
wire [7:0] Y9;
wire [7:0] X10;
wire [7:0] Y10;
wire [7:0] X11;
wire [7:0] Y11;
wire [7:0] X12;
wire [7:0] Y12;
wire [7:0] X13;
wire [7:0] Y13;
wire [7:0] X14;
wire [7:0] Y14;
wire [7:0] X15;
wire [7:0] Y15;
wire [7:0] X16;
wire [7:0] Y16;
wire [7:0] X17;
wire [7:0] Y17;
wire [7:0] X18;
wire [7:0] Y18;
wire [7:0] X19;
wire [7:0] Y19;
wire [7:0] X20;
wire [7:0] Y20;
wire [7:0] X21;
wire [7:0] Y21;
wire [7:0] X22;
wire [7:0] Y22;
wire [7:0] X23;
wire [7:0] Y23;
wire [7:0] X24;
wire [7:0] Y24;
wire [7:0] X25;
wire [7:0] Y25;
wire [7:0] X26;
wire [7:0] Y26;
wire [7:0] X27;
wire [7:0] Y27;
wire [7:0] X28;
wire [7:0] Y28;
wire [7:0] X29;
wire [7:0] Y29;
wire [7:0] X30;
wire [7:0] Y30;
wire [7:0] X31;
wire [7:0] Y31;
reg clrCnt;
assign X0 = in[0];
assign X1 = in[1];
assign X2 = in[2];
assign X3 = in[3];
assign X4 = in[4];
assign X5 = in[5];
assign X6 = in[6];
assign X7 = in[7];
assign X8 = in[8];
assign X9 = in[9];
assign X10 = in[10];
initial clk = 0;
always #10000 clk = ~clk;
// Instantiate top-level module of core 'X' signals are system inputs

// and 'Y' signals are system outputs
dft_top dft_top_instance (.clk(clk), .reset(reset), .next(next),
.next_out(next_out),
.X0(X0), .Y0(Y0),
.X1(X1), .Y1(Y1),
.X2(X2), .Y2(Y2),
.X3(X3), .Y3(Y3),
.X4(X4), .Y4(Y4),
.X5(X5), .Y5(Y5),
.X6(X6), .Y6(Y6),
.X7(X7), .Y7(Y7),
.X8(X8), .Y8(Y8),
.X9(X9), .Y9(Y9),
.X10(X10), .Y10(Y10),
.X11(X11), .Y11(Y11),
.X12(X12), .Y12(Y12),
.X13(X13), .Y13(Y13),
.X14(X14), .Y14(Y14),
.X15(X15), .Y15(Y15),
.X16(X16), .Y16(Y16),
.X17(X17), .Y17(Y17),
.X18(X18), .Y18(Y18),
.X19(X19), .Y19(Y19),
.X20(X20), .Y20(Y20),
.X21(X21), .Y21(Y21),
.X22(X22), .Y22(Y22),
.X23(X23), .Y23(Y23),
.X24(X24), .Y24(Y24),
.X25(X25), .Y25(Y25),
.X26(X26), .Y26(Y26),
.X27(X27), .Y27(Y27),
.X28(X28), .Y28(Y28),
.X29(X29), .Y29(Y29),
.X30(X30), .Y30(Y30),
.X31(X31), .Y31(Y31));
// You can use this counter to verify that the gap and latency are as expected.
always @(posedge clk) begin
if (clrCnt) counter <= 0;
else counter <= counter+1;
end
initial begin
@(posedge clk);
@(posedge clk);
// On the next cycle, begin loading input vector.

next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// The 256 complex data points enter the system over 16 cycles
for (j=0; j < 15; j = j+1) begin
// Input: 16 complex words per cycle
for (k=0; k < 32; k = k+1) begin
in[k] <= j*32 + k;
end
@(posedge clk);
end
j = 15;
for (k=0; k < 32; k = k+1) begin
in[k] <= j*32 + k;
end
@(posedge clk);
// Wait until the next data vector can be entered
while (counter < 14)
@(posedge clk);
// On the next cycle, we will start the next data vector

next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// Start entering next input vector

for (j=0; j < 15; j = j+1) begin
// Input 32 words per cycle
for (k=0; k < 32; k = k+1) begin
in[k] <= 512 + j*32 + k;
end
@(posedge clk);
end
j = 15;
for (k=0; k < 32; k = k+1) begin
in[k] <= 512 + j*32 + k;
end
end
initial begin
// set initial values
in[0] <= 0;
in[1] <= 0;
in[2] <= 0;
in[3] <= 0;
in[4] <= 0;
in[5] <= 0;
in[6] <= 0;
in[7] <= 0;
in[8] <= 0;
in[9] <= 0;
in[10] <= 0;
in[11] <= 0;
in[12] <= 0;
in[13] <= 0;
in[14] <= 0;
in[15] <= 0;
in[16] <= 0;
in[17] <= 0;
in[18] <= 0;
in[19] <= 0;
in[20] <= 0;
in[21] <= 0;
in[22] <= 0;
in[23] <= 0;
in[24] <= 0;
in[25] <= 0;
in[26] <= 0;
in[27] <= 0;
in[28] <= 0;
in[29] <= 0;
in[30] <= 0;
in[31] <= 0;
next <= 0;
reset <= 0;
@(posedge clk);
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
// Wait until next_out goes high, then wait one clock cycle and begin
receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 1---");
for (m=0; m < 15; m=m+1) begin

$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$display("%x", Y4);
$display("%x", Y5);
$display("%x", Y6);
$display("%x", Y7);
$display("%x", Y8);
$display("%x", Y9);
$display("%x", Y10);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$display("%x", Y4);
$display("%x", Y5);
$display("%x", Y6);
$display("%x", Y7);
$display("%x", Y8);
$display("%x", Y9);
// Wait until next_out goes high, then wait one clock cycle and begin
receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 2---");
for (m=0; m < 15; m=m+1) begin

$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$display("%x", Y4);
$display("%x", Y5);
$display("%x", Y6);
$display("%x", Y7);
$display("%x", Y8);
$display("%x", Y9);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$display("%x", Y4);
$display("%x", Y5);
$display("%x", Y6);
$display("%x", Y7);
$display("%x", Y8);
$display("%x", Y9);
$finish;
end
endmodule
// Latency: 165
// Gap: 16
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
input clk, reset, next;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
wire [7:0] t0_0;

wire [7:0] t0_1;
wire [7:0] t0_2;
wire [7:0] t0_3;
wire [7:0] t0_4;
wire [7:0] t0_5;
wire [7:0] t0_6;
wire [7:0] t0_7;
wire [7:0] t0_8;
wire [7:0] t0_9;
wire [7:0] t0_10;
wire [7:0] t0_11;
wire [7:0] t0_12;
wire [7:0] t0_13;
wire [7:0] t0_14;
wire [7:0] t0_15;
wire [7:0] t0_16;
wire [7:0] t0_17;
wire [7:0] t0_18;
wire [7:0] t0_19;
wire [7:0] t0_20;
wire [7:0] t0_21;
wire [7:0] t0_22;
wire [7:0] t0_23;
wire [7:0] t0_24;
wire [7:0] t0_25;
wire [7:0] t0_26;
wire [7:0] t0_27;
wire [7:0] t0_28;
wire [7:0] t0_29;
wire [7:0] t0_30;
wire [7:0] t0_31;
wire next_0;
wire [7:0] t1_0;
wire [7:0] t1_1;
wire [7:0] t1_2;
wire [7:0] t1_3;
wire [7:0] t1_4;
wire [7:0] t1_5;
wire [7:0] t1_6;
wire [7:0] t1_7;
wire [7:0] t1_8;
wire [7:0] t1_9;
wire [7:0] t1_10;
wire [7:0] t1_11;
wire [7:0] t1_12;
wire [7:0] t1_13;
wire [7:0] t1_14;
wire [7:0] t1_15;
wire [7:0] t1_16;
wire [7:0] t1_17;
wire [7:0] t1_18;
wire [7:0] t1_19;
wire [7:0] t1_20;
wire [7:0] t1_21;
wire [7:0] t1_22;
wire [7:0] t1_23;
wire [7:0] t1_24;
wire [7:0] t1_25;
wire [7:0] t1_26;
wire [7:0] t1_27;
wire [7:0] t1_28;
wire [7:0] t1_29;
wire [7:0] t1_30;
wire [7:0] t1_31;
wire next_1;
wire [7:0] t2_0;
wire [7:0] t2_1;
wire [7:0] t2_2;
wire [7:0] t2_3;
wire [7:0] t2_4;
wire [7:0] t2_5;
wire [7:0] t2_6;
wire [7:0] t2_7;
wire [7:0] t2_8;
wire [7:0] t2_9;
wire [7:0] t2_10;
wire [7:0] t2_11;
wire [7:0] t2_12;
wire [7:0] t2_13;
wire [7:0] t2_14;
wire [7:0] t2_15;
wire [7:0] t2_16;
wire [7:0] t2_17;
wire [7:0] t2_18;
wire [7:0] t2_19;
wire [7:0] t2_20;
wire [7:0] t2_21;
wire [7:0] t2_22;
wire [7:0] t2_23;
wire [7:0] t2_24;
wire [7:0] t2_25;
wire [7:0] t2_26;
wire [7:0] t2_27;
wire [7:0] t2_28;
wire [7:0] t2_29;
wire [7:0] t2_30;
wire [7:0] t2_31;
wire next_2;
wire [7:0] t3_0;
wire [7:0] t3_1;
wire [7:0] t3_2;
wire [7:0] t3_3;
wire [7:0] t3_4;
wire [7:0] t3_5;
wire [7:0] t3_6;
wire [7:0] t3_7;
wire [7:0] t3_8;
wire [7:0] t3_9;
wire [7:0] t3_10;
wire [7:0] t3_11;
wire [7:0] t3_12;
wire [7:0] t3_13;
wire [7:0] t3_14;
wire [7:0] t3_15;
wire [7:0] t3_16;
wire [7:0] t3_17;
wire [7:0] t3_18;
wire [7:0] t3_19;
wire [7:0] t3_20;
wire [7:0] t3_21;
wire [7:0] t3_22;
wire [7:0] t3_23;
wire [7:0] t3_24;
wire [7:0] t3_25;
wire [7:0] t3_26;
wire [7:0] t3_27;
wire [7:0] t3_28;
wire [7:0] t3_29;
wire [7:0] t3_30;
wire [7:0] t3_31;
wire next_3;
wire [7:0] t4_0;
wire [7:0] t4_1;
wire [7:0] t4_2;
wire [7:0] t4_3;
wire [7:0] t4_4;
wire [7:0] t4_5;
wire [7:0] t4_6;
wire [7:0] t4_7;
wire [7:0] t4_8;
wire [7:0] t4_9;
wire [7:0] t4_10;
wire [7:0] t4_11;
wire [7:0] t4_12;
wire [7:0] t4_13;
wire [7:0] t4_14;
wire [7:0] t4_15;
wire [7:0] t4_16;
wire [7:0] t4_17;
wire [7:0] t4_18;
wire [7:0] t4_19;
wire [7:0] t4_20;
wire [7:0] t4_21;
wire [7:0] t4_22;
wire [7:0] t4_23;
wire [7:0] t4_24;
wire [7:0] t4_25;
wire [7:0] t4_26;
wire [7:0] t4_27;
wire [7:0] t4_28;
wire [7:0] t4_29;
wire [7:0] t4_30;
wire [7:0] t4_31;
wire next_4;
wire [7:0] t5_0;
wire [7:0] t5_1;
wire [7:0] t5_2;
wire [7:0] t5_3;
wire [7:0] t5_4;
wire [7:0] t5_5;
wire [7:0] t5_6;
wire [7:0] t5_7;
wire [7:0] t5_8;
wire [7:0] t5_9;
wire [7:0] t5_10;
wire [7:0] t5_11;
wire [7:0] t5_12;
wire [7:0] t5_13;
wire [7:0] t5_14;
wire [7:0] t5_15;
wire [7:0] t5_16;
wire [7:0] t5_17;
wire [7:0] t5_18;
wire [7:0] t5_19;
wire [7:0] t5_20;
wire [7:0] t5_21;
wire [7:0] t5_22;
wire [7:0] t5_23;
wire [7:0] t5_24;
wire [7:0] t5_25;
wire [7:0] t5_26;
wire [7:0] t5_27;
wire [7:0] t5_28;
wire [7:0] t5_29;
wire [7:0] t5_30;
wire [7:0] t5_31;
wire next_5;
wire [7:0] t6_0;
wire [7:0] t6_1;
wire [7:0] t6_2;
wire [7:0] t6_3;
wire [7:0] t6_4;
wire [7:0] t6_5;
wire [7:0] t6_6;
wire [7:0] t6_7;
wire [7:0] t6_8;
wire [7:0] t6_9;
wire [7:0] t6_10;
wire [7:0] t6_11;
wire [7:0] t6_12;
wire [7:0] t6_13;
wire [7:0] t6_14;
wire [7:0] t6_15;
wire [7:0] t6_16;
wire [7:0] t6_17;
wire [7:0] t6_18;
wire [7:0] t6_19;
wire [7:0] t6_20;
wire [7:0] t6_21;
wire [7:0] t6_22;
wire [7:0] t6_23;
wire [7:0] t6_24;
wire [7:0] t6_25;
wire [7:0] t6_26;
wire [7:0] t6_27;
wire [7:0] t6_28;
wire [7:0] t6_29;
wire [7:0] t6_30;
wire [7:0] t6_31;
wire next_6;
wire [7:0] t7_0;
wire [7:0] t7_1;
wire [7:0] t7_2;
wire [7:0] t7_3;
wire [7:0] t7_4;
wire [7:0] t7_5;
wire [7:0] t7_6;
wire [7:0] t7_7;
wire [7:0] t7_8;
wire [7:0] t7_9;
wire [7:0] t7_10;
wire [7:0] t7_11;
wire [7:0] t7_12;
wire [7:0] t7_13;
wire [7:0] t7_14;
wire [7:0] t7_15;
wire [7:0] t7_16;
wire [7:0] t7_17;
wire [7:0] t7_18;
wire [7:0] t7_19;
wire [7:0] t7_20;
wire [7:0] t7_21;
wire [7:0] t7_22;
wire [7:0] t7_23;
wire [7:0] t7_24;
wire [7:0] t7_25;
wire [7:0] t7_26;
wire [7:0] t7_27;
wire [7:0] t7_28;
wire [7:0] t7_29;
wire [7:0] t7_30;
wire [7:0] t7_31;
wire next_7;
wire [7:0] t8_0;
wire [7:0] t8_1;
wire [7:0] t8_2;
wire [7:0] t8_3;
wire [7:0] t8_4;
wire [7:0] t8_5;
wire [7:0] t8_6;
wire [7:0] t8_7;
wire [7:0] t8_8;
wire [7:0] t8_9;
wire [7:0] t8_10;
wire [7:0] t8_11;
wire [7:0] t8_12;
wire [7:0] t8_13;
wire [7:0] t8_14;
wire [7:0] t8_15;
wire [7:0] t8_16;
wire [7:0] t8_17;
wire [7:0] t8_18;
wire [7:0] t8_19;
wire [7:0] t8_20;
wire [7:0] t8_21;
wire [7:0] t8_22;
wire [7:0] t8_23;
wire [7:0] t8_24;
wire [7:0] t8_25;
wire [7:0] t8_26;
wire [7:0] t8_27;
wire [7:0] t8_28;
wire [7:0] t8_29;
wire [7:0] t8_30;
wire [7:0] t8_31;
wire next_8;
wire [7:0] t9_0;
wire [7:0] t9_1;
wire [7:0] t9_2;
wire [7:0] t9_3;
wire [7:0] t9_4;
wire [7:0] t9_5;
wire [7:0] t9_6;
wire [7:0] t9_7;
wire [7:0] t9_8;
wire [7:0] t9_9;
wire [7:0] t9_10;
wire [7:0] t9_11;
wire [7:0] t9_12;
wire [7:0] t9_13;
wire [7:0] t9_14;
wire [7:0] t9_15;
wire [7:0] t9_16;
wire [7:0] t9_17;
wire [7:0] t9_18;
wire [7:0] t9_19;
wire [7:0] t9_20;
wire [7:0] t9_21;
wire [7:0] t9_22;
wire [7:0] t9_23;
wire [7:0] t9_24;
wire [7:0] t9_25;
wire [7:0] t9_26;
wire [7:0] t9_27;
wire [7:0] t9_28;
wire [7:0] t9_29;
wire [7:0] t9_30;
wire [7:0] t9_31;
wire next_9;
assign t0_0 = X0;
assign Y0 = t9_0;
assign t0_1 = X1;
assign Y1 = t9_1;
assign t0_2 = X2;
assign Y2 = t9_2;
assign t0_3 = X3;
assign Y3 = t9_3;
assign t0_4 = X4;
assign Y4 = t9_4;
assign t0_5 = X5;
assign Y5 = t9_5;
assign t0_6 = X6;
assign Y6 = t9_6;
assign t0_7 = X7;
assign Y7 = t9_7;
assign t0_8 = X8;
assign Y8 = t9_8;
assign t0_9 = X9;
assign Y9 = t9_9;
assign t0_10 = X10;
assign Y10 = t9_10;
assign t0_11 = X11;
assign Y11 = t9_11;
assign t0_12 = X12;
assign Y12 = t9_12;
assign t0_13 = X13;
assign Y13 = t9_13;
assign t0_14 = X14;
assign Y14 = t9_14;
assign t0_15 = X15;
assign Y15 = t9_15;
assign t0_16 = X16;
assign Y16 = t9_16;
assign t0_17 = X17;
assign Y17 = t9_17;
assign t0_18 = X18;
assign Y18 = t9_18;
assign t0_19 = X19;
assign Y19 = t9_19;
assign t0_20 = X20;
assign Y20 = t9_20;
assign t0_21 = X21;
assign Y21 = t9_21;
assign t0_22 = X22;
assign Y22 = t9_22;
assign t0_23 = X23;
assign Y23 = t9_23;
assign t0_24 = X24;
assign Y24 = t9_24;
assign t0_25 = X25;
assign Y25 = t9_25;
assign t0_26 = X26;
assign Y26 = t9_26;
assign t0_27 = X27;
assign Y27 = t9_27;
assign t0_28 = X28;
assign Y28 = t9_28;
assign t0_29 = X29;
assign Y29 = t9_29;
assign t0_30 = X30;
assign Y30 = t9_30;
assign t0_31 = X31;
assign Y31 = t9_31;
assign next_0 = next;
assign next_out = next_9;
// latency=39, gap=16
rc17612 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3),
.X4(t0_4), .Y4(t1_4),
.X5(t0_5), .Y5(t1_5),
.X6(t0_6), .Y6(t1_6),
.X7(t0_7), .Y7(t1_7),
.X8(t0_8), .Y8(t1_8),
.X9(t0_9), .Y9(t1_9),
.X10(t0_10), .Y10(t1_10),
.X11(t0_11), .Y11(t1_11),
.X12(t0_12), .Y12(t1_12),
.X13(t0_13), .Y13(t1_13),
.X14(t0_14), .Y14(t1_14),
.X15(t0_15), .Y15(t1_15),
.X16(t0_16), .Y16(t1_16),
.X17(t0_17), .Y17(t1_17),
.X18(t0_18), .Y18(t1_18),
.X19(t0_19), .Y19(t1_19),
.X20(t0_20), .Y20(t1_20),
.X21(t0_21), .Y21(t1_21),
.X22(t0_22), .Y22(t1_22),
.X23(t0_23), .Y23(t1_23),
.X24(t0_24), .Y24(t1_24),
.X25(t0_25), .Y25(t1_25),
.X26(t0_26), .Y26(t1_26),
.X27(t0_27), .Y27(t1_27),
.X28(t0_28), .Y28(t1_28),
.X29(t0_29), .Y29(t1_29),
.X30(t0_30), .Y30(t1_30),
.X31(t0_31), .Y31(t1_31));
codeBlock17614 stage1(.clk(clk), .reset(reset), .next_in(next_1),
.next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3),
.X4_in(t1_4), .Y4(t2_4),
.X5_in(t1_5), .Y5(t2_5),
.X6_in(t1_6), .Y6(t2_6),
.X7_in(t1_7), .Y7(t2_7),
.X8_in(t1_8), .Y8(t2_8),
.X9_in(t1_9), .Y9(t2_9),
.X10_in(t1_10), .Y10(t2_10),
.X11_in(t1_11), .Y11(t2_11),
.X12_in(t1_12), .Y12(t2_12),
.X13_in(t1_13), .Y13(t2_13),
.X14_in(t1_14), .Y14(t2_14),
.X15_in(t1_15), .Y15(t2_15),
.X16_in(t1_16), .Y16(t2_16),
.X17_in(t1_17), .Y17(t2_17),
.X18_in(t1_18), .Y18(t2_18),
.X19_in(t1_19), .Y19(t2_19),
.X20_in(t1_20), .Y20(t2_20),
.X21_in(t1_21), .Y21(t2_21),
.X22_in(t1_22), .Y22(t2_22),
.X23_in(t1_23), .Y23(t2_23),
.X24_in(t1_24), .Y24(t2_24),
.X25_in(t1_25), .Y25(t2_25),
.X26_in(t1_26), .Y26(t2_26),
.X27_in(t1_27), .Y27(t2_27),
.X28_in(t1_28), .Y28(t2_28),
.X29_in(t1_29), .Y29(t2_29),
.X30_in(t1_30), .Y30(t2_30),
.X31_in(t1_31), .Y31(t2_31));
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3),
.X4(t2_4), .Y4(t3_4),
.X5(t2_5), .Y5(t3_5),
.X6(t2_6), .Y6(t3_6),
.X7(t2_7), .Y7(t3_7),
.X8(t2_8), .Y8(t3_8),
.X9(t2_9), .Y9(t3_9),
.X10(t2_10), .Y10(t3_10),
.X11(t2_11), .Y11(t3_11),
.X12(t2_12), .Y12(t3_12),
.X13(t2_13), .Y13(t3_13),
.X14(t2_14), .Y14(t3_14),
.X15(t2_15), .Y15(t3_15),
.X16(t2_16), .Y16(t3_16),
.X17(t2_17), .Y17(t3_17),
.X18(t2_18), .Y18(t3_18),
.X19(t2_19), .Y19(t3_19),
.X20(t2_20), .Y20(t3_20),
.X21(t2_21), .Y21(t3_21),
.X22(t2_22), .Y22(t3_22),
.X23(t2_23), .Y23(t3_23),
.X24(t2_24), .Y24(t3_24),
.X25(t2_25), .Y25(t3_25),
.X26(t2_26), .Y26(t3_26),
.X27(t2_27), .Y27(t3_27),
.X28(t2_28), .Y28(t3_28),
.X29(t2_29), .Y29(t3_29),
.X30(t2_30), .Y30(t3_30),
.X31(t2_31), .Y31(t3_31));
DirSum_20265 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3),
.X4(t3_4), .Y4(t4_4),
.X5(t3_5), .Y5(t4_5),
.X6(t3_6), .Y6(t4_6),
.X7(t3_7), .Y7(t4_7),
.X8(t3_8), .Y8(t4_8),
.X9(t3_9), .Y9(t4_9),
.X10(t3_10), .Y10(t4_10),
.X11(t3_11), .Y11(t4_11),
.X12(t3_12), .Y12(t4_12),
.X13(t3_13), .Y13(t4_13),
.X14(t3_14), .Y14(t4_14),
.X15(t3_15), .Y15(t4_15),
.X16(t3_16), .Y16(t4_16),
.X17(t3_17), .Y17(t4_17),
.X18(t3_18), .Y18(t4_18),
.X19(t3_19), .Y19(t4_19),
.X20(t3_20), .Y20(t4_20),
.X21(t3_21), .Y21(t4_21),
.X22(t3_22), .Y22(t4_22),
.X23(t3_23), .Y23(t4_23),
.X24(t3_24), .Y24(t4_24),
.X25(t3_25), .Y25(t4_25),
.X26(t3_26), .Y26(t4_26),
.X27(t3_27), .Y27(t4_27),
.X28(t3_28), .Y28(t4_28),
.X29(t3_29), .Y29(t4_29),
.X30(t3_30), .Y30(t4_30),
.X31(t3_31), .Y31(t4_31));
.next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3),
.X4_in(t4_4), .Y4(t5_4),
.X5_in(t4_5), .Y5(t5_5),
.X6_in(t4_6), .Y6(t5_6),
.X7_in(t4_7), .Y7(t5_7),
.X8_in(t4_8), .Y8(t5_8),
.X9_in(t4_9), .Y9(t5_9),
.X10_in(t4_10), .Y10(t5_10),
.X11_in(t4_11), .Y11(t5_11),
.X12_in(t4_12), .Y12(t5_12),
.X13_in(t4_13), .Y13(t5_13),
.X14_in(t4_14), .Y14(t5_14),
.X15_in(t4_15), .Y15(t5_15),
.X16_in(t4_16), .Y16(t5_16),
.X17_in(t4_17), .Y17(t5_17),
.X18_in(t4_18), .Y18(t5_18),
.X19_in(t4_19), .Y19(t5_19),
.X20_in(t4_20), .Y20(t5_20),
.X21_in(t4_21), .Y21(t5_21),
.X22_in(t4_22), .Y22(t5_22),
.X23_in(t4_23), .Y23(t5_23),
.X24_in(t4_24), .Y24(t5_24),
.X25_in(t4_25), .Y25(t5_25),
.X26_in(t4_26), .Y26(t5_26),
.X27_in(t4_27), .Y27(t5_27),
.X28_in(t4_28), .Y28(t5_28),
.X29_in(t4_29), .Y29(t5_29),
.X30_in(t4_30), .Y30(t5_30),
.X31_in(t4_31), .Y31(t5_31));
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3),
.X4(t5_4), .Y4(t6_4),
.X5(t5_5), .Y5(t6_5),
.X6(t5_6), .Y6(t6_6),
.X7(t5_7), .Y7(t6_7),
.X8(t5_8), .Y8(t6_8),
.X9(t5_9), .Y9(t6_9),
.X10(t5_10), .Y10(t6_10),
.X11(t5_11), .Y11(t6_11),
.X12(t5_12), .Y12(t6_12),
.X13(t5_13), .Y13(t6_13),
.X14(t5_14), .Y14(t6_14),
.X15(t5_15), .Y15(t6_15),
.X16(t5_16), .Y16(t6_16),
.X17(t5_17), .Y17(t6_17),
.X18(t5_18), .Y18(t6_18),
.X19(t5_19), .Y19(t6_19),
.X20(t5_20), .Y20(t6_20),
.X21(t5_21), .Y21(t6_21),
.X22(t5_22), .Y22(t6_22),
.X23(t5_23), .Y23(t6_23),
.X24(t5_24), .Y24(t6_24),
.X25(t5_25), .Y25(t6_25),
.X26(t5_26), .Y26(t6_26),
.X27(t5_27), .Y27(t6_27),
.X28(t5_28), .Y28(t6_28),
.X29(t5_29), .Y29(t6_29),
.X30(t5_30), .Y30(t6_30),
.X31(t5_31), .Y31(t6_31));
DirSum_23302 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3),
.X4(t6_4), .Y4(t7_4),
.X5(t6_5), .Y5(t7_5),
.X6(t6_6), .Y6(t7_6),
.X7(t6_7), .Y7(t7_7),
.X8(t6_8), .Y8(t7_8),
.X9(t6_9), .Y9(t7_9),
.X10(t6_10), .Y10(t7_10),
.X11(t6_11), .Y11(t7_11),
.X12(t6_12), .Y12(t7_12),
.X13(t6_13), .Y13(t7_13),
.X14(t6_14), .Y14(t7_14),
.X15(t6_15), .Y15(t7_15),
.X16(t6_16), .Y16(t7_16),
.X17(t6_17), .Y17(t7_17),
.X18(t6_18), .Y18(t7_18),
.X19(t6_19), .Y19(t7_19),
.X20(t6_20), .Y20(t7_20),
.X21(t6_21), .Y21(t7_21),
.X22(t6_22), .Y22(t7_22),
.X23(t6_23), .Y23(t7_23),
.X24(t6_24), .Y24(t7_24),
.X25(t6_25), .Y25(t7_25),
.X26(t6_26), .Y26(t7_26),
.X27(t6_27), .Y27(t7_27),
.X28(t6_28), .Y28(t7_28),
.X29(t6_29), .Y29(t7_29),
.X30(t6_30), .Y30(t7_30),
.X31(t6_31), .Y31(t7_31));
.next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3),
.X4_in(t7_4), .Y4(t8_4),
.X5_in(t7_5), .Y5(t8_5),
.X6_in(t7_6), .Y6(t8_6),
.X7_in(t7_7), .Y7(t8_7),
.X8_in(t7_8), .Y8(t8_8),
.X9_in(t7_9), .Y9(t8_9),
.X10_in(t7_10), .Y10(t8_10),
.X11_in(t7_11), .Y11(t8_11),
.X12_in(t7_12), .Y12(t8_12),
.X13_in(t7_13), .Y13(t8_13),
.X14_in(t7_14), .Y14(t8_14),
.X15_in(t7_15), .Y15(t8_15),
.X16_in(t7_16), .Y16(t8_16),
.X17_in(t7_17), .Y17(t8_17),
.X18_in(t7_18), .Y18(t8_18),
.X19_in(t7_19), .Y19(t8_19),
.X20_in(t7_20), .Y20(t8_20),
.X21_in(t7_21), .Y21(t8_21),
.X22_in(t7_22), .Y22(t8_22),
.X23_in(t7_23), .Y23(t8_23),
.X24_in(t7_24), .Y24(t8_24),
.X25_in(t7_25), .Y25(t8_25),
.X26_in(t7_26), .Y26(t8_26),
.X27_in(t7_27), .Y27(t8_27),
.X28_in(t7_28), .Y28(t8_28),
.X29_in(t7_29), .Y29(t8_29),
.X30_in(t7_30), .Y30(t8_30),
.X31_in(t7_31), .Y31(t8_31));
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3),
.X4(t8_4), .Y4(t9_4),
.X5(t8_5), .Y5(t9_5),
.X6(t8_6), .Y6(t9_6),
.X7(t8_7), .Y7(t9_7),
.X8(t8_8), .Y8(t9_8),
.X9(t8_9), .Y9(t9_9),
.X10(t8_10), .Y10(t9_10),
.X11(t8_11), .Y11(t9_11),
.X12(t8_12), .Y12(t9_12),
.X13(t8_13), .Y13(t9_13),
.X14(t8_14), .Y14(t9_14),
.X15(t8_15), .Y15(t9_15),
.X16(t8_16), .Y16(t9_16),
.X17(t8_17), .Y17(t9_17),
.X18(t8_18), .Y18(t9_18),
.X19(t8_19), .Y19(t9_19),
.X20(t8_20), .Y20(t9_20),
.X21(t8_21), .Y21(t9_21),
.X22(t8_22), .Y22(t9_22),
.X23(t8_23), .Y23(t9_23),
.X24(t8_24), .Y24(t9_24),
.X25(t8_25), .Y25(t9_25),
.X26(t8_26), .Y26(t9_26),
.X27(t8_27), .Y27(t9_27),
.X28(t8_28), .Y28(t9_28),
.X29(t8_29), .Y29(t9_29),
.X30(t8_30), .Y30(t9_30),
.X31(t8_31), .Y31(t9_31));
endmodule
// Latency: 39
// Gap: 16
module rc17612(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
wire [15:0] t0;

wire [15:0] s0;
assign t0 = {X0, X1};
wire [15:0] t1;
wire [15:0] s1;
wire [15:0] t2;
wire [15:0] s2;
wire [15:0] t3;
wire [15:0] s3;
wire [15:0] t4;
wire [15:0] s4;
wire [15:0] t5;
wire [15:0] s5;
assign t5 = {X10, X11};
wire [15:0] t6;
wire [15:0] s6;
assign t6 = {X12, X13};
wire [15:0] t7;
wire [15:0] s7;
assign t7 = {X14, X15};
wire [15:0] t8;
wire [15:0] s8;
assign t8 = {X16, X17};
wire [15:0] t9;
wire [15:0] s9;
assign t9 = {X18, X19};
wire [15:0] t10;
wire [15:0] s10;
assign t10 = {X20, X21};
wire [15:0] t11;
wire [15:0] s11;
assign t11 = {X22, X23};
wire [15:0] t12;
wire [15:0] s12;
assign t12 = {X24, X25};
wire [15:0] t13;
wire [15:0] s13;
assign t13 = {X26, X27};
wire [15:0] t14;
wire [15:0] s14;
assign t14 = {X28, X29};
wire [15:0] t15;
wire [15:0] s15;
assign t15 = {X30, X31};
assign Y0 = s0[15:8];
assign Y1 = s0[7:0];
assign Y2 = s1[15:8];
assign Y4 = s2[15:8];
assign Y6 = s3[15:8];
assign Y8 = s4[15:8];
assign Y10 = s5[15:8];
assign Y11 = s5[7:0];
assign Y12 = s6[15:8];
assign Y13 = s6[7:0];
assign Y14 = s7[15:8];
assign Y15 = s7[7:0];
assign Y16 = s8[15:8];
assign Y17 = s8[7:0];
assign Y18 = s9[15:8];
assign Y19 = s9[7:0];
assign Y20 = s10[15:8];
assign Y21 = s10[7:0];
assign Y22 = s11[15:8];
assign Y23 = s11[7:0];
assign Y24 = s12[15:8];
assign Y25 = s12[7:0];
assign Y26 = s13[15:8];
assign Y27 = s13[7:0];
assign Y28 = s14[15:8];
assign Y29 = s14[7:0];
assign Y30 = s15[15:8];
assign Y31 = s15[7:0];
perm17610 instPerm27493(.x0(t0), .y0(s0),

.x1(t1), .y1(s1),
.x2(t2), .y2(s2),
.x3(t3), .y3(s3),
.x4(t4), .y4(s4),
.x5(t5), .y5(s5),
.x6(t6), .y6(s6),
.x7(t7), .y7(s7),
.x8(t8), .y8(s8),
.x9(t9), .y9(s9),
.x10(t10), .y10(s10),
.x11(t11), .y11(s11),
.x12(t12), .y12(s12),
.x13(t13), .y13(s13),
.x14(t14), .y14(s14),
.x15(t15), .y15(s15),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet17610(itr, clk, ct

, x0, y0
, x1, y1
, x2, y2
, x3, y3
, x4, y4
, x5, y5
, x6, y6
, x7, y7
, x8, y8
, x9, y9
, x10, y10
, x11, y11
, x12, y12
, x13, y13
, x14, y14
, x15, y15
);
parameter width = 16;
input [3:0] ct;

input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
wire [width-1:0] t0_0, t0_1, t0_2, t0_3, t0_4, t0_5, t0_6, t0_7, t0_8, t0_9,
t0_10, t0_11, t0_12, t0_13, t0_14, t0_15;
t1_10, t1_11, t1_12, t1_13, t1_14, t1_15;
t2_10, t2_11, t2_12, t2_13, t2_14, t2_15;
reg [width-1:0] t3_0, t3_1, t3_2, t3_3, t3_4, t3_5, t3_6, t3_7, t3_8, t3_9,
t3_10, t3_11, t3_12, t3_13, t3_14, t3_15;
t4_10, t4_11, t4_12, t4_13, t4_14, t4_15;
t5_10, t5_11, t5_12, t5_13, t5_14, t5_15;
t6_10, t6_11, t6_12, t6_13, t6_14, t6_15;
t7_10, t7_11, t7_12, t7_13, t7_14, t7_15;
t8_10, t8_11, t8_12, t8_13, t8_14, t8_15;
t9_10, t9_11, t9_12, t9_13, t9_14, t9_15;
wire [width-1:0] t10_0, t10_1, t10_2, t10_3, t10_4, t10_5, t10_6, t10_7, t10_8,
t10_9, t10_10, t10_11, t10_12, t10_13, t10_14, t10_15;
reg [width-1:0] t11_0, t11_1, t11_2, t11_3, t11_4, t11_5, t11_6, t11_7, t11_8,
t11_9, t11_10, t11_11, t11_12, t11_13, t11_14, t11_15;
t12_9, t12_10, t12_11, t12_12, t12_13, t12_14, t12_15;
t13_9, t13_10, t13_11, t13_12, t13_13, t13_14, t13_15;
reg [31:0] control;

case(ct)
4'd0: control <= 32'b11111111111111111010101011110000;
4'd1: control <= 32'b11111111111111111010101011110000;
4'd2: control <= 32'b00000000111111111010101011110000;
4'd3: control <= 32'b00000000111111111010101011110000;
4'd4: control <= 32'b11111111000000001010101011110000;
4'd5: control <= 32'b11111111000000001010101011110000;
4'd6: control <= 32'b00000000000000001010101011110000;
4'd7: control <= 32'b00000000000000001010101011110000;
4'd8: control <= 32'b11111111111111110101010100001111;
4'd9: control <= 32'b11111111111111110101010100001111;
4'd10: control <= 32'b00000000111111110101010100001111;
4'd11: control <= 32'b00000000111111110101010100001111;
4'd12: control <= 32'b11111111000000000101010100001111;
4'd13: control <= 32'b11111111000000000101010100001111;
4'd14: control <= 32'b00000000000000000101010100001111;
4'd15: control <= 32'b00000000000000000101010100001111;
endcase
end
// synthesis attribute rom_style of control is "distributed"

reg [31:0] control0;
control0 <= control;
control1 <= control0;
end
assign t0_0 = x0;
assign t0_1 = x8;
assign t0_2 = x1;
assign t0_3 = x9;
assign t0_4 = x2;
assign t0_5 = x10;
assign t0_6 = x3;
assign t0_7 = x11;
assign t0_8 = x4;
assign t0_9 = x12;
assign t0_10 = x5;
assign t0_11 = x13;
assign t0_12 = x6;
assign t0_13 = x14;
assign t0_14 = x7;
assign t0_15 = x15;
assign t1_0 = t0_0;
assign t1_1 = t0_1;
assign t1_2 = t0_2;
assign t1_3 = t0_3;
assign t1_4 = t0_4;
assign t1_5 = t0_5;
assign t1_6 = t0_6;
assign t1_7 = t0_7;
assign t1_8 = t0_9;
assign t1_9 = t0_8;
assign t1_10 = t0_11;
assign t1_11 = t0_10;
assign t1_12 = t0_13;
assign t1_13 = t0_12;
assign t1_14 = t0_15;
assign t1_15 = t0_14;
assign t2_0 = t1_0;
assign t2_1 = t1_8;
assign t2_2 = t1_1;
assign t2_3 = t1_9;
assign t2_4 = t1_2;
assign t2_5 = t1_10;
assign t2_6 = t1_3;
assign t2_8 = t1_4;
assign t2_11 = t1_13;
assign t2_13 = t1_14;
assign t2_15 = t1_15;
t3_0 <= t2_0;
t3_1 <= t2_1;
t3_2 <= t2_2;
t3_3 <= t2_3;
t3_4 <= t2_4;
t3_5 <= t2_5;
t3_6 <= t2_6;
t3_7 <= t2_7;
t3_8 <= t2_8;
t3_9 <= t2_9;
t3_10 <= t2_10;
t3_11 <= t2_11;
t3_12 <= t2_12;
t3_13 <= t2_13;
t3_14 <= t2_14;
t3_15 <= t2_15;
end
assign t4_0 = t3_0;
assign t4_1 = t3_8;
assign t4_2 = t3_1;
assign t4_3 = t3_9;
assign t4_4 = t3_2;
assign t4_6 = t3_3;
assign t4_8 = t3_4;
assign t4_11 = t3_13;
assign t4_13 = t3_14;
assign t4_15 = t3_15;
assign t5_0 = t4_0;
assign t5_1 = t4_1;
assign t5_2 = t4_2;
assign t5_3 = t4_3;
assign t5_4 = t4_4;
assign t5_5 = t4_5;
assign t5_6 = t4_6;
assign t5_7 = t4_7;
assign t5_8 = t4_8;
assign t5_9 = t4_9;
assign t5_10 = t4_10;
assign t5_11 = t4_11;
assign t5_12 = t4_12;
assign t5_13 = t4_13;
assign t5_14 = t4_14;
assign t5_15 = t4_15;
assign t6_0 = t5_0;
assign t6_1 = t5_8;
assign t6_2 = t5_1;
assign t6_3 = t5_9;
assign t6_4 = t5_2;
assign t6_6 = t5_3;
assign t6_8 = t5_4;
assign t6_11 = t5_13;
assign t6_13 = t5_14;
assign t6_15 = t5_15;
t7_0 <= (control1[31] == 0) ? t6_0 : t6_1;
t7_1 <= (control1[31] == 0) ? t6_1 : t6_0;
t7_2 <= (control1[30] == 0) ? t6_2 : t6_3;
t7_3 <= (control1[30] == 0) ? t6_3 : t6_2;
t7_4 <= (control1[29] == 0) ? t6_4 : t6_5;
t7_5 <= (control1[29] == 0) ? t6_5 : t6_4;
t7_6 <= (control1[28] == 0) ? t6_6 : t6_7;
t7_7 <= (control1[28] == 0) ? t6_7 : t6_6;
t7_8 <= (control1[27] == 0) ? t6_8 : t6_9;
t7_9 <= (control1[27] == 0) ? t6_9 : t6_8;
t7_10 <= (control1[26] == 0) ? t6_10 : t6_11;
t7_11 <= (control1[26] == 0) ? t6_11 : t6_10;
t7_12 <= (control1[25] == 0) ? t6_12 : t6_13;
t7_13 <= (control1[25] == 0) ? t6_13 : t6_12;
t7_14 <= (control1[24] == 0) ? t6_14 : t6_15;
t7_15 <= (control1[24] == 0) ? t6_15 : t6_14;
end
assign t8_0 = t7_0;
assign t8_1 = t7_2;
assign t8_2 = t7_4;
assign t8_3 = t7_6;
assign t8_4 = t7_8;
assign t8_8 = t7_1;
assign t8_9 = t7_3;
assign t8_13 = t7_11;
assign t8_14 = t7_13;
assign t8_15 = t7_15;
assign t9_0 = (control2[23] == 0) ? t8_0 : t8_1;
assign t10_5 = t9_10;
assign t10_6 = t9_12;
assign t10_7 = t9_14;
assign t10_10 = t9_5;
assign t10_11 = t9_7;
assign t10_12 = t9_9;
assign t10_13 = t9_11;
assign t10_14 = t9_13;
assign t10_15 = t9_15;
t11_0 <= (control2[15] == 0) ? t10_0 : t10_1;
t11_1 <= (control2[15] == 0) ? t10_1 : t10_0;
t11_2 <= (control2[14] == 0) ? t10_2 : t10_3;
t11_3 <= (control2[14] == 0) ? t10_3 : t10_2;
t11_4 <= (control2[13] == 0) ? t10_4 : t10_5;
t11_5 <= (control2[13] == 0) ? t10_5 : t10_4;
t11_6 <= (control2[12] == 0) ? t10_6 : t10_7;
t11_7 <= (control2[12] == 0) ? t10_7 : t10_6;
t11_8 <= (control2[11] == 0) ? t10_8 : t10_9;
t11_9 <= (control2[11] == 0) ? t10_9 : t10_8;
t11_10 <= (control2[10] == 0) ? t10_10 : t10_11;
t11_11 <= (control2[10] == 0) ? t10_11 : t10_10;
t11_12 <= (control2[9] == 0) ? t10_12 : t10_13;
t11_13 <= (control2[9] == 0) ? t10_13 : t10_12;
t11_14 <= (control2[8] == 0) ? t10_14 : t10_15;
t11_15 <= (control2[8] == 0) ? t10_15 : t10_14;
end
assign t12_0 = t11_0;
assign t12_1 = t11_2;
assign t12_2 = t11_4;
assign t12_3 = t11_6;
assign t12_4 = t11_8;
assign t12_5 = t11_10;
assign t12_6 = t11_12;
assign t12_7 = t11_14;
assign t12_8 = t11_1;
assign t12_9 = t11_3;
assign t12_10 = t11_5;
assign t12_11 = t11_7;
assign t12_12 = t11_9;
assign t12_13 = t11_11;
assign t12_14 = t11_13;
assign t12_15 = t11_15;
t13_0 <= (control3[7] == 0) ? t12_0 : t12_1;
t13_1 <= (control3[7] == 0) ? t12_1 : t12_0;
t13_2 <= (control3[6] == 0) ? t12_2 : t12_3;
t13_3 <= (control3[6] == 0) ? t12_3 : t12_2;
t13_4 <= (control3[5] == 0) ? t12_4 : t12_5;
t13_5 <= (control3[5] == 0) ? t12_5 : t12_4;
t13_6 <= (control3[4] == 0) ? t12_6 : t12_7;
t13_7 <= (control3[4] == 0) ? t12_7 : t12_6;
t13_8 <= (control3[3] == 0) ? t12_8 : t12_9;
t13_9 <= (control3[3] == 0) ? t12_9 : t12_8;
t13_10 <= (control3[2] == 0) ? t12_10 : t12_11;
t13_11 <= (control3[2] == 0) ? t12_11 : t12_10;
t13_12 <= (control3[1] == 0) ? t12_12 : t12_13;
t13_13 <= (control3[1] == 0) ? t12_13 : t12_12;
t13_14 <= (control3[0] == 0) ? t12_14 : t12_15;
t13_15 <= (control3[0] == 0) ? t12_15 : t12_14;
end
y0 <= t13_0;
y1 <= t13_2;
y2 <= t13_4;
y3 <= t13_6;
y4 <= t13_8;
y5 <= t13_10;
y6 <= t13_12;
y7 <= t13_14;
y8 <= t13_1;
y9 <= t13_3;
y10 <= t13_5;
y11 <= t13_7;
y12 <= t13_9;
y13 <= t13_11;
y14 <= t13_13;
y15 <= t13_15;
end
endmodule
// Latency: 39
// Gap: 16
module perm17610(clk, next, reset, next_out,
x0, y0,
x1, y1,
x2, y2,
x3, y3,
x4, y4,
x5, y5,
x6, y6,
x7, y7,
x8, y8,
x9, y9,
x10, y10,
x11, y11,
x12, y12,
x13, y13,
x14, y14,
x15, y15);
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 4;

output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;

reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;

assign tm0 = 0;
shiftRegFIFO #(6, 1) shiftFIFO_27498(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_27499(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0},

{outFlip0, s1rd0}, s1wr_en, clk);
nextReg #(15, 4) nextReg_27510(.X(next), .Y(next2), .reset(reset), .clk(clk));

shiftRegFIFO #(7, 1) shiftFIFO_27511(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_27514(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_27515(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_27518(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(6, 1) shiftFIFO_27521(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;

assign muxCycle = s1rdloc;
shiftRegFIFO #(6, 4) shiftFIFO_27526(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;

assign readInt = (state2 == 1);
shiftRegFIFO #(7, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0},

{outFlip1, s2rdloc}, s2wr_en, clk);
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
end
endcase
end
end

state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
end
endcase
end
end

state3 <= 0;
outFlip1 <= 0;
end
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
state3 <= 1;
end
endcase
end
end
case({tm0_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 14;
{1'd0, 4'd1}: s1rd0 <= 15;
{1'd0, 4'd2}: s1rd0 <= 12;
{1'd0, 4'd3}: s1rd0 <= 13;
{1'd0, 4'd4}: s1rd0 <= 10;
{1'd0, 4'd5}: s1rd0 <= 11;
{1'd0, 4'd6}: s1rd0 <= 8;
{1'd0, 4'd7}: s1rd0 <= 9;
{1'd0, 4'd8}: s1rd0 <= 6;
{1'd0, 4'd9}: s1rd0 <= 7;
{1'd0, 4'd10}: s1rd0 <= 4;
{1'd0, 4'd11}: s1rd0 <= 5;
{1'd0, 4'd12}: s1rd0 <= 2;
{1'd0, 4'd13}: s1rd0 <= 3;
{1'd0, 4'd14}: s1rd0 <= 0;
{1'd0, 4'd15}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"

{1'd0, 4'd0}: s1rd1 <= 12;
{1'd0, 4'd1}: s1rd1 <= 13;
{1'd0, 4'd2}: s1rd1 <= 14;
{1'd0, 4'd3}: s1rd1 <= 15;
{1'd0, 4'd4}: s1rd1 <= 8;
{1'd0, 4'd5}: s1rd1 <= 9;
{1'd0, 4'd6}: s1rd1 <= 10;
{1'd0, 4'd7}: s1rd1 <= 11;
{1'd0, 4'd8}: s1rd1 <= 4;
{1'd0, 4'd9}: s1rd1 <= 5;
{1'd0, 4'd10}: s1rd1 <= 6;
{1'd0, 4'd11}: s1rd1 <= 7;
{1'd0, 4'd12}: s1rd1 <= 0;
{1'd0, 4'd13}: s1rd1 <= 1;
{1'd0, 4'd14}: s1rd1 <= 2;
{1'd0, 4'd15}: s1rd1 <= 3;
endcase
end

{1'd0, 4'd0}: s1rd2 <= 10;
{1'd0, 4'd1}: s1rd2 <= 11;
{1'd0, 4'd2}: s1rd2 <= 8;
{1'd0, 4'd3}: s1rd2 <= 9;
{1'd0, 4'd4}: s1rd2 <= 14;
{1'd0, 4'd5}: s1rd2 <= 15;
{1'd0, 4'd6}: s1rd2 <= 12;
{1'd0, 4'd7}: s1rd2 <= 13;
{1'd0, 4'd8}: s1rd2 <= 2;
{1'd0, 4'd9}: s1rd2 <= 3;
{1'd0, 4'd10}: s1rd2 <= 0;
{1'd0, 4'd11}: s1rd2 <= 1;
{1'd0, 4'd12}: s1rd2 <= 6;
{1'd0, 4'd13}: s1rd2 <= 7;
{1'd0, 4'd14}: s1rd2 <= 4;
{1'd0, 4'd15}: s1rd2 <= 5;
endcase
end

{1'd0, 4'd0}: s1rd3 <= 8;
{1'd0, 4'd1}: s1rd3 <= 9;
{1'd0, 4'd2}: s1rd3 <= 10;
{1'd0, 4'd3}: s1rd3 <= 11;
{1'd0, 4'd4}: s1rd3 <= 12;
{1'd0, 4'd5}: s1rd3 <= 13;
{1'd0, 4'd6}: s1rd3 <= 14;
{1'd0, 4'd7}: s1rd3 <= 15;
{1'd0, 4'd8}: s1rd3 <= 0;
{1'd0, 4'd9}: s1rd3 <= 1;
{1'd0, 4'd10}: s1rd3 <= 2;
{1'd0, 4'd11}: s1rd3 <= 3;
{1'd0, 4'd12}: s1rd3 <= 4;
{1'd0, 4'd13}: s1rd3 <= 5;
{1'd0, 4'd14}: s1rd3 <= 6;
{1'd0, 4'd15}: s1rd3 <= 7;
endcase
end

{1'd0, 4'd0}: s1rd4 <= 14;
{1'd0, 4'd1}: s1rd4 <= 15;
{1'd0, 4'd2}: s1rd4 <= 12;
{1'd0, 4'd3}: s1rd4 <= 13;
{1'd0, 4'd4}: s1rd4 <= 10;
{1'd0, 4'd5}: s1rd4 <= 11;
{1'd0, 4'd6}: s1rd4 <= 8;
{1'd0, 4'd7}: s1rd4 <= 9;
{1'd0, 4'd8}: s1rd4 <= 6;
{1'd0, 4'd9}: s1rd4 <= 7;
{1'd0, 4'd10}: s1rd4 <= 4;
{1'd0, 4'd11}: s1rd4 <= 5;
{1'd0, 4'd12}: s1rd4 <= 2;
{1'd0, 4'd13}: s1rd4 <= 3;
{1'd0, 4'd14}: s1rd4 <= 0;
{1'd0, 4'd15}: s1rd4 <= 1;
endcase
end

{1'd0, 4'd0}: s1rd5 <= 12;
{1'd0, 4'd1}: s1rd5 <= 13;
{1'd0, 4'd2}: s1rd5 <= 14;
{1'd0, 4'd3}: s1rd5 <= 15;
{1'd0, 4'd4}: s1rd5 <= 8;
{1'd0, 4'd5}: s1rd5 <= 9;
{1'd0, 4'd6}: s1rd5 <= 10;
{1'd0, 4'd7}: s1rd5 <= 11;
{1'd0, 4'd8}: s1rd5 <= 4;
{1'd0, 4'd9}: s1rd5 <= 5;
{1'd0, 4'd10}: s1rd5 <= 6;
{1'd0, 4'd11}: s1rd5 <= 7;
{1'd0, 4'd12}: s1rd5 <= 0;
{1'd0, 4'd13}: s1rd5 <= 1;
{1'd0, 4'd14}: s1rd5 <= 2;
{1'd0, 4'd15}: s1rd5 <= 3;
endcase
end

{1'd0, 4'd0}: s1rd6 <= 10;
{1'd0, 4'd1}: s1rd6 <= 11;
{1'd0, 4'd2}: s1rd6 <= 8;
{1'd0, 4'd3}: s1rd6 <= 9;
{1'd0, 4'd4}: s1rd6 <= 14;
{1'd0, 4'd5}: s1rd6 <= 15;
{1'd0, 4'd6}: s1rd6 <= 12;
{1'd0, 4'd7}: s1rd6 <= 13;
{1'd0, 4'd8}: s1rd6 <= 2;
{1'd0, 4'd9}: s1rd6 <= 3;
{1'd0, 4'd10}: s1rd6 <= 0;
{1'd0, 4'd11}: s1rd6 <= 1;
{1'd0, 4'd12}: s1rd6 <= 6;
{1'd0, 4'd13}: s1rd6 <= 7;
{1'd0, 4'd14}: s1rd6 <= 4;
{1'd0, 4'd15}: s1rd6 <= 5;
endcase
end

{1'd0, 4'd0}: s1rd7 <= 8;
{1'd0, 4'd1}: s1rd7 <= 9;
{1'd0, 4'd2}: s1rd7 <= 10;
{1'd0, 4'd3}: s1rd7 <= 11;
{1'd0, 4'd4}: s1rd7 <= 12;
{1'd0, 4'd5}: s1rd7 <= 13;
{1'd0, 4'd6}: s1rd7 <= 14;
{1'd0, 4'd7}: s1rd7 <= 15;
{1'd0, 4'd8}: s1rd7 <= 0;
{1'd0, 4'd9}: s1rd7 <= 1;
{1'd0, 4'd10}: s1rd7 <= 2;
{1'd0, 4'd11}: s1rd7 <= 3;
{1'd0, 4'd12}: s1rd7 <= 4;
{1'd0, 4'd13}: s1rd7 <= 5;
{1'd0, 4'd14}: s1rd7 <= 6;
{1'd0, 4'd15}: s1rd7 <= 7;
endcase
end

{1'd0, 4'd0}: s1rd8 <= 6;
{1'd0, 4'd1}: s1rd8 <= 7;
{1'd0, 4'd2}: s1rd8 <= 4;
{1'd0, 4'd3}: s1rd8 <= 5;
{1'd0, 4'd4}: s1rd8 <= 2;
{1'd0, 4'd5}: s1rd8 <= 3;
{1'd0, 4'd6}: s1rd8 <= 0;
{1'd0, 4'd7}: s1rd8 <= 1;
{1'd0, 4'd8}: s1rd8 <= 14;
{1'd0, 4'd9}: s1rd8 <= 15;
{1'd0, 4'd10}: s1rd8 <= 12;
{1'd0, 4'd11}: s1rd8 <= 13;
{1'd0, 4'd12}: s1rd8 <= 10;
{1'd0, 4'd13}: s1rd8 <= 11;
{1'd0, 4'd14}: s1rd8 <= 8;
{1'd0, 4'd15}: s1rd8 <= 9;
endcase
end

{1'd0, 4'd0}: s1rd9 <= 4;
{1'd0, 4'd1}: s1rd9 <= 5;
{1'd0, 4'd2}: s1rd9 <= 6;
{1'd0, 4'd3}: s1rd9 <= 7;
{1'd0, 4'd4}: s1rd9 <= 0;
{1'd0, 4'd5}: s1rd9 <= 1;
{1'd0, 4'd6}: s1rd9 <= 2;
{1'd0, 4'd7}: s1rd9 <= 3;
{1'd0, 4'd8}: s1rd9 <= 12;
{1'd0, 4'd9}: s1rd9 <= 13;
{1'd0, 4'd10}: s1rd9 <= 14;
{1'd0, 4'd11}: s1rd9 <= 15;
{1'd0, 4'd12}: s1rd9 <= 8;
{1'd0, 4'd13}: s1rd9 <= 9;
{1'd0, 4'd14}: s1rd9 <= 10;
{1'd0, 4'd15}: s1rd9 <= 11;
endcase
end

{1'd0, 4'd0}: s1rd10 <= 2;
{1'd0, 4'd1}: s1rd10 <= 3;
{1'd0, 4'd2}: s1rd10 <= 0;
{1'd0, 4'd3}: s1rd10 <= 1;
{1'd0, 4'd4}: s1rd10 <= 6;
{1'd0, 4'd5}: s1rd10 <= 7;
{1'd0, 4'd6}: s1rd10 <= 4;
{1'd0, 4'd7}: s1rd10 <= 5;
{1'd0, 4'd8}: s1rd10 <= 10;
{1'd0, 4'd9}: s1rd10 <= 11;
{1'd0, 4'd10}: s1rd10 <= 8;
{1'd0, 4'd11}: s1rd10 <= 9;
{1'd0, 4'd12}: s1rd10 <= 14;
{1'd0, 4'd13}: s1rd10 <= 15;
{1'd0, 4'd14}: s1rd10 <= 12;
{1'd0, 4'd15}: s1rd10 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd11 <= 0;
{1'd0, 4'd1}: s1rd11 <= 1;
{1'd0, 4'd2}: s1rd11 <= 2;
{1'd0, 4'd3}: s1rd11 <= 3;
{1'd0, 4'd4}: s1rd11 <= 4;
{1'd0, 4'd5}: s1rd11 <= 5;
{1'd0, 4'd6}: s1rd11 <= 6;
{1'd0, 4'd7}: s1rd11 <= 7;
{1'd0, 4'd8}: s1rd11 <= 8;
{1'd0, 4'd9}: s1rd11 <= 9;
{1'd0, 4'd10}: s1rd11 <= 10;
{1'd0, 4'd11}: s1rd11 <= 11;
{1'd0, 4'd12}: s1rd11 <= 12;
{1'd0, 4'd13}: s1rd11 <= 13;
{1'd0, 4'd14}: s1rd11 <= 14;
{1'd0, 4'd15}: s1rd11 <= 15;
endcase
end

{1'd0, 4'd0}: s1rd12 <= 6;
{1'd0, 4'd1}: s1rd12 <= 7;
{1'd0, 4'd2}: s1rd12 <= 4;
{1'd0, 4'd3}: s1rd12 <= 5;
{1'd0, 4'd4}: s1rd12 <= 2;
{1'd0, 4'd5}: s1rd12 <= 3;
{1'd0, 4'd6}: s1rd12 <= 0;
{1'd0, 4'd7}: s1rd12 <= 1;
{1'd0, 4'd8}: s1rd12 <= 14;
{1'd0, 4'd9}: s1rd12 <= 15;
{1'd0, 4'd10}: s1rd12 <= 12;
{1'd0, 4'd11}: s1rd12 <= 13;
{1'd0, 4'd12}: s1rd12 <= 10;
{1'd0, 4'd13}: s1rd12 <= 11;
{1'd0, 4'd14}: s1rd12 <= 8;
{1'd0, 4'd15}: s1rd12 <= 9;
endcase
end

{1'd0, 4'd0}: s1rd13 <= 4;
{1'd0, 4'd1}: s1rd13 <= 5;
{1'd0, 4'd2}: s1rd13 <= 6;
{1'd0, 4'd3}: s1rd13 <= 7;
{1'd0, 4'd4}: s1rd13 <= 0;
{1'd0, 4'd5}: s1rd13 <= 1;
{1'd0, 4'd6}: s1rd13 <= 2;
{1'd0, 4'd7}: s1rd13 <= 3;
{1'd0, 4'd8}: s1rd13 <= 12;
{1'd0, 4'd9}: s1rd13 <= 13;
{1'd0, 4'd10}: s1rd13 <= 14;
{1'd0, 4'd11}: s1rd13 <= 15;
{1'd0, 4'd12}: s1rd13 <= 8;
{1'd0, 4'd13}: s1rd13 <= 9;
{1'd0, 4'd14}: s1rd13 <= 10;
{1'd0, 4'd15}: s1rd13 <= 11;
endcase
end

{1'd0, 4'd0}: s1rd14 <= 2;
{1'd0, 4'd1}: s1rd14 <= 3;
{1'd0, 4'd2}: s1rd14 <= 0;
{1'd0, 4'd3}: s1rd14 <= 1;
{1'd0, 4'd4}: s1rd14 <= 6;
{1'd0, 4'd5}: s1rd14 <= 7;
{1'd0, 4'd6}: s1rd14 <= 4;
{1'd0, 4'd7}: s1rd14 <= 5;
{1'd0, 4'd8}: s1rd14 <= 10;
{1'd0, 4'd9}: s1rd14 <= 11;
{1'd0, 4'd10}: s1rd14 <= 8;
{1'd0, 4'd11}: s1rd14 <= 9;
{1'd0, 4'd12}: s1rd14 <= 14;
{1'd0, 4'd13}: s1rd14 <= 15;
{1'd0, 4'd14}: s1rd14 <= 12;
{1'd0, 4'd15}: s1rd14 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd15 <= 0;
{1'd0, 4'd1}: s1rd15 <= 1;
{1'd0, 4'd2}: s1rd15 <= 2;
{1'd0, 4'd3}: s1rd15 <= 3;
{1'd0, 4'd4}: s1rd15 <= 4;
{1'd0, 4'd5}: s1rd15 <= 5;
{1'd0, 4'd6}: s1rd15 <= 6;
{1'd0, 4'd7}: s1rd15 <= 7;
{1'd0, 4'd8}: s1rd15 <= 8;
{1'd0, 4'd9}: s1rd15 <= 9;
{1'd0, 4'd10}: s1rd15 <= 10;
{1'd0, 4'd11}: s1rd15 <= 11;
{1'd0, 4'd12}: s1rd15 <= 12;
{1'd0, 4'd13}: s1rd15 <= 13;
{1'd0, 4'd14}: s1rd15 <= 14;
{1'd0, 4'd15}: s1rd15 <= 15;
endcase
end

swNet17610 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1, t2, s2, t3, s3, t4, s4, t5,
s5, t6, s6, t7, s7, t8, s8, t9, s9, t10, s10, t11, s11, t12, s12, t13, s13, t14,
s14, t15, s15);

case({tm0_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 13;
{1'd0, 4'd1}: s2wr0 <= 15;
{1'd0, 4'd2}: s2wr0 <= 9;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 5;
{1'd0, 4'd5}: s2wr0 <= 7;
{1'd0, 4'd6}: s2wr0 <= 1;
{1'd0, 4'd7}: s2wr0 <= 3;
{1'd0, 4'd8}: s2wr0 <= 12;
{1'd0, 4'd9}: s2wr0 <= 14;
{1'd0, 4'd10}: s2wr0 <= 8;
{1'd0, 4'd11}: s2wr0 <= 10;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 6;
{1'd0, 4'd14}: s2wr0 <= 0;
{1'd0, 4'd15}: s2wr0 <= 2;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"

{1'd0, 4'd0}: s2wr1 <= 9;
{1'd0, 4'd1}: s2wr1 <= 11;
{1'd0, 4'd2}: s2wr1 <= 13;
{1'd0, 4'd3}: s2wr1 <= 15;
{1'd0, 4'd4}: s2wr1 <= 1;
{1'd0, 4'd5}: s2wr1 <= 3;
{1'd0, 4'd6}: s2wr1 <= 5;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 10;
{1'd0, 4'd10}: s2wr1 <= 12;
{1'd0, 4'd11}: s2wr1 <= 14;
{1'd0, 4'd12}: s2wr1 <= 0;
{1'd0, 4'd13}: s2wr1 <= 2;
{1'd0, 4'd14}: s2wr1 <= 4;
{1'd0, 4'd15}: s2wr1 <= 6;

{1'd0, 4'd0}: s2wr2 <= 5;
{1'd0, 4'd1}: s2wr2 <= 7;
{1'd0, 4'd2}: s2wr2 <= 1;
{1'd0, 4'd3}: s2wr2 <= 3;
{1'd0, 4'd4}: s2wr2 <= 13;
{1'd0, 4'd5}: s2wr2 <= 15;
{1'd0, 4'd6}: s2wr2 <= 9;
{1'd0, 4'd7}: s2wr2 <= 11;
{1'd0, 4'd8}: s2wr2 <= 4;
{1'd0, 4'd9}: s2wr2 <= 6;
{1'd0, 4'd10}: s2wr2 <= 0;
{1'd0, 4'd11}: s2wr2 <= 2;
{1'd0, 4'd12}: s2wr2 <= 12;
{1'd0, 4'd13}: s2wr2 <= 14;
{1'd0, 4'd14}: s2wr2 <= 8;
{1'd0, 4'd15}: s2wr2 <= 10;

{1'd0, 4'd0}: s2wr3 <= 1;
{1'd0, 4'd1}: s2wr3 <= 3;
{1'd0, 4'd2}: s2wr3 <= 5;
{1'd0, 4'd3}: s2wr3 <= 7;
{1'd0, 4'd4}: s2wr3 <= 9;
{1'd0, 4'd5}: s2wr3 <= 11;
{1'd0, 4'd6}: s2wr3 <= 13;
{1'd0, 4'd7}: s2wr3 <= 15;
{1'd0, 4'd8}: s2wr3 <= 0;
{1'd0, 4'd9}: s2wr3 <= 2;
{1'd0, 4'd10}: s2wr3 <= 4;
{1'd0, 4'd11}: s2wr3 <= 6;
{1'd0, 4'd12}: s2wr3 <= 8;
{1'd0, 4'd13}: s2wr3 <= 10;
{1'd0, 4'd14}: s2wr3 <= 12;
{1'd0, 4'd15}: s2wr3 <= 14;

{1'd0, 4'd0}: s2wr4 <= 12;
{1'd0, 4'd1}: s2wr4 <= 14;
{1'd0, 4'd2}: s2wr4 <= 8;
{1'd0, 4'd3}: s2wr4 <= 10;
{1'd0, 4'd4}: s2wr4 <= 4;
{1'd0, 4'd5}: s2wr4 <= 6;
{1'd0, 4'd6}: s2wr4 <= 0;
{1'd0, 4'd7}: s2wr4 <= 2;
{1'd0, 4'd8}: s2wr4 <= 13;
{1'd0, 4'd9}: s2wr4 <= 15;
{1'd0, 4'd10}: s2wr4 <= 9;
{1'd0, 4'd11}: s2wr4 <= 11;
{1'd0, 4'd12}: s2wr4 <= 5;
{1'd0, 4'd13}: s2wr4 <= 7;
{1'd0, 4'd14}: s2wr4 <= 1;
{1'd0, 4'd15}: s2wr4 <= 3;

{1'd0, 4'd0}: s2wr5 <= 8;
{1'd0, 4'd1}: s2wr5 <= 10;
{1'd0, 4'd2}: s2wr5 <= 12;
{1'd0, 4'd3}: s2wr5 <= 14;
{1'd0, 4'd4}: s2wr5 <= 0;
{1'd0, 4'd5}: s2wr5 <= 2;
{1'd0, 4'd6}: s2wr5 <= 4;
{1'd0, 4'd7}: s2wr5 <= 6;
{1'd0, 4'd8}: s2wr5 <= 9;
{1'd0, 4'd9}: s2wr5 <= 11;
{1'd0, 4'd10}: s2wr5 <= 13;
{1'd0, 4'd11}: s2wr5 <= 15;
{1'd0, 4'd12}: s2wr5 <= 1;
{1'd0, 4'd13}: s2wr5 <= 3;
{1'd0, 4'd14}: s2wr5 <= 5;
{1'd0, 4'd15}: s2wr5 <= 7;

{1'd0, 4'd0}: s2wr6 <= 4;
{1'd0, 4'd1}: s2wr6 <= 6;
{1'd0, 4'd2}: s2wr6 <= 0;
{1'd0, 4'd3}: s2wr6 <= 2;
{1'd0, 4'd4}: s2wr6 <= 12;
{1'd0, 4'd5}: s2wr6 <= 14;
{1'd0, 4'd6}: s2wr6 <= 8;
{1'd0, 4'd7}: s2wr6 <= 10;
{1'd0, 4'd8}: s2wr6 <= 5;
{1'd0, 4'd9}: s2wr6 <= 7;
{1'd0, 4'd10}: s2wr6 <= 1;
{1'd0, 4'd11}: s2wr6 <= 3;
{1'd0, 4'd12}: s2wr6 <= 13;
{1'd0, 4'd13}: s2wr6 <= 15;
{1'd0, 4'd14}: s2wr6 <= 9;
{1'd0, 4'd15}: s2wr6 <= 11;

{1'd0, 4'd0}: s2wr7 <= 0;
{1'd0, 4'd1}: s2wr7 <= 2;
{1'd0, 4'd2}: s2wr7 <= 4;
{1'd0, 4'd3}: s2wr7 <= 6;
{1'd0, 4'd4}: s2wr7 <= 8;
{1'd0, 4'd5}: s2wr7 <= 10;
{1'd0, 4'd6}: s2wr7 <= 12;
{1'd0, 4'd7}: s2wr7 <= 14;
{1'd0, 4'd8}: s2wr7 <= 1;
{1'd0, 4'd9}: s2wr7 <= 3;
{1'd0, 4'd10}: s2wr7 <= 5;
{1'd0, 4'd11}: s2wr7 <= 7;
{1'd0, 4'd12}: s2wr7 <= 9;
{1'd0, 4'd13}: s2wr7 <= 11;
{1'd0, 4'd14}: s2wr7 <= 13;
{1'd0, 4'd15}: s2wr7 <= 15;

{1'd0, 4'd0}: s2wr8 <= 13;
{1'd0, 4'd1}: s2wr8 <= 15;
{1'd0, 4'd2}: s2wr8 <= 9;
{1'd0, 4'd3}: s2wr8 <= 11;
{1'd0, 4'd4}: s2wr8 <= 5;
{1'd0, 4'd5}: s2wr8 <= 7;
{1'd0, 4'd6}: s2wr8 <= 1;
{1'd0, 4'd7}: s2wr8 <= 3;
{1'd0, 4'd8}: s2wr8 <= 12;
{1'd0, 4'd9}: s2wr8 <= 14;
{1'd0, 4'd10}: s2wr8 <= 8;
{1'd0, 4'd11}: s2wr8 <= 10;
{1'd0, 4'd12}: s2wr8 <= 4;
{1'd0, 4'd13}: s2wr8 <= 6;
{1'd0, 4'd14}: s2wr8 <= 0;
{1'd0, 4'd15}: s2wr8 <= 2;

{1'd0, 4'd0}: s2wr9 <= 9;
{1'd0, 4'd1}: s2wr9 <= 11;
{1'd0, 4'd2}: s2wr9 <= 13;
{1'd0, 4'd3}: s2wr9 <= 15;
{1'd0, 4'd4}: s2wr9 <= 1;
{1'd0, 4'd5}: s2wr9 <= 3;
{1'd0, 4'd6}: s2wr9 <= 5;
{1'd0, 4'd7}: s2wr9 <= 7;
{1'd0, 4'd8}: s2wr9 <= 8;
{1'd0, 4'd9}: s2wr9 <= 10;
{1'd0, 4'd10}: s2wr9 <= 12;
{1'd0, 4'd11}: s2wr9 <= 14;
{1'd0, 4'd12}: s2wr9 <= 0;
{1'd0, 4'd13}: s2wr9 <= 2;
{1'd0, 4'd14}: s2wr9 <= 4;
{1'd0, 4'd15}: s2wr9 <= 6;

{1'd0, 4'd0}: s2wr10 <= 5;
{1'd0, 4'd1}: s2wr10 <= 7;
{1'd0, 4'd2}: s2wr10 <= 1;
{1'd0, 4'd3}: s2wr10 <= 3;
{1'd0, 4'd4}: s2wr10 <= 13;
{1'd0, 4'd5}: s2wr10 <= 15;
{1'd0, 4'd6}: s2wr10 <= 9;
{1'd0, 4'd7}: s2wr10 <= 11;
{1'd0, 4'd8}: s2wr10 <= 4;
{1'd0, 4'd9}: s2wr10 <= 6;
{1'd0, 4'd10}: s2wr10 <= 0;
{1'd0, 4'd11}: s2wr10 <= 2;
{1'd0, 4'd12}: s2wr10 <= 12;
{1'd0, 4'd13}: s2wr10 <= 14;
{1'd0, 4'd14}: s2wr10 <= 8;
{1'd0, 4'd15}: s2wr10 <= 10;

{1'd0, 4'd0}: s2wr11 <= 1;
{1'd0, 4'd1}: s2wr11 <= 3;
{1'd0, 4'd2}: s2wr11 <= 5;
{1'd0, 4'd3}: s2wr11 <= 7;
{1'd0, 4'd4}: s2wr11 <= 9;
{1'd0, 4'd5}: s2wr11 <= 11;
{1'd0, 4'd6}: s2wr11 <= 13;
{1'd0, 4'd7}: s2wr11 <= 15;
{1'd0, 4'd8}: s2wr11 <= 0;
{1'd0, 4'd9}: s2wr11 <= 2;
{1'd0, 4'd10}: s2wr11 <= 4;
{1'd0, 4'd11}: s2wr11 <= 6;
{1'd0, 4'd12}: s2wr11 <= 8;
{1'd0, 4'd13}: s2wr11 <= 10;
{1'd0, 4'd14}: s2wr11 <= 12;
{1'd0, 4'd15}: s2wr11 <= 14;

{1'd0, 4'd0}: s2wr12 <= 12;
{1'd0, 4'd1}: s2wr12 <= 14;
{1'd0, 4'd2}: s2wr12 <= 8;
{1'd0, 4'd3}: s2wr12 <= 10;
{1'd0, 4'd4}: s2wr12 <= 4;
{1'd0, 4'd5}: s2wr12 <= 6;
{1'd0, 4'd6}: s2wr12 <= 0;
{1'd0, 4'd7}: s2wr12 <= 2;
{1'd0, 4'd8}: s2wr12 <= 13;
{1'd0, 4'd9}: s2wr12 <= 15;
{1'd0, 4'd10}: s2wr12 <= 9;
{1'd0, 4'd11}: s2wr12 <= 11;
{1'd0, 4'd12}: s2wr12 <= 5;
{1'd0, 4'd13}: s2wr12 <= 7;
{1'd0, 4'd14}: s2wr12 <= 1;
{1'd0, 4'd15}: s2wr12 <= 3;

{1'd0, 4'd0}: s2wr13 <= 8;
{1'd0, 4'd1}: s2wr13 <= 10;
{1'd0, 4'd2}: s2wr13 <= 12;
{1'd0, 4'd3}: s2wr13 <= 14;
{1'd0, 4'd4}: s2wr13 <= 0;
{1'd0, 4'd5}: s2wr13 <= 2;
{1'd0, 4'd6}: s2wr13 <= 4;
{1'd0, 4'd7}: s2wr13 <= 6;
{1'd0, 4'd8}: s2wr13 <= 9;
{1'd0, 4'd9}: s2wr13 <= 11;
{1'd0, 4'd10}: s2wr13 <= 13;
{1'd0, 4'd11}: s2wr13 <= 15;
{1'd0, 4'd12}: s2wr13 <= 1;
{1'd0, 4'd13}: s2wr13 <= 3;
{1'd0, 4'd14}: s2wr13 <= 5;
{1'd0, 4'd15}: s2wr13 <= 7;

{1'd0, 4'd0}: s2wr14 <= 4;
{1'd0, 4'd1}: s2wr14 <= 6;
{1'd0, 4'd2}: s2wr14 <= 0;
{1'd0, 4'd3}: s2wr14 <= 2;
{1'd0, 4'd4}: s2wr14 <= 12;
{1'd0, 4'd5}: s2wr14 <= 14;
{1'd0, 4'd6}: s2wr14 <= 8;
{1'd0, 4'd7}: s2wr14 <= 10;
{1'd0, 4'd8}: s2wr14 <= 5;
{1'd0, 4'd9}: s2wr14 <= 7;
{1'd0, 4'd10}: s2wr14 <= 1;
{1'd0, 4'd11}: s2wr14 <= 3;
{1'd0, 4'd12}: s2wr14 <= 13;
{1'd0, 4'd13}: s2wr14 <= 15;
{1'd0, 4'd14}: s2wr14 <= 9;
{1'd0, 4'd15}: s2wr14 <= 11;

{1'd0, 4'd0}: s2wr15 <= 0;
{1'd0, 4'd1}: s2wr15 <= 2;
{1'd0, 4'd2}: s2wr15 <= 4;
{1'd0, 4'd3}: s2wr15 <= 6;
{1'd0, 4'd4}: s2wr15 <= 8;
{1'd0, 4'd5}: s2wr15 <= 10;
{1'd0, 4'd6}: s2wr15 <= 12;
{1'd0, 4'd7}: s2wr15 <= 14;
{1'd0, 4'd8}: s2wr15 <= 1;
{1'd0, 4'd9}: s2wr15 <= 3;
{1'd0, 4'd10}: s2wr15 <= 5;
{1'd0, 4'd11}: s2wr15 <= 7;
{1'd0, 4'd12}: s2wr15 <= 9;
{1'd0, 4'd13}: s2wr15 <= 11;
{1'd0, 4'd14}: s2wr15 <= 13;
{1'd0, 4'd15}: s2wr15 <= 15;

endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;

input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];

out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;

input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];

out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);

parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];

integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin

for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);

parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin

count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 7
// Gap: 1
module codeBlock17614(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3,
X4_in, Y4,
X5_in, Y5,
X6_in, Y6,
X7_in, Y7,
X8_in, Y8,
X9_in, Y9,
X10_in, Y10,
X11_in, Y11,
X12_in, Y12,
X13_in, Y13,
X14_in, Y14,
X15_in, Y15,
X16_in, Y16,
X17_in, Y17,
X18_in, Y18,
X19_in, Y19,
X20_in, Y20,
X21_in, Y21,
X22_in, Y22,
X23_in, Y23,
X24_in, Y24,
X25_in, Y25,
X26_in, Y26,
X27_in, Y27,
X28_in, Y28,
X29_in, Y29,
X30_in, Y30,
X31_in, Y31);
output next_out;
input clk, reset, next_in;
reg next;
input [7:0] X0_in,

X1_in,
X2_in,
X3_in,
X4_in,
X5_in,
X6_in,
X7_in,
X8_in,
X9_in,
X10_in,
X11_in,
X12_in,
X13_in,
X14_in,
X15_in,
X16_in,
X17_in,
X18_in,
X19_in,
X20_in,
X21_in,
X22_in,
X23_in,
X24_in,
X25_in,
X26_in,
X27_in,
X28_in,
X29_in,
X30_in,
X31_in;
reg [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
shiftRegFIFO #(6, 1) shiftFIFO_27533(.X(next), .Y(next_out), .clk(clk));
wire signed [7:0] a1074;

wire signed [7:0] t1850;
reg signed [7:0] tm296;
wire signed [7:0] Y0;
wire signed [7:0] tm1;

assign tm1 = 8'h2d;
assign a1074 = X0;

assign a1075 = X8;
assign a1076 = X1;
assign a1077 = X9;
assign a1082 = X2;
assign a1083 = X10;
assign a1084 = X3;
assign a1085 = X11;
assign a1090 = X4;
assign a1091 = X12;
assign a1092 = X5;
assign a1093 = X13;
assign a1098 = X6;
assign a1099 = X14;
assign a1100 = X7;
assign a1101 = X15;
assign a1106 = X16;
assign a1107 = X24;
assign a1108 = X17;
assign a1109 = X25;
assign a1114 = X18;
assign a1115 = X26;
assign a1116 = X19;
assign a1117 = X27;
assign a1122 = X20;
assign a1123 = X28;
assign a1124 = X21;
assign a1125 = X29;
assign a1130 = X22;
assign a1131 = X30;
assign a1132 = X23;
assign a1133 = X31;
assign Y0 = tm346;
assign Y1 = tm349;
assign Y8 = tm352;
assign Y9 = tm355;
assign Y4 = tm358;
assign Y5 = tm361;
assign Y12 = tm364;
assign Y13 = tm367;
assign Y2 = t1894;
assign Y3 = t1895;
assign Y10 = t1896;
assign Y11 = t1897;
assign Y6 = t1898;
assign Y7 = t1899;
assign Y14 = t1900;
assign Y15 = t1901;
assign Y16 = tm370;
assign Y17 = tm373;
assign Y24 = tm376;
assign Y25 = tm379;
assign Y20 = tm382;
assign Y21 = tm385;
assign Y28 = tm388;
assign Y29 = tm391;
assign Y18 = t1946;
assign Y19 = t1947;
assign Y26 = t1948;
assign Y27 = t1949;
assign Y22 = t1950;
assign Y23 = t1951;
assign Y30 = t1952;
assign Y31 = t1953;
addfxp #(8, 1) add17626(.a(a1074), .b(a1075), .clk(clk), .q(t1850)); // 0

subfxp #(8, 1) sub17656(.a(a1074), .b(a1075), .clk(clk), .q(t1852)); // 0
addfxp #(8, 1) add17914(.a(t1850), .b(t1860), .clk(clk), .q(t1870)); // 1
subfxp #(8, 1) sub17928(.a(t1850), .b(t1860), .clk(clk), .q(t1872)); // 1
multfix #(8, 2) m17738(.a(tm1), .b(t1856), .clk(clk), .q_sc(a1066),
.q_unsc(), .rst(reset));
addfxp #(8, 1) add18114(.a(tm298), .b(t1890), .clk(clk), .q(t1894)); // 5
subfxp #(8, 1) sub18128(.a(tm298), .b(t1890), .clk(clk), .q(t1896)); // 5

end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
X4 <= X4_in;
X5 <= X5_in;
X6 <= X6_in;
X7 <= X7_in;
X8 <= X8_in;
X9 <= X9_in;
X10 <= X10_in;
X11 <= X11_in;
X12 <= X12_in;
X13 <= X13_in;
X14 <= X14_in;
X15 <= X15_in;
X16 <= X16_in;
X17 <= X17_in;
X18 <= X18_in;
X19 <= X19_in;
X20 <= X20_in;
X21 <= X21_in;
X22 <= X22_in;
X23 <= X23_in;
X24 <= X24_in;
X25 <= X25_in;
X26 <= X26_in;
X27 <= X27_in;
X28 <= X28_in;
X29 <= X29_in;
X30 <= X30_in;
X31 <= X31_in;
next <= next_in;
tm296 <= t1886;
tm299 <= t1887;
tm308 <= t1888;
tm311 <= t1889;
tm320 <= t1938;
tm323 <= t1939;
tm332 <= t1940;
tm335 <= t1941;
tm297 <= tm296;
tm300 <= tm299;
tm309 <= tm308;
tm312 <= tm311;
tm321 <= tm320;
tm324 <= tm323;
tm333 <= tm332;
tm336 <= tm335;
tm344 <= t1878;
tm347 <= t1879;
tm350 <= t1880;
tm353 <= t1881;
tm356 <= t1882;
tm359 <= t1883;
tm362 <= t1884;
tm365 <= t1885;
tm368 <= t1930;
tm371 <= t1931;
tm374 <= t1932;
tm377 <= t1933;
tm380 <= t1934;
tm383 <= t1935;
tm386 <= t1936;
tm389 <= t1937;
tm298 <= tm297;
tm301 <= tm300;
tm310 <= tm309;
tm313 <= tm312;
tm322 <= tm321;
tm325 <= tm324;
tm334 <= tm333;
tm337 <= tm336;
tm345 <= tm344;
tm348 <= tm347;
tm351 <= tm350;
tm354 <= tm353;
tm357 <= tm356;
tm360 <= tm359;
tm363 <= tm362;
tm366 <= tm365;
tm369 <= tm368;
tm372 <= tm371;
tm375 <= tm374;
tm378 <= tm377;
tm381 <= tm380;
tm384 <= tm383;
tm387 <= tm386;
tm390 <= tm389;
tm346 <= tm345;
tm349 <= tm348;
tm352 <= tm351;
tm355 <= tm354;
tm358 <= tm357;
tm361 <= tm360;
tm364 <= tm363;
tm367 <= tm366;
tm370 <= tm369;
tm373 <= tm372;
tm376 <= tm375;
tm379 <= tm378;
tm382 <= tm381;
tm385 <= tm384;
tm388 <= tm387;
tm391 <= tm390;
end
end
endmodule
// Latency: 15
// Gap: 4
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
wire [15:0] t0;

wire [15:0] s0;
wire [15:0] t1;
wire [15:0] s1;
wire [15:0] t2;
wire [15:0] s2;
wire [15:0] t3;
wire [15:0] s3;
wire [15:0] t4;
wire [15:0] s4;
wire [15:0] t5;
wire [15:0] s5;
assign t5 = {X10, X11};
wire [15:0] t6;
wire [15:0] s6;
assign t6 = {X12, X13};
wire [15:0] t7;
wire [15:0] s7;
assign t7 = {X14, X15};
wire [15:0] t8;
wire [15:0] s8;
assign t8 = {X16, X17};
wire [15:0] t9;
wire [15:0] s9;
assign t9 = {X18, X19};
wire [15:0] t10;
wire [15:0] s10;
assign t10 = {X20, X21};
wire [15:0] t11;
wire [15:0] s11;
assign t11 = {X22, X23};
wire [15:0] t12;
wire [15:0] s12;
assign t12 = {X24, X25};
wire [15:0] t13;
wire [15:0] s13;
assign t13 = {X26, X27};
wire [15:0] t14;
wire [15:0] s14;
assign t14 = {X28, X29};
wire [15:0] t15;
wire [15:0] s15;
assign t15 = {X30, X31};
assign Y0 = s0[15:8];
assign Y2 = s1[15:8];
assign Y4 = s2[15:8];
assign Y6 = s3[15:8];
assign Y8 = s4[15:8];
assign Y10 = s5[15:8];
assign Y11 = s5[7:0];
assign Y12 = s6[15:8];
assign Y13 = s6[7:0];
assign Y14 = s7[15:8];
assign Y15 = s7[7:0];
assign Y16 = s8[15:8];
assign Y17 = s8[7:0];
assign Y18 = s9[15:8];
assign Y19 = s9[7:0];
assign Y20 = s10[15:8];
assign Y21 = s10[7:0];
assign Y22 = s11[15:8];
assign Y23 = s11[7:0];
assign Y24 = s12[15:8];
assign Y25 = s12[7:0];
assign Y26 = s13[15:8];
assign Y27 = s13[7:0];
assign Y28 = s14[15:8];
assign Y29 = s14[7:0];
assign Y30 = s15[15:8];
assign Y31 = s15[7:0];

.x1(t1), .y1(s1),
.x2(t2), .y2(s2),
.x3(t3), .y3(s3),
.x4(t4), .y4(s4),
.x5(t5), .y5(s5),
.x6(t6), .y6(s6),
.x7(t7), .y7(s7),
.x8(t8), .y8(s8),
.x9(t9), .y9(s9),
.x10(t10), .y10(s10),
.x11(t11), .y11(s11),
.x12(t12), .y12(s12),
.x13(t13), .y13(s13),
.x14(t14), .y14(s14),
.x15(t15), .y15(s15),
);
endmodule

, x0, y0
, x1, y1
, x2, y2
, x3, y3
, x4, y4
, x5, y5
, x6, y6
, x7, y7
, x8, y8
, x9, y9
, x10, y10
, x11, y11
, x12, y12
, x13, y13
, x14, y14
, x15, y15
);
input [1:0] ct;

input clk;
input [0:0] itr;
t0_10, t0_11, t0_12, t0_13, t0_14, t0_15;
t1_10, t1_11, t1_12, t1_13, t1_14, t1_15;
t2_10, t2_11, t2_12, t2_13, t2_14, t2_15;
t3_10, t3_11, t3_12, t3_13, t3_14, t3_15;
t4_10, t4_11, t4_12, t4_13, t4_14, t4_15;
t5_10, t5_11, t5_12, t5_13, t5_14, t5_15;
t6_10, t6_11, t6_12, t6_13, t6_14, t6_15;
t7_10, t7_11, t7_12, t7_13, t7_14, t7_15;
t8_10, t8_11, t8_12, t8_13, t8_14, t8_15;
t9_10, t9_11, t9_12, t9_13, t9_14, t9_15;
t10_9, t10_10, t10_11, t10_12, t10_13, t10_14, t10_15;
t11_9, t11_10, t11_11, t11_12, t11_13, t11_14, t11_15;
t12_9, t12_10, t12_11, t12_12, t12_13, t12_14, t12_15;
t13_9, t13_10, t13_11, t13_12, t13_13, t13_14, t13_15;
reg [15:0] control;

case(ct)
2'd0: control <= 16'b1111111111111111;
2'd1: control <= 16'b0000000011111111;
2'd2: control <= 16'b1111111100000000;
2'd3: control <= 16'b0000000000000000;
endcase
end

end
assign t0_0 = x0;
assign t0_1 = x8;
assign t0_2 = x1;
assign t0_3 = x9;
assign t0_4 = x2;
assign t0_5 = x10;
assign t0_6 = x3;
assign t0_7 = x11;
assign t0_8 = x4;
assign t0_9 = x12;
assign t0_10 = x5;
assign t0_11 = x13;
assign t0_12 = x6;
assign t0_13 = x14;
assign t0_14 = x7;
assign t0_15 = x15;
assign t1_0 = t0_0;
assign t1_1 = t0_1;
assign t1_2 = t0_3;
assign t1_3 = t0_2;
assign t1_4 = t0_4;
assign t1_5 = t0_5;
assign t1_6 = t0_7;
assign t1_7 = t0_6;
assign t1_8 = t0_8;
assign t1_9 = t0_9;
assign t1_10 = t0_11;
assign t1_11 = t0_10;
assign t1_12 = t0_12;
assign t1_13 = t0_13;
assign t1_14 = t0_15;
assign t1_15 = t0_14;
assign t2_0 = t1_0;
assign t2_1 = t1_8;
assign t2_2 = t1_1;
assign t2_3 = t1_9;
assign t2_4 = t1_2;
assign t2_6 = t1_3;
assign t2_8 = t1_4;
assign t2_11 = t1_13;
assign t2_13 = t1_14;
assign t2_15 = t1_15;
t3_0 <= t2_0;
t3_1 <= t2_1;
t3_2 <= t2_2;
t3_3 <= t2_3;
t3_4 <= t2_4;
t3_5 <= t2_5;
t3_6 <= t2_6;
t3_7 <= t2_7;
t3_8 <= t2_8;
t3_9 <= t2_9;
t3_10 <= t2_10;
t3_11 <= t2_11;
t3_12 <= t2_12;
t3_13 <= t2_13;
t3_14 <= t2_14;
t3_15 <= t2_15;
end
assign t4_0 = t3_0;
assign t4_1 = t3_8;
assign t4_2 = t3_1;
assign t4_3 = t3_9;
assign t4_4 = t3_2;
assign t4_6 = t3_3;
assign t4_8 = t3_4;
assign t4_11 = t3_13;
assign t4_13 = t3_14;
assign t4_15 = t3_15;
assign t5_0 = t4_0;
assign t5_1 = t4_1;
assign t5_2 = t4_2;
assign t5_3 = t4_3;
assign t5_4 = t4_4;
assign t5_5 = t4_5;
assign t5_6 = t4_6;
assign t5_7 = t4_7;
assign t5_8 = t4_8;
assign t5_9 = t4_9;
assign t5_10 = t4_10;
assign t5_11 = t4_11;
assign t5_12 = t4_12;
assign t5_13 = t4_13;
assign t5_14 = t4_14;
assign t5_15 = t4_15;
assign t6_0 = t5_0;
assign t6_1 = t5_8;
assign t6_2 = t5_1;
assign t6_3 = t5_9;
assign t6_4 = t5_2;
assign t6_6 = t5_3;
assign t6_8 = t5_4;
assign t6_11 = t5_13;
assign t6_13 = t5_14;
assign t6_15 = t5_15;
t7_0 <= t6_0;
t7_1 <= t6_1;
t7_2 <= t6_2;
t7_3 <= t6_3;
t7_4 <= t6_4;
t7_5 <= t6_5;
t7_6 <= t6_6;
t7_7 <= t6_7;
t7_8 <= t6_9;
t7_9 <= t6_8;
t7_10 <= t6_11;
t7_11 <= t6_10;
t7_12 <= t6_13;
t7_13 <= t6_12;
t7_14 <= t6_15;
t7_15 <= t6_14;
end
assign t8_0 = t7_0;
assign t8_1 = t7_2;
assign t8_2 = t7_4;
assign t8_3 = t7_6;
assign t8_4 = t7_8;
assign t8_8 = t7_1;
assign t8_9 = t7_3;
assign t8_13 = t7_11;
assign t8_14 = t7_13;
assign t8_15 = t7_15;
assign t10_5 = t9_10;
assign t10_6 = t9_12;
assign t10_7 = t9_14;
assign t10_10 = t9_5;
assign t10_11 = t9_7;
assign t10_12 = t9_9;
assign t10_13 = t9_11;
assign t10_14 = t9_13;
assign t10_15 = t9_15;
t11_0 <= (control2[7] == 0) ? t10_0 : t10_1;
t11_1 <= (control2[7] == 0) ? t10_1 : t10_0;
t11_2 <= (control2[6] == 0) ? t10_2 : t10_3;
t11_3 <= (control2[6] == 0) ? t10_3 : t10_2;
t11_4 <= (control2[5] == 0) ? t10_4 : t10_5;
t11_5 <= (control2[5] == 0) ? t10_5 : t10_4;
t11_6 <= (control2[4] == 0) ? t10_6 : t10_7;
t11_7 <= (control2[4] == 0) ? t10_7 : t10_6;
t11_8 <= (control2[3] == 0) ? t10_8 : t10_9;
t11_9 <= (control2[3] == 0) ? t10_9 : t10_8;
t11_10 <= (control2[2] == 0) ? t10_10 : t10_11;
t11_11 <= (control2[2] == 0) ? t10_11 : t10_10;
t11_12 <= (control2[1] == 0) ? t10_12 : t10_13;
t11_13 <= (control2[1] == 0) ? t10_13 : t10_12;
t11_14 <= (control2[0] == 0) ? t10_14 : t10_15;
t11_15 <= (control2[0] == 0) ? t10_15 : t10_14;
end
assign t12_0 = t11_0;
assign t12_1 = t11_2;
assign t12_2 = t11_4;
assign t12_3 = t11_6;
assign t12_4 = t11_8;
assign t12_5 = t11_10;
assign t12_6 = t11_12;
assign t12_7 = t11_14;
assign t12_8 = t11_1;
assign t12_9 = t11_3;
assign t12_10 = t11_5;
assign t12_11 = t11_7;
assign t12_12 = t11_9;
assign t12_13 = t11_11;
assign t12_14 = t11_13;
assign t12_15 = t11_15;
t13_0 <= t12_0;
t13_1 <= t12_1;
t13_2 <= t12_3;
t13_3 <= t12_2;
t13_4 <= t12_4;
t13_5 <= t12_5;
t13_6 <= t12_7;
t13_7 <= t12_6;
t13_8 <= t12_8;
t13_9 <= t12_9;
t13_10 <= t12_11;
t13_11 <= t12_10;
t13_12 <= t12_12;
t13_13 <= t12_13;
t13_14 <= t12_15;
t13_15 <= t12_14;
end
y0 <= t13_0;
y1 <= t13_2;
y2 <= t13_4;
y3 <= t13_6;
y4 <= t13_8;
y5 <= t13_10;
y6 <= t13_12;
y7 <= t13_14;
y8 <= t13_1;
y9 <= t13_3;
y10 <= t13_5;
y11 <= t13_7;
y12 <= t13_9;
y13 <= t13_11;
y14 <= t13_13;
y15 <= t13_15;
end
endmodule
// Latency: 15
// Gap: 4
x0, y0,
x1, y1,
x2, y2,
x3, y3,
x4, y4,
x5, y5,
x6, y6,
x7, y7,
x8, y8,
x9, y9,
x10, y10,
x11, y11,
x12, y12,
x13, y13,
x14, y14,
x15, y15);

output next_out;

wire [0:0] tm9;

assign tm9 = 0;


shiftRegFIFO #(3, 1) shiftFIFO_27549(.X(next), .Y(next2), .clk(clk));




state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
end
endcase
end
end

state2 <= 0;
outFlip0_z <= 0;
end
s1rdloc <= 0;
state2 <= 1;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
end
1: begin
state2 <= 1;
end
endcase
end
end

state3 <= 0;
outFlip1 <= 0;
end
s2rdloc <= 0;
state3 <= 1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
end
1: begin
state3 <= 1;
end
endcase
end
end
{1'd0, 2'd0}: s1rd0 <= 3;
{1'd0, 2'd1}: s1rd0 <= 2;
{1'd0, 2'd2}: s1rd0 <= 1;
{1'd0, 2'd3}: s1rd0 <= 0;
endcase
end

{1'd0, 2'd0}: s1rd1 <= 3;
{1'd0, 2'd1}: s1rd1 <= 2;
{1'd0, 2'd2}: s1rd1 <= 1;
{1'd0, 2'd3}: s1rd1 <= 0;
endcase
end

{1'd0, 2'd0}: s1rd2 <= 2;
{1'd0, 2'd1}: s1rd2 <= 3;
{1'd0, 2'd2}: s1rd2 <= 0;
{1'd0, 2'd3}: s1rd2 <= 1;
endcase
end

{1'd0, 2'd0}: s1rd3 <= 2;
{1'd0, 2'd1}: s1rd3 <= 3;
{1'd0, 2'd2}: s1rd3 <= 0;
{1'd0, 2'd3}: s1rd3 <= 1;
endcase
end

{1'd0, 2'd0}: s1rd4 <= 1;
{1'd0, 2'd1}: s1rd4 <= 0;
{1'd0, 2'd2}: s1rd4 <= 3;
{1'd0, 2'd3}: s1rd4 <= 2;
endcase
end

{1'd0, 2'd0}: s1rd5 <= 1;
{1'd0, 2'd1}: s1rd5 <= 0;
{1'd0, 2'd2}: s1rd5 <= 3;
{1'd0, 2'd3}: s1rd5 <= 2;
endcase
end

{1'd0, 2'd0}: s1rd6 <= 0;
{1'd0, 2'd1}: s1rd6 <= 1;
{1'd0, 2'd2}: s1rd6 <= 2;
{1'd0, 2'd3}: s1rd6 <= 3;
endcase
end

{1'd0, 2'd0}: s1rd7 <= 0;
{1'd0, 2'd1}: s1rd7 <= 1;
{1'd0, 2'd2}: s1rd7 <= 2;
{1'd0, 2'd3}: s1rd7 <= 3;
endcase
end

{1'd0, 2'd0}: s1rd8 <= 3;
{1'd0, 2'd1}: s1rd8 <= 2;
{1'd0, 2'd2}: s1rd8 <= 1;
{1'd0, 2'd3}: s1rd8 <= 0;
endcase
end

{1'd0, 2'd0}: s1rd9 <= 3;
{1'd0, 2'd1}: s1rd9 <= 2;
{1'd0, 2'd2}: s1rd9 <= 1;
{1'd0, 2'd3}: s1rd9 <= 0;
endcase
end

{1'd0, 2'd0}: s1rd10 <= 2;
{1'd0, 2'd1}: s1rd10 <= 3;
{1'd0, 2'd2}: s1rd10 <= 0;
{1'd0, 2'd3}: s1rd10 <= 1;
endcase
end

{1'd0, 2'd0}: s1rd11 <= 2;
{1'd0, 2'd1}: s1rd11 <= 3;
{1'd0, 2'd2}: s1rd11 <= 0;
{1'd0, 2'd3}: s1rd11 <= 1;
endcase
end

{1'd0, 2'd0}: s1rd12 <= 1;
{1'd0, 2'd1}: s1rd12 <= 0;
{1'd0, 2'd2}: s1rd12 <= 3;
{1'd0, 2'd3}: s1rd12 <= 2;
endcase
end
{1'd0, 2'd0}: s1rd13 <= 1;
{1'd0, 2'd1}: s1rd13 <= 0;
{1'd0, 2'd2}: s1rd13 <= 3;
{1'd0, 2'd3}: s1rd13 <= 2;
endcase
end

{1'd0, 2'd0}: s1rd14 <= 0;
{1'd0, 2'd1}: s1rd14 <= 1;
{1'd0, 2'd2}: s1rd14 <= 2;
{1'd0, 2'd3}: s1rd14 <= 3;
endcase
end

{1'd0, 2'd0}: s1rd15 <= 0;
{1'd0, 2'd1}: s1rd15 <= 1;
{1'd0, 2'd2}: s1rd15 <= 2;
{1'd0, 2'd3}: s1rd15 <= 3;
endcase
end

swNet18786 sw(tm9_d, clk, muxCycle, t0, s0, t1, s1, t2, s2, t3, s3, t4, s4, t5,
s5, t6, s6, t7, s7, t8, s8, t9, s9, t10, s10, t11, s11, t12, s12, t13, s13, t14,
s14, t15, s15);

{1'd0, 2'd0}: s2wr0 <= 3;
{1'd0, 2'd1}: s2wr0 <= 2;
{1'd0, 2'd2}: s2wr0 <= 1;
{1'd0, 2'd3}: s2wr0 <= 0;

{1'd0, 2'd0}: s2wr1 <= 3;
{1'd0, 2'd1}: s2wr1 <= 2;
{1'd0, 2'd2}: s2wr1 <= 1;
{1'd0, 2'd3}: s2wr1 <= 0;

{1'd0, 2'd0}: s2wr2 <= 2;
{1'd0, 2'd1}: s2wr2 <= 3;
{1'd0, 2'd2}: s2wr2 <= 0;
{1'd0, 2'd3}: s2wr2 <= 1;

{1'd0, 2'd0}: s2wr3 <= 2;
{1'd0, 2'd1}: s2wr3 <= 3;
{1'd0, 2'd2}: s2wr3 <= 0;
{1'd0, 2'd3}: s2wr3 <= 1;

{1'd0, 2'd0}: s2wr4 <= 1;
{1'd0, 2'd1}: s2wr4 <= 0;
{1'd0, 2'd2}: s2wr4 <= 3;
{1'd0, 2'd3}: s2wr4 <= 2;

{1'd0, 2'd0}: s2wr5 <= 1;
{1'd0, 2'd1}: s2wr5 <= 0;
{1'd0, 2'd2}: s2wr5 <= 3;
{1'd0, 2'd3}: s2wr5 <= 2;

{1'd0, 2'd0}: s2wr6 <= 0;
{1'd0, 2'd1}: s2wr6 <= 1;
{1'd0, 2'd2}: s2wr6 <= 2;
{1'd0, 2'd3}: s2wr6 <= 3;

{1'd0, 2'd0}: s2wr7 <= 0;
{1'd0, 2'd1}: s2wr7 <= 1;
{1'd0, 2'd2}: s2wr7 <= 2;
{1'd0, 2'd3}: s2wr7 <= 3;

{1'd0, 2'd0}: s2wr8 <= 3;
{1'd0, 2'd1}: s2wr8 <= 2;
{1'd0, 2'd2}: s2wr8 <= 1;
{1'd0, 2'd3}: s2wr8 <= 0;

{1'd0, 2'd0}: s2wr9 <= 3;
{1'd0, 2'd1}: s2wr9 <= 2;
{1'd0, 2'd2}: s2wr9 <= 1;
{1'd0, 2'd3}: s2wr9 <= 0;

{1'd0, 2'd0}: s2wr10 <= 2;
{1'd0, 2'd1}: s2wr10 <= 3;
{1'd0, 2'd2}: s2wr10 <= 0;
{1'd0, 2'd3}: s2wr10 <= 1;

{1'd0, 2'd0}: s2wr11 <= 2;
{1'd0, 2'd1}: s2wr11 <= 3;
{1'd0, 2'd2}: s2wr11 <= 0;
{1'd0, 2'd3}: s2wr11 <= 1;

{1'd0, 2'd0}: s2wr12 <= 1;
{1'd0, 2'd1}: s2wr12 <= 0;
{1'd0, 2'd2}: s2wr12 <= 3;
{1'd0, 2'd3}: s2wr12 <= 2;

{1'd0, 2'd0}: s2wr13 <= 1;
{1'd0, 2'd1}: s2wr13 <= 0;
{1'd0, 2'd2}: s2wr13 <= 3;
{1'd0, 2'd3}: s2wr13 <= 2;

{1'd0, 2'd0}: s2wr14 <= 0;
{1'd0, 2'd1}: s2wr14 <= 1;
{1'd0, 2'd2}: s2wr14 <= 2;
{1'd0, 2'd3}: s2wr14 <= 3;

{1'd0, 2'd0}: s2wr15 <= 0;
{1'd0, 2'd1}: s2wr15 <= 1;
{1'd0, 2'd2}: s2wr15 <= 2;
{1'd0, 2'd3}: s2wr15 <= 3;

endmodule
// Latency: 8
// Gap: 4
module DirSum_20265(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
reg [1:0] i2;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;

i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 3)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock18791 codeBlockIsnt27564(.clk(clk), .reset(reset), .next_in(next),

.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3),
.X4_in(X4), .Y4(Y4),
.X5_in(X5), .Y5(Y5),
.X6_in(X6), .Y6(Y6),
.X7_in(X7), .Y7(Y7),
.X8_in(X8), .Y8(Y8),
.X9_in(X9), .Y9(Y9),
.X10_in(X10), .Y10(Y10),
.X11_in(X11), .Y11(Y11),
.X12_in(X12), .Y12(Y12),
.X13_in(X13), .Y13(Y13),
.X14_in(X14), .Y14(Y14),
.X15_in(X15), .Y15(Y15),
.X16_in(X16), .Y16(Y16),
.X17_in(X17), .Y17(Y17),
.X18_in(X18), .Y18(Y18),
.X19_in(X19), .Y19(Y19),
.X20_in(X20), .Y20(Y20),
.X21_in(X21), .Y21(Y21),
.X22_in(X22), .Y22(Y22),
.X23_in(X23), .Y23(Y23),
.X24_in(X24), .Y24(Y24),
.X25_in(X25), .Y25(Y25),
.X26_in(X26), .Y26(Y26),
.X27_in(X27), .Y27(Y27),
.X28_in(X28), .Y28(Y28),
.X29_in(X29), .Y29(Y29),
.X30_in(X30), .Y30(Y30),
.X31_in(X31), .Y31(Y31));
endmodule
module D70_20077(addr, out, clk);

input clk;
output [7:0] out;
reg [7:0] out, out2, out3;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hd7;
1: out3 <= 8'hc8;
2: out3 <= 8'h13;
3: out3 <= 8'h40;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hdc;
1: out3 <= 8'hc1;
2: out3 <= 8'hf4;
3: out3 <= 8'h35;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'he2;
1: out3 <= 8'hc0;
2: out3 <= 8'hd7;
3: out3 <= 8'h13;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'he8;
1: out3 <= 8'hc5;
2: out3 <= 8'hc5;
3: out3 <= 8'he8;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hed;
1: out3 <= 8'hcf;
2: out3 <= 8'hc0;
3: out3 <= 8'hc8;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hf4;
1: out3 <= 8'hdc;
2: out3 <= 8'hcb;
3: out3 <= 8'hc1;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfa;
1: out3 <= 8'hed;
2: out3 <= 8'he2;
3: out3 <= 8'hd7;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hc1;
2: out3 <= 8'he8;
3: out3 <= 8'h35;
default: out3 <= 0;
endcase
end
endmodule
input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hc5;
2: out3 <= 8'hd3;
3: out3 <= 8'h18;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hcb;
2: out3 <= 8'hc5;
3: out3 <= 8'hf4;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hd3;
2: out3 <= 8'hc0;
3: out3 <= 8'hd3;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hdc;
2: out3 <= 8'hc5;
3: out3 <= 8'hc1;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'he8;
2: out3 <= 8'hd3;
3: out3 <= 8'hc5;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hf4;
2: out3 <= 8'he8;
3: out3 <= 8'hdc;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h31;
1: out3 <= 8'he2;
2: out3 <= 8'hc3;
3: out3 <= 8'h6;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h35;
1: out3 <= 8'hf4;
2: out3 <= 8'hc1;
3: out3 <= 8'hdc;
default: out3 <= 0;
endcase
end
endmodule
input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h38;
1: out3 <= 8'h6;
2: out3 <= 8'hcf;
3: out3 <= 8'hc3;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3b;
1: out3 <= 8'h18;
2: out3 <= 8'he8;
3: out3 <= 8'hc5;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3d;
1: out3 <= 8'h29;
2: out3 <= 8'h6;
3: out3 <= 8'he2;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3f;
1: out3 <= 8'h35;
2: out3 <= 8'h24;
3: out3 <= 8'hc;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3d;
2: out3 <= 8'h38;
3: out3 <= 8'h31;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'hc;
2: out3 <= 8'hc5;
3: out3 <= 8'hdc;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h18;
2: out3 <= 8'hd3;
3: out3 <= 8'hc5;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h24;
2: out3 <= 8'he8;
3: out3 <= 8'hc1;
default: out3 <= 0;
endcase
end
endmodule
input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h2d;
2: out3 <= 8'h0;
3: out3 <= 8'hd3;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h35;
2: out3 <= 8'h18;
3: out3 <= 8'hf4;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3b;
2: out3 <= 8'h2d;
3: out3 <= 8'h18;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [1:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3f;
2: out3 <= 8'h3b;
3: out3 <= 8'h35;
default: out3 <= 0;
endcase
end
endmodule
// Latency: 8
// Gap: 1
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3,
X4_in, Y4,
X5_in, Y5,
X6_in, Y6,
X7_in, Y7,
X8_in, Y8,
X9_in, Y9,
X10_in, Y10,
X11_in, Y11,
X12_in, Y12,
X13_in, Y13,
X14_in, Y14,
X15_in, Y15,
X16_in, Y16,
X17_in, Y17,
X18_in, Y18,
X19_in, Y19,
X20_in, Y20,
X21_in, Y21,
X22_in, Y22,
X23_in, Y23,
X24_in, Y24,
X25_in, Y25,
X26_in, Y26,
X27_in, Y27,
X28_in, Y28,
X29_in, Y29,
X30_in, Y30,
X31_in, Y31);
output next_out;
reg next;
input [1:0] i2_in;
reg [1:0] i2;
input [7:0] X0_in,

X1_in,
X2_in,
X3_in,
X4_in,
X5_in,
X6_in,
X7_in,
X8_in,
X9_in,
X10_in,
X11_in,
X12_in,
X13_in,
X14_in,
X15_in,
X16_in,
X17_in,
X18_in,
X19_in,
X20_in,
X21_in,
X22_in,
X23_in,
X24_in,
X25_in,
X26_in,
X27_in,
X28_in,
X29_in,
X30_in,
X31_in;
reg [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;

assign a922 = X0;

assign a827 = a922;
assign a925 = X1;
assign a831 = a925;
assign a926 = X2;
assign a927 = X3;
assign a930 = X4;
assign a931 = X5;
assign a934 = X6;
assign a935 = X7;
assign a938 = X8;
assign a939 = X9;
assign a942 = X10;
assign a943 = X11;
assign a946 = X12;
assign a947 = X13;
assign a950 = X14;
assign a951 = X15;
assign a954 = X16;
assign a875 = a954;
assign a957 = X17;
assign a879 = a957;
assign a958 = X18;
assign a959 = X19;
assign a962 = X20;
assign a963 = X21;
assign a966 = X22;
assign a967 = X23;
assign a970 = X24;
assign a971 = X25;
assign a974 = X26;
assign a975 = X27;
assign a978 = X28;
assign a979 = X29;
assign a982 = X30;
assign a983 = X31;
assign a832 = tm12;
assign a834 = tm13;
assign a838 = tm14;
assign a840 = tm15;
assign a844 = tm16;
assign a846 = tm17;
assign a850 = tm18;
assign a852 = tm19;
assign a856 = tm20;
assign a858 = tm21;
assign a862 = tm22;
assign a864 = tm23;
assign a868 = tm24;
assign a870 = tm25;
assign a880 = tm28;
assign a882 = tm29;
assign a886 = tm30;
assign a888 = tm31;
assign a892 = tm32;
assign a894 = tm33;
assign a898 = tm34;
assign a900 = tm35;
assign a904 = tm36;
assign a906 = tm37;
assign a910 = tm38;
assign a912 = tm39;
assign a916 = tm40;
assign a918 = tm41;
assign Y0 = tm622;
assign Y1 = tm629;
assign Y16 = tm636;
assign Y17 = tm643;
D70_20077 instD70inst0_20077(.addr(i2[1:0]), .out(tm41), .clk(clk));

multfix #(8, 2) m18890(.a(tm88), .b(tm395), .clk(clk), .q_sc(a833),
multfix #(8, 2) m19130(.a(tm100), .b(tm443), .clk(clk), .q_sc(a851), .q_unsc(),
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
subfxp #(8, 1) sub18919(.a(a833), .b(a835), .clk(clk), .q(Y2)); // 6
addfxp #(8, 1) add18948(.a(a836), .b(a837), .clk(clk), .q(Y3)); // 6

tm88 <= 0;
tm395 <= 0;
tm89 <= 0;
tm399 <= 0;
tm89 <= 0;
tm395 <= 0;
tm88 <= 0;
tm399 <= 0;
tm92 <= 0;
tm411 <= 0;
tm93 <= 0;
tm415 <= 0;
tm93 <= 0;
tm411 <= 0;
tm92 <= 0;
tm415 <= 0;
tm96 <= 0;
tm427 <= 0;
tm97 <= 0;
tm431 <= 0;
tm97 <= 0;
tm427 <= 0;
tm96 <= 0;
tm431 <= 0;
tm100 <= 0;
tm443 <= 0;
tm101 <= 0;
tm447 <= 0;
tm101 <= 0;
tm443 <= 0;
tm100 <= 0;
tm447 <= 0;
tm104 <= 0;
tm459 <= 0;
tm105 <= 0;
tm463 <= 0;
tm105 <= 0;
tm459 <= 0;
tm104 <= 0;
tm463 <= 0;
tm108 <= 0;
tm475 <= 0;
tm109 <= 0;
tm479 <= 0;
tm109 <= 0;
tm475 <= 0;
tm108 <= 0;
tm479 <= 0;
tm112 <= 0;
tm491 <= 0;
tm113 <= 0;
tm495 <= 0;
tm113 <= 0;
tm491 <= 0;
tm112 <= 0;
tm495 <= 0;
tm120 <= 0;
tm507 <= 0;
tm121 <= 0;
tm511 <= 0;
tm121 <= 0;
tm507 <= 0;
tm120 <= 0;
tm511 <= 0;
tm124 <= 0;
tm523 <= 0;
tm125 <= 0;
tm527 <= 0;
tm125 <= 0;
tm523 <= 0;
tm124 <= 0;
tm527 <= 0;
tm128 <= 0;
tm539 <= 0;
tm129 <= 0;
tm543 <= 0;
tm129 <= 0;
tm539 <= 0;
tm128 <= 0;
tm543 <= 0;
tm132 <= 0;
tm555 <= 0;
tm133 <= 0;
tm559 <= 0;
tm133 <= 0;
tm555 <= 0;
tm132 <= 0;
tm559 <= 0;
tm136 <= 0;
tm571 <= 0;
tm137 <= 0;
tm575 <= 0;
tm137 <= 0;
tm571 <= 0;
tm136 <= 0;
tm575 <= 0;
tm140 <= 0;
tm587 <= 0;
tm141 <= 0;
tm591 <= 0;
tm141 <= 0;
tm587 <= 0;
tm140 <= 0;
tm591 <= 0;
tm144 <= 0;
tm603 <= 0;
tm145 <= 0;
tm607 <= 0;
tm145 <= 0;
tm603 <= 0;
tm144 <= 0;
tm607 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
X4 <= X4_in;
X5 <= X5_in;
X6 <= X6_in;
X7 <= X7_in;
X8 <= X8_in;
X9 <= X9_in;
X10 <= X10_in;
X11 <= X11_in;
X12 <= X12_in;
X13 <= X13_in;
X14 <= X14_in;
X15 <= X15_in;
X16 <= X16_in;
X17 <= X17_in;
X18 <= X18_in;
X19 <= X19_in;
X20 <= X20_in;
X21 <= X21_in;
X22 <= X22_in;
X23 <= X23_in;
X24 <= X24_in;
X25 <= X25_in;
X26 <= X26_in;
X27 <= X27_in;
X28 <= X28_in;
X29 <= X29_in;
X30 <= X30_in;
X31 <= X31_in;
next <= next_in;
tm392 <= a926;
tm396 <= a927;
tm408 <= a930;
tm412 <= a931;
tm424 <= a934;
tm428 <= a935;
tm440 <= a938;
tm444 <= a939;
tm456 <= a942;
tm460 <= a943;
tm472 <= a946;
tm476 <= a947;
tm488 <= a950;
tm492 <= a951;
tm504 <= a958;
tm508 <= a959;
tm520 <= a962;
tm524 <= a963;
tm536 <= a966;
tm540 <= a967;
tm552 <= a970;
tm556 <= a971;
tm568 <= a974;
tm572 <= a975;
tm584 <= a978;
tm588 <= a979;
tm600 <= a982;
tm604 <= a983;
tm616 <= a827;
tm623 <= a831;
tm630 <= a875;
tm637 <= a879;
tm393 <= tm392;
tm397 <= tm396;
tm409 <= tm408;
tm413 <= tm412;
tm425 <= tm424;
tm429 <= tm428;
tm441 <= tm440;
tm445 <= tm444;
tm457 <= tm456;
tm461 <= tm460;
tm473 <= tm472;
tm477 <= tm476;
tm489 <= tm488;
tm493 <= tm492;
tm505 <= tm504;
tm509 <= tm508;
tm521 <= tm520;
tm525 <= tm524;
tm537 <= tm536;
tm541 <= tm540;
tm553 <= tm552;
tm557 <= tm556;
tm569 <= tm568;
tm573 <= tm572;
tm585 <= tm584;
tm589 <= tm588;
tm601 <= tm600;
tm605 <= tm604;
tm617 <= tm616;
tm624 <= tm623;
tm631 <= tm630;
tm638 <= tm637;
tm394 <= tm393;
tm398 <= tm397;
tm410 <= tm409;
tm414 <= tm413;
tm426 <= tm425;
tm430 <= tm429;
tm442 <= tm441;
tm446 <= tm445;
tm458 <= tm457;
tm462 <= tm461;
tm474 <= tm473;
tm478 <= tm477;
tm490 <= tm489;
tm494 <= tm493;
tm506 <= tm505;
tm510 <= tm509;
tm522 <= tm521;
tm526 <= tm525;
tm538 <= tm537;
tm542 <= tm541;
tm554 <= tm553;
tm558 <= tm557;
tm570 <= tm569;
tm574 <= tm573;
tm586 <= tm585;
tm590 <= tm589;
tm602 <= tm601;
tm606 <= tm605;
tm618 <= tm617;
tm625 <= tm624;
tm632 <= tm631;
tm639 <= tm638;
tm88 <= a832;
tm89 <= a834;
tm92 <= a838;
tm93 <= a840;
tm96 <= a844;
tm97 <= a846;
tm100 <= a850;
tm101 <= a852;
tm104 <= a856;
tm105 <= a858;
tm108 <= a862;
tm109 <= a864;
tm112 <= a868;
tm113 <= a870;
tm120 <= a880;
tm121 <= a882;
tm124 <= a886;
tm125 <= a888;
tm128 <= a892;
tm129 <= a894;
tm132 <= a898;
tm133 <= a900;
tm136 <= a904;
tm137 <= a906;
tm140 <= a910;
tm141 <= a912;
tm144 <= a916;
tm145 <= a918;
tm395 <= tm394;
tm399 <= tm398;
tm411 <= tm410;
tm415 <= tm414;
tm427 <= tm426;
tm431 <= tm430;
tm443 <= tm442;
tm447 <= tm446;
tm459 <= tm458;
tm463 <= tm462;
tm475 <= tm474;
tm479 <= tm478;
tm491 <= tm490;
tm495 <= tm494;
tm507 <= tm506;
tm511 <= tm510;
tm523 <= tm522;
tm527 <= tm526;
tm539 <= tm538;
tm543 <= tm542;
tm555 <= tm554;
tm559 <= tm558;
tm571 <= tm570;
tm575 <= tm574;
tm587 <= tm586;
tm591 <= tm590;
tm603 <= tm602;
tm607 <= tm606;
tm619 <= tm618;
tm626 <= tm625;
tm633 <= tm632;
tm640 <= tm639;
tm620 <= tm619;
tm627 <= tm626;
tm634 <= tm633;
tm641 <= tm640;
tm621 <= tm620;
tm628 <= tm627;
tm635 <= tm634;
tm642 <= tm641;
tm622 <= tm621;
tm629 <= tm628;
tm636 <= tm635;
tm643 <= tm642;
end
end
endmodule
// Latency: 7
// Gap: 1
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3,
X4_in, Y4,
X5_in, Y5,
X6_in, Y6,
X7_in, Y7,
X8_in, Y8,
X9_in, Y9,
X10_in, Y10,
X11_in, Y11,
X12_in, Y12,
X13_in, Y13,
X14_in, Y14,
X15_in, Y15,
X16_in, Y16,
X17_in, Y17,
X18_in, Y18,
X19_in, Y19,
X20_in, Y20,
X21_in, Y21,
X22_in, Y22,
X23_in, Y23,
X24_in, Y24,
X25_in, Y25,
X26_in, Y26,
X27_in, Y27,
X28_in, Y28,
X29_in, Y29,
X30_in, Y30,
X31_in, Y31);
output next_out;
reg next;
input [7:0] X0_in,

X1_in,
X2_in,
X3_in,
X4_in,
X5_in,
X6_in,
X7_in,
X8_in,
X9_in,
X10_in,
X11_in,
X12_in,
X13_in,
X14_in,
X15_in,
X16_in,
X17_in,
X18_in,
X19_in,
X20_in,
X21_in,
X22_in,
X23_in,
X24_in,
X25_in,
X26_in,
X27_in,
X28_in,
X29_in,
X30_in,
X31_in;
reg [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;


assign tm42 = 8'h2d;
assign a570 = X0;

assign a571 = X8;
assign a572 = X1;
assign a573 = X9;
assign a578 = X2;
assign a579 = X10;
assign a580 = X3;
assign a581 = X11;
assign a586 = X4;
assign a587 = X12;
assign a588 = X5;
assign a589 = X13;
assign a594 = X6;
assign a595 = X14;
assign a596 = X7;
assign a597 = X15;
assign a602 = X16;
assign a603 = X24;
assign a604 = X17;
assign a605 = X25;
assign a610 = X18;
assign a611 = X26;
assign a612 = X19;
assign a613 = X27;
assign a618 = X20;
assign a619 = X28;
assign a620 = X21;
assign a621 = X29;
assign a626 = X22;
assign a627 = X30;
assign a628 = X23;
assign a629 = X31;
assign Y0 = tm694;
assign Y1 = tm697;
assign Y8 = tm700;
assign Y9 = tm703;
assign Y4 = tm706;
assign Y5 = tm709;
assign Y12 = tm712;
assign Y13 = tm715;
assign Y2 = t1150;
assign Y3 = t1151;
assign Y10 = t1152;
assign Y11 = t1153;
assign Y6 = t1154;
assign Y7 = t1155;
assign Y14 = t1156;
assign Y15 = t1157;
assign Y16 = tm718;
assign Y17 = tm721;
assign Y24 = tm724;
assign Y25 = tm727;
assign Y20 = tm730;
assign Y21 = tm733;
assign Y28 = tm736;
assign Y29 = tm739;
assign Y18 = t1202;
assign Y19 = t1203;
assign Y26 = t1204;
assign Y27 = t1205;
assign Y22 = t1206;
assign Y23 = t1207;
assign Y30 = t1208;
assign Y31 = t1209;


end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
X4 <= X4_in;
X5 <= X5_in;
X6 <= X6_in;
X7 <= X7_in;
X8 <= X8_in;
X9 <= X9_in;
X10 <= X10_in;
X11 <= X11_in;
X12 <= X12_in;
X13 <= X13_in;
X14 <= X14_in;
X15 <= X15_in;
X16 <= X16_in;
X17 <= X17_in;
X18 <= X18_in;
X19 <= X19_in;
X20 <= X20_in;
X21 <= X21_in;
X22 <= X22_in;
X23 <= X23_in;
X24 <= X24_in;
X25 <= X25_in;
X26 <= X26_in;
X27 <= X27_in;
X28 <= X28_in;
X29 <= X29_in;
X30 <= X30_in;
X31 <= X31_in;
next <= next_in;
tm644 <= t1142;
tm647 <= t1143;
tm656 <= t1144;
tm659 <= t1145;
tm668 <= t1194;
tm671 <= t1195;
tm680 <= t1196;
tm683 <= t1197;
tm645 <= tm644;
tm648 <= tm647;
tm657 <= tm656;
tm660 <= tm659;
tm669 <= tm668;
tm672 <= tm671;
tm681 <= tm680;
tm684 <= tm683;
tm692 <= t1134;
tm695 <= t1135;
tm698 <= t1136;
tm701 <= t1137;
tm704 <= t1138;
tm707 <= t1139;
tm710 <= t1140;
tm713 <= t1141;
tm716 <= t1186;
tm719 <= t1187;
tm722 <= t1188;
tm725 <= t1189;
tm728 <= t1190;
tm731 <= t1191;
tm734 <= t1192;
tm737 <= t1193;
tm646 <= tm645;
tm649 <= tm648;
tm658 <= tm657;
tm661 <= tm660;
tm670 <= tm669;
tm673 <= tm672;
tm682 <= tm681;
tm685 <= tm684;
tm693 <= tm692;
tm696 <= tm695;
tm699 <= tm698;
tm702 <= tm701;
tm705 <= tm704;
tm708 <= tm707;
tm711 <= tm710;
tm714 <= tm713;
tm717 <= tm716;
tm720 <= tm719;
tm723 <= tm722;
tm726 <= tm725;
tm729 <= tm728;
tm732 <= tm731;
tm735 <= tm734;
tm738 <= tm737;
tm694 <= tm693;
tm697 <= tm696;
tm700 <= tm699;
tm703 <= tm702;
tm706 <= tm705;
tm709 <= tm708;
tm712 <= tm711;
tm715 <= tm714;
tm718 <= tm717;
tm721 <= tm720;
tm724 <= tm723;
tm727 <= tm726;
tm730 <= tm729;
tm733 <= tm732;
tm736 <= tm735;
tm739 <= tm738;
end
end
endmodule
// Latency: 39
// Gap: 16
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
wire [15:0] t0;

wire [15:0] s0;
wire [15:0] t1;
wire [15:0] s1;
wire [15:0] t2;
wire [15:0] s2;
wire [15:0] t3;
wire [15:0] s3;
wire [15:0] t4;
wire [15:0] s4;
wire [15:0] t5;
wire [15:0] s5;
assign t5 = {X10, X11};
wire [15:0] t6;
wire [15:0] s6;
assign t6 = {X12, X13};
wire [15:0] t7;
wire [15:0] s7;
assign t7 = {X14, X15};
wire [15:0] t8;
wire [15:0] s8;
assign t8 = {X16, X17};
wire [15:0] t9;
wire [15:0] s9;
assign t9 = {X18, X19};
wire [15:0] t10;
wire [15:0] s10;
assign t10 = {X20, X21};
wire [15:0] t11;
wire [15:0] s11;
assign t11 = {X22, X23};
wire [15:0] t12;
wire [15:0] s12;
assign t12 = {X24, X25};
wire [15:0] t13;
wire [15:0] s13;
assign t13 = {X26, X27};
wire [15:0] t14;
wire [15:0] s14;
assign t14 = {X28, X29};
wire [15:0] t15;
wire [15:0] s15;
assign t15 = {X30, X31};
assign Y0 = s0[15:8];
assign Y2 = s1[15:8];
assign Y4 = s2[15:8];
assign Y6 = s3[15:8];
assign Y8 = s4[15:8];
assign Y10 = s5[15:8];
assign Y11 = s5[7:0];
assign Y12 = s6[15:8];
assign Y13 = s6[7:0];
assign Y14 = s7[15:8];
assign Y15 = s7[7:0];
assign Y16 = s8[15:8];
assign Y17 = s8[7:0];
assign Y18 = s9[15:8];
assign Y19 = s9[7:0];
assign Y20 = s10[15:8];
assign Y21 = s10[7:0];
assign Y22 = s11[15:8];
assign Y23 = s11[7:0];
assign Y24 = s12[15:8];
assign Y25 = s12[7:0];
assign Y26 = s13[15:8];
assign Y27 = s13[7:0];
assign Y28 = s14[15:8];
assign Y29 = s14[7:0];
assign Y30 = s15[15:8];
assign Y31 = s15[7:0];

.x1(t1), .y1(s1),
.x2(t2), .y2(s2),
.x3(t3), .y3(s3),
.x4(t4), .y4(s4),
.x5(t5), .y5(s5),
.x6(t6), .y6(s6),
.x7(t7), .y7(s7),
.x8(t8), .y8(s8),
.x9(t9), .y9(s9),
.x10(t10), .y10(s10),
.x11(t11), .y11(s11),
.x12(t12), .y12(s12),
.x13(t13), .y13(s13),
.x14(t14), .y14(s14),
.x15(t15), .y15(s15),
);
endmodule

, x0, y0
, x1, y1
, x2, y2
, x3, y3
, x4, y4
, x5, y5
, x6, y6
, x7, y7
, x8, y8
, x9, y9
, x10, y10
, x11, y11
, x12, y12
, x13, y13
, x14, y14
, x15, y15
);
input [3:0] ct;

input clk;
input [0:0] itr;
t0_10, t0_11, t0_12, t0_13, t0_14, t0_15;
t1_10, t1_11, t1_12, t1_13, t1_14, t1_15;
t2_10, t2_11, t2_12, t2_13, t2_14, t2_15;
t3_10, t3_11, t3_12, t3_13, t3_14, t3_15;
t4_10, t4_11, t4_12, t4_13, t4_14, t4_15;
t5_10, t5_11, t5_12, t5_13, t5_14, t5_15;
t6_10, t6_11, t6_12, t6_13, t6_14, t6_15;
t7_10, t7_11, t7_12, t7_13, t7_14, t7_15;
t8_10, t8_11, t8_12, t8_13, t8_14, t8_15;
t9_10, t9_11, t9_12, t9_13, t9_14, t9_15;
t10_9, t10_10, t10_11, t10_12, t10_13, t10_14, t10_15;
t11_9, t11_10, t11_11, t11_12, t11_13, t11_14, t11_15;
t12_9, t12_10, t12_11, t12_12, t12_13, t12_14, t12_15;
t13_9, t13_10, t13_11, t13_12, t13_13, t13_14, t13_15;
reg [23:0] control;

case(ct)
4'd0: control <= 24'b111111111111111111110000;
4'd1: control <= 24'b111111111111111111110000;
4'd2: control <= 24'b000000001111111111110000;
4'd3: control <= 24'b000000001111111111110000;
4'd4: control <= 24'b111111110000000011110000;
4'd5: control <= 24'b111111110000000011110000;
4'd6: control <= 24'b000000000000000011110000;
4'd7: control <= 24'b000000000000000011110000;
4'd8: control <= 24'b111111111111111100001111;
4'd9: control <= 24'b111111111111111100001111;
4'd10: control <= 24'b000000001111111100001111;
4'd11: control <= 24'b000000001111111100001111;
4'd12: control <= 24'b111111110000000000001111;
4'd13: control <= 24'b111111110000000000001111;
4'd14: control <= 24'b000000000000000000001111;
4'd15: control <= 24'b000000000000000000001111;
endcase
end

end
assign t0_0 = x0;
assign t0_1 = x8;
assign t0_2 = x1;
assign t0_3 = x9;
assign t0_4 = x2;
assign t0_5 = x10;
assign t0_6 = x3;
assign t0_7 = x11;
assign t0_8 = x4;
assign t0_9 = x12;
assign t0_10 = x5;
assign t0_11 = x13;
assign t0_12 = x6;
assign t0_13 = x14;
assign t0_14 = x7;
assign t0_15 = x15;
assign t1_0 = t0_0;
assign t1_1 = t0_1;
assign t1_2 = t0_2;
assign t1_3 = t0_3;
assign t1_4 = t0_4;
assign t1_5 = t0_5;
assign t1_6 = t0_6;
assign t1_7 = t0_7;
assign t1_8 = t0_9;
assign t1_9 = t0_8;
assign t1_10 = t0_11;
assign t1_11 = t0_10;
assign t1_12 = t0_13;
assign t1_13 = t0_12;
assign t1_14 = t0_15;
assign t1_15 = t0_14;
assign t2_0 = t1_0;
assign t2_1 = t1_8;
assign t2_2 = t1_1;
assign t2_3 = t1_9;
assign t2_4 = t1_2;
assign t2_6 = t1_3;
assign t2_8 = t1_4;
assign t2_11 = t1_13;
assign t2_13 = t1_14;
assign t2_15 = t1_15;
t3_0 <= t2_0;
t3_1 <= t2_1;
t3_2 <= t2_2;
t3_3 <= t2_3;
t3_4 <= t2_4;
t3_5 <= t2_5;
t3_6 <= t2_6;
t3_7 <= t2_7;
t3_8 <= t2_8;
t3_9 <= t2_9;
t3_10 <= t2_10;
t3_11 <= t2_11;
t3_12 <= t2_12;
t3_13 <= t2_13;
t3_14 <= t2_14;
t3_15 <= t2_15;
end
assign t4_0 = t3_0;
assign t4_1 = t3_8;
assign t4_2 = t3_1;
assign t4_3 = t3_9;
assign t4_4 = t3_2;
assign t4_6 = t3_3;
assign t4_8 = t3_4;
assign t4_11 = t3_13;
assign t4_13 = t3_14;
assign t4_15 = t3_15;
assign t5_0 = t4_0;
assign t5_1 = t4_1;
assign t5_2 = t4_2;
assign t5_3 = t4_3;
assign t5_4 = t4_4;
assign t5_5 = t4_5;
assign t5_6 = t4_6;
assign t5_7 = t4_7;
assign t5_8 = t4_8;
assign t5_9 = t4_9;
assign t5_10 = t4_10;
assign t5_11 = t4_11;
assign t5_12 = t4_12;
assign t5_13 = t4_13;
assign t5_14 = t4_14;
assign t5_15 = t4_15;
assign t6_0 = t5_0;
assign t6_1 = t5_8;
assign t6_2 = t5_1;
assign t6_3 = t5_9;
assign t6_4 = t5_2;
assign t6_6 = t5_3;
assign t6_8 = t5_4;
assign t6_11 = t5_13;
assign t6_13 = t5_14;
assign t6_15 = t5_15;
t7_0 <= (control1[23] == 0) ? t6_0 : t6_1;
t7_1 <= (control1[23] == 0) ? t6_1 : t6_0;
t7_2 <= (control1[22] == 0) ? t6_2 : t6_3;
t7_3 <= (control1[22] == 0) ? t6_3 : t6_2;
t7_4 <= (control1[21] == 0) ? t6_4 : t6_5;
t7_5 <= (control1[21] == 0) ? t6_5 : t6_4;
t7_6 <= (control1[20] == 0) ? t6_6 : t6_7;
t7_7 <= (control1[20] == 0) ? t6_7 : t6_6;
t7_8 <= (control1[19] == 0) ? t6_8 : t6_9;
t7_9 <= (control1[19] == 0) ? t6_9 : t6_8;
t7_10 <= (control1[18] == 0) ? t6_10 : t6_11;
t7_11 <= (control1[18] == 0) ? t6_11 : t6_10;
t7_12 <= (control1[17] == 0) ? t6_12 : t6_13;
t7_13 <= (control1[17] == 0) ? t6_13 : t6_12;
t7_14 <= (control1[16] == 0) ? t6_14 : t6_15;
t7_15 <= (control1[16] == 0) ? t6_15 : t6_14;
end
assign t8_0 = t7_0;
assign t8_1 = t7_2;
assign t8_2 = t7_4;
assign t8_3 = t7_6;
assign t8_4 = t7_8;
assign t8_8 = t7_1;
assign t8_9 = t7_3;
assign t8_13 = t7_11;
assign t8_14 = t7_13;
assign t8_15 = t7_15;
assign t10_5 = t9_10;
assign t10_6 = t9_12;
assign t10_7 = t9_14;
assign t10_10 = t9_5;
assign t10_11 = t9_7;
assign t10_12 = t9_9;
assign t10_13 = t9_11;
assign t10_14 = t9_13;
assign t10_15 = t9_15;
t11_0 <= t10_0;
t11_1 <= t10_1;
t11_2 <= t10_3;
t11_3 <= t10_2;
t11_4 <= t10_4;
t11_5 <= t10_5;
t11_6 <= t10_7;
t11_7 <= t10_6;
t11_8 <= t10_8;
t11_9 <= t10_9;
t11_10 <= t10_11;
t11_11 <= t10_10;
t11_12 <= t10_12;
t11_13 <= t10_13;
t11_14 <= t10_15;
t11_15 <= t10_14;
end
assign t12_0 = t11_0;
assign t12_1 = t11_2;
assign t12_2 = t11_4;
assign t12_3 = t11_6;
assign t12_4 = t11_8;
assign t12_5 = t11_10;
assign t12_6 = t11_12;
assign t12_7 = t11_14;
assign t12_8 = t11_1;
assign t12_9 = t11_3;
assign t12_10 = t11_5;
assign t12_11 = t11_7;
assign t12_12 = t11_9;
assign t12_13 = t11_11;
assign t12_14 = t11_13;
assign t12_15 = t11_15;
t13_0 <= (control3[7] == 0) ? t12_0 : t12_1;
t13_1 <= (control3[7] == 0) ? t12_1 : t12_0;
t13_2 <= (control3[6] == 0) ? t12_2 : t12_3;
t13_3 <= (control3[6] == 0) ? t12_3 : t12_2;
t13_4 <= (control3[5] == 0) ? t12_4 : t12_5;
t13_5 <= (control3[5] == 0) ? t12_5 : t12_4;
t13_6 <= (control3[4] == 0) ? t12_6 : t12_7;
t13_7 <= (control3[4] == 0) ? t12_7 : t12_6;
t13_8 <= (control3[3] == 0) ? t12_8 : t12_9;
t13_9 <= (control3[3] == 0) ? t12_9 : t12_8;
t13_10 <= (control3[2] == 0) ? t12_10 : t12_11;
t13_11 <= (control3[2] == 0) ? t12_11 : t12_10;
t13_12 <= (control3[1] == 0) ? t12_12 : t12_13;
t13_13 <= (control3[1] == 0) ? t12_13 : t12_12;
t13_14 <= (control3[0] == 0) ? t12_14 : t12_15;
t13_15 <= (control3[0] == 0) ? t12_15 : t12_14;
end
y0 <= t13_0;
y1 <= t13_2;
y2 <= t13_4;
y3 <= t13_6;
y4 <= t13_8;
y5 <= t13_10;
y6 <= t13_12;
y7 <= t13_14;
y8 <= t13_1;
y9 <= t13_3;
y10 <= t13_5;
y11 <= t13_7;
y12 <= t13_9;
y13 <= t13_11;
y14 <= t13_13;
y15 <= t13_15;
end
endmodule
// Latency: 39
// Gap: 16
x0, y0,
x1, y1,
x2, y2,
x3, y3,
x4, y4,
x5, y5,
x6, y6,
x7, y7,
x8, y8,
x9, y9,
x10, y10,
x11, y11,
x12, y12,
x13, y13,
x14, y14,
x15, y15);

output next_out;

wire [0:0] tm50;

assign tm50 = 0;






state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
end
endcase
end
end

state2 <= 0;
outFlip0_z <= 0;
end
s1rdloc <= 0;
state2 <= 1;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
end
1: begin
state2 <= 1;
end
endcase
end
end

state3 <= 0;
outFlip1 <= 0;
end
s2rdloc <= 0;
state3 <= 1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
end
1: begin
state3 <= 1;
end
endcase
end
end
{1'd0, 4'd0}: s1rd0 <= 13;
{1'd0, 4'd1}: s1rd0 <= 15;
{1'd0, 4'd2}: s1rd0 <= 9;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 5;
{1'd0, 4'd5}: s1rd0 <= 7;
{1'd0, 4'd6}: s1rd0 <= 1;
{1'd0, 4'd7}: s1rd0 <= 3;
{1'd0, 4'd8}: s1rd0 <= 12;
{1'd0, 4'd9}: s1rd0 <= 14;
{1'd0, 4'd10}: s1rd0 <= 8;
{1'd0, 4'd11}: s1rd0 <= 10;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 6;
{1'd0, 4'd14}: s1rd0 <= 0;
{1'd0, 4'd15}: s1rd0 <= 2;
endcase
end

{1'd0, 4'd0}: s1rd1 <= 9;
{1'd0, 4'd1}: s1rd1 <= 11;
{1'd0, 4'd2}: s1rd1 <= 13;
{1'd0, 4'd3}: s1rd1 <= 15;
{1'd0, 4'd4}: s1rd1 <= 1;
{1'd0, 4'd5}: s1rd1 <= 3;
{1'd0, 4'd6}: s1rd1 <= 5;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 10;
{1'd0, 4'd10}: s1rd1 <= 12;
{1'd0, 4'd11}: s1rd1 <= 14;
{1'd0, 4'd12}: s1rd1 <= 0;
{1'd0, 4'd13}: s1rd1 <= 2;
{1'd0, 4'd14}: s1rd1 <= 4;
{1'd0, 4'd15}: s1rd1 <= 6;
endcase
end

{1'd0, 4'd0}: s1rd2 <= 5;
{1'd0, 4'd1}: s1rd2 <= 7;
{1'd0, 4'd2}: s1rd2 <= 1;
{1'd0, 4'd3}: s1rd2 <= 3;
{1'd0, 4'd4}: s1rd2 <= 13;
{1'd0, 4'd5}: s1rd2 <= 15;
{1'd0, 4'd6}: s1rd2 <= 9;
{1'd0, 4'd7}: s1rd2 <= 11;
{1'd0, 4'd8}: s1rd2 <= 4;
{1'd0, 4'd9}: s1rd2 <= 6;
{1'd0, 4'd10}: s1rd2 <= 0;
{1'd0, 4'd11}: s1rd2 <= 2;
{1'd0, 4'd12}: s1rd2 <= 12;
{1'd0, 4'd13}: s1rd2 <= 14;
{1'd0, 4'd14}: s1rd2 <= 8;
{1'd0, 4'd15}: s1rd2 <= 10;
endcase
end

{1'd0, 4'd0}: s1rd3 <= 1;
{1'd0, 4'd1}: s1rd3 <= 3;
{1'd0, 4'd2}: s1rd3 <= 5;
{1'd0, 4'd3}: s1rd3 <= 7;
{1'd0, 4'd4}: s1rd3 <= 9;
{1'd0, 4'd5}: s1rd3 <= 11;
{1'd0, 4'd6}: s1rd3 <= 13;
{1'd0, 4'd7}: s1rd3 <= 15;
{1'd0, 4'd8}: s1rd3 <= 0;
{1'd0, 4'd9}: s1rd3 <= 2;
{1'd0, 4'd10}: s1rd3 <= 4;
{1'd0, 4'd11}: s1rd3 <= 6;
{1'd0, 4'd12}: s1rd3 <= 8;
{1'd0, 4'd13}: s1rd3 <= 10;
{1'd0, 4'd14}: s1rd3 <= 12;
{1'd0, 4'd15}: s1rd3 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd4 <= 12;
{1'd0, 4'd1}: s1rd4 <= 14;
{1'd0, 4'd2}: s1rd4 <= 8;
{1'd0, 4'd3}: s1rd4 <= 10;
{1'd0, 4'd4}: s1rd4 <= 4;
{1'd0, 4'd5}: s1rd4 <= 6;
{1'd0, 4'd6}: s1rd4 <= 0;
{1'd0, 4'd7}: s1rd4 <= 2;
{1'd0, 4'd8}: s1rd4 <= 13;
{1'd0, 4'd9}: s1rd4 <= 15;
{1'd0, 4'd10}: s1rd4 <= 9;
{1'd0, 4'd11}: s1rd4 <= 11;
{1'd0, 4'd12}: s1rd4 <= 5;
{1'd0, 4'd13}: s1rd4 <= 7;
{1'd0, 4'd14}: s1rd4 <= 1;
{1'd0, 4'd15}: s1rd4 <= 3;
endcase
end

{1'd0, 4'd0}: s1rd5 <= 8;
{1'd0, 4'd1}: s1rd5 <= 10;
{1'd0, 4'd2}: s1rd5 <= 12;
{1'd0, 4'd3}: s1rd5 <= 14;
{1'd0, 4'd4}: s1rd5 <= 0;
{1'd0, 4'd5}: s1rd5 <= 2;
{1'd0, 4'd6}: s1rd5 <= 4;
{1'd0, 4'd7}: s1rd5 <= 6;
{1'd0, 4'd8}: s1rd5 <= 9;
{1'd0, 4'd9}: s1rd5 <= 11;
{1'd0, 4'd10}: s1rd5 <= 13;
{1'd0, 4'd11}: s1rd5 <= 15;
{1'd0, 4'd12}: s1rd5 <= 1;
{1'd0, 4'd13}: s1rd5 <= 3;
{1'd0, 4'd14}: s1rd5 <= 5;
{1'd0, 4'd15}: s1rd5 <= 7;
endcase
end

{1'd0, 4'd0}: s1rd6 <= 4;
{1'd0, 4'd1}: s1rd6 <= 6;
{1'd0, 4'd2}: s1rd6 <= 0;
{1'd0, 4'd3}: s1rd6 <= 2;
{1'd0, 4'd4}: s1rd6 <= 12;
{1'd0, 4'd5}: s1rd6 <= 14;
{1'd0, 4'd6}: s1rd6 <= 8;
{1'd0, 4'd7}: s1rd6 <= 10;
{1'd0, 4'd8}: s1rd6 <= 5;
{1'd0, 4'd9}: s1rd6 <= 7;
{1'd0, 4'd10}: s1rd6 <= 1;
{1'd0, 4'd11}: s1rd6 <= 3;
{1'd0, 4'd12}: s1rd6 <= 13;
{1'd0, 4'd13}: s1rd6 <= 15;
{1'd0, 4'd14}: s1rd6 <= 9;
{1'd0, 4'd15}: s1rd6 <= 11;
endcase
end

{1'd0, 4'd0}: s1rd7 <= 0;
{1'd0, 4'd1}: s1rd7 <= 2;
{1'd0, 4'd2}: s1rd7 <= 4;
{1'd0, 4'd3}: s1rd7 <= 6;
{1'd0, 4'd4}: s1rd7 <= 8;
{1'd0, 4'd5}: s1rd7 <= 10;
{1'd0, 4'd6}: s1rd7 <= 12;
{1'd0, 4'd7}: s1rd7 <= 14;
{1'd0, 4'd8}: s1rd7 <= 1;
{1'd0, 4'd9}: s1rd7 <= 3;
{1'd0, 4'd10}: s1rd7 <= 5;
{1'd0, 4'd11}: s1rd7 <= 7;
{1'd0, 4'd12}: s1rd7 <= 9;
{1'd0, 4'd13}: s1rd7 <= 11;
{1'd0, 4'd14}: s1rd7 <= 13;
{1'd0, 4'd15}: s1rd7 <= 15;
endcase
end

{1'd0, 4'd0}: s1rd8 <= 13;
{1'd0, 4'd1}: s1rd8 <= 15;
{1'd0, 4'd2}: s1rd8 <= 9;
{1'd0, 4'd3}: s1rd8 <= 11;
{1'd0, 4'd4}: s1rd8 <= 5;
{1'd0, 4'd5}: s1rd8 <= 7;
{1'd0, 4'd6}: s1rd8 <= 1;
{1'd0, 4'd7}: s1rd8 <= 3;
{1'd0, 4'd8}: s1rd8 <= 12;
{1'd0, 4'd9}: s1rd8 <= 14;
{1'd0, 4'd10}: s1rd8 <= 8;
{1'd0, 4'd11}: s1rd8 <= 10;
{1'd0, 4'd12}: s1rd8 <= 4;
{1'd0, 4'd13}: s1rd8 <= 6;
{1'd0, 4'd14}: s1rd8 <= 0;
{1'd0, 4'd15}: s1rd8 <= 2;
endcase
end

{1'd0, 4'd0}: s1rd9 <= 9;
{1'd0, 4'd1}: s1rd9 <= 11;
{1'd0, 4'd2}: s1rd9 <= 13;
{1'd0, 4'd3}: s1rd9 <= 15;
{1'd0, 4'd4}: s1rd9 <= 1;
{1'd0, 4'd5}: s1rd9 <= 3;
{1'd0, 4'd6}: s1rd9 <= 5;
{1'd0, 4'd7}: s1rd9 <= 7;
{1'd0, 4'd8}: s1rd9 <= 8;
{1'd0, 4'd9}: s1rd9 <= 10;
{1'd0, 4'd10}: s1rd9 <= 12;
{1'd0, 4'd11}: s1rd9 <= 14;
{1'd0, 4'd12}: s1rd9 <= 0;
{1'd0, 4'd13}: s1rd9 <= 2;
{1'd0, 4'd14}: s1rd9 <= 4;
{1'd0, 4'd15}: s1rd9 <= 6;
endcase
end

{1'd0, 4'd0}: s1rd10 <= 5;
{1'd0, 4'd1}: s1rd10 <= 7;
{1'd0, 4'd2}: s1rd10 <= 1;
{1'd0, 4'd3}: s1rd10 <= 3;
{1'd0, 4'd4}: s1rd10 <= 13;
{1'd0, 4'd5}: s1rd10 <= 15;
{1'd0, 4'd6}: s1rd10 <= 9;
{1'd0, 4'd7}: s1rd10 <= 11;
{1'd0, 4'd8}: s1rd10 <= 4;
{1'd0, 4'd9}: s1rd10 <= 6;
{1'd0, 4'd10}: s1rd10 <= 0;
{1'd0, 4'd11}: s1rd10 <= 2;
{1'd0, 4'd12}: s1rd10 <= 12;
{1'd0, 4'd13}: s1rd10 <= 14;
{1'd0, 4'd14}: s1rd10 <= 8;
{1'd0, 4'd15}: s1rd10 <= 10;
endcase
end

{1'd0, 4'd0}: s1rd11 <= 1;
{1'd0, 4'd1}: s1rd11 <= 3;
{1'd0, 4'd2}: s1rd11 <= 5;
{1'd0, 4'd3}: s1rd11 <= 7;
{1'd0, 4'd4}: s1rd11 <= 9;
{1'd0, 4'd5}: s1rd11 <= 11;
{1'd0, 4'd6}: s1rd11 <= 13;
{1'd0, 4'd7}: s1rd11 <= 15;
{1'd0, 4'd8}: s1rd11 <= 0;
{1'd0, 4'd9}: s1rd11 <= 2;
{1'd0, 4'd10}: s1rd11 <= 4;
{1'd0, 4'd11}: s1rd11 <= 6;
{1'd0, 4'd12}: s1rd11 <= 8;
{1'd0, 4'd13}: s1rd11 <= 10;
{1'd0, 4'd14}: s1rd11 <= 12;
{1'd0, 4'd15}: s1rd11 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd12 <= 12;
{1'd0, 4'd1}: s1rd12 <= 14;
{1'd0, 4'd2}: s1rd12 <= 8;
{1'd0, 4'd3}: s1rd12 <= 10;
{1'd0, 4'd4}: s1rd12 <= 4;
{1'd0, 4'd5}: s1rd12 <= 6;
{1'd0, 4'd6}: s1rd12 <= 0;
{1'd0, 4'd7}: s1rd12 <= 2;
{1'd0, 4'd8}: s1rd12 <= 13;
{1'd0, 4'd9}: s1rd12 <= 15;
{1'd0, 4'd10}: s1rd12 <= 9;
{1'd0, 4'd11}: s1rd12 <= 11;
{1'd0, 4'd12}: s1rd12 <= 5;
{1'd0, 4'd13}: s1rd12 <= 7;
{1'd0, 4'd14}: s1rd12 <= 1;
{1'd0, 4'd15}: s1rd12 <= 3;
endcase
end

{1'd0, 4'd0}: s1rd13 <= 8;
{1'd0, 4'd1}: s1rd13 <= 10;
{1'd0, 4'd2}: s1rd13 <= 12;
{1'd0, 4'd3}: s1rd13 <= 14;
{1'd0, 4'd4}: s1rd13 <= 0;
{1'd0, 4'd5}: s1rd13 <= 2;
{1'd0, 4'd6}: s1rd13 <= 4;
{1'd0, 4'd7}: s1rd13 <= 6;
{1'd0, 4'd8}: s1rd13 <= 9;
{1'd0, 4'd9}: s1rd13 <= 11;
{1'd0, 4'd10}: s1rd13 <= 13;
{1'd0, 4'd11}: s1rd13 <= 15;
{1'd0, 4'd12}: s1rd13 <= 1;
{1'd0, 4'd13}: s1rd13 <= 3;
{1'd0, 4'd14}: s1rd13 <= 5;
{1'd0, 4'd15}: s1rd13 <= 7;
endcase
end

{1'd0, 4'd0}: s1rd14 <= 4;
{1'd0, 4'd1}: s1rd14 <= 6;
{1'd0, 4'd2}: s1rd14 <= 0;
{1'd0, 4'd3}: s1rd14 <= 2;
{1'd0, 4'd4}: s1rd14 <= 12;
{1'd0, 4'd5}: s1rd14 <= 14;
{1'd0, 4'd6}: s1rd14 <= 8;
{1'd0, 4'd7}: s1rd14 <= 10;
{1'd0, 4'd8}: s1rd14 <= 5;
{1'd0, 4'd9}: s1rd14 <= 7;
{1'd0, 4'd10}: s1rd14 <= 1;
{1'd0, 4'd11}: s1rd14 <= 3;
{1'd0, 4'd12}: s1rd14 <= 13;
{1'd0, 4'd13}: s1rd14 <= 15;
{1'd0, 4'd14}: s1rd14 <= 9;
{1'd0, 4'd15}: s1rd14 <= 11;
endcase
end

{1'd0, 4'd0}: s1rd15 <= 0;
{1'd0, 4'd1}: s1rd15 <= 2;
{1'd0, 4'd2}: s1rd15 <= 4;
{1'd0, 4'd3}: s1rd15 <= 6;
{1'd0, 4'd4}: s1rd15 <= 8;
{1'd0, 4'd5}: s1rd15 <= 10;
{1'd0, 4'd6}: s1rd15 <= 12;
{1'd0, 4'd7}: s1rd15 <= 14;
{1'd0, 4'd8}: s1rd15 <= 1;
{1'd0, 4'd9}: s1rd15 <= 3;
{1'd0, 4'd10}: s1rd15 <= 5;
{1'd0, 4'd11}: s1rd15 <= 7;
{1'd0, 4'd12}: s1rd15 <= 9;
{1'd0, 4'd13}: s1rd15 <= 11;
{1'd0, 4'd14}: s1rd15 <= 13;
{1'd0, 4'd15}: s1rd15 <= 15;
endcase
end

swNet21440 sw(tm50_d, clk, muxCycle, t0, s0, t1, s1, t2, s2, t3, s3, t4, s4,
t5, s5, t6, s6, t7, s7, t8, s8, t9, s9, t10, s10, t11, s11, t12, s12, t13, s13,
t14, s14, t15, s15);

{1'd0, 4'd0}: s2wr0 <= 14;
{1'd0, 4'd1}: s2wr0 <= 15;
{1'd0, 4'd2}: s2wr0 <= 12;
{1'd0, 4'd3}: s2wr0 <= 13;
{1'd0, 4'd4}: s2wr0 <= 10;
{1'd0, 4'd5}: s2wr0 <= 11;
{1'd0, 4'd6}: s2wr0 <= 8;
{1'd0, 4'd7}: s2wr0 <= 9;
{1'd0, 4'd8}: s2wr0 <= 6;
{1'd0, 4'd9}: s2wr0 <= 7;
{1'd0, 4'd10}: s2wr0 <= 4;
{1'd0, 4'd11}: s2wr0 <= 5;
{1'd0, 4'd12}: s2wr0 <= 2;
{1'd0, 4'd13}: s2wr0 <= 3;
{1'd0, 4'd14}: s2wr0 <= 0;
{1'd0, 4'd15}: s2wr0 <= 1;

{1'd0, 4'd0}: s2wr1 <= 12;
{1'd0, 4'd1}: s2wr1 <= 13;
{1'd0, 4'd2}: s2wr1 <= 14;
{1'd0, 4'd3}: s2wr1 <= 15;
{1'd0, 4'd4}: s2wr1 <= 8;
{1'd0, 4'd5}: s2wr1 <= 9;
{1'd0, 4'd6}: s2wr1 <= 10;
{1'd0, 4'd7}: s2wr1 <= 11;
{1'd0, 4'd8}: s2wr1 <= 4;
{1'd0, 4'd9}: s2wr1 <= 5;
{1'd0, 4'd10}: s2wr1 <= 6;
{1'd0, 4'd11}: s2wr1 <= 7;
{1'd0, 4'd12}: s2wr1 <= 0;
{1'd0, 4'd13}: s2wr1 <= 1;
{1'd0, 4'd14}: s2wr1 <= 2;
{1'd0, 4'd15}: s2wr1 <= 3;

{1'd0, 4'd0}: s2wr2 <= 10;
{1'd0, 4'd1}: s2wr2 <= 11;
{1'd0, 4'd2}: s2wr2 <= 8;
{1'd0, 4'd3}: s2wr2 <= 9;
{1'd0, 4'd4}: s2wr2 <= 14;
{1'd0, 4'd5}: s2wr2 <= 15;
{1'd0, 4'd6}: s2wr2 <= 12;
{1'd0, 4'd7}: s2wr2 <= 13;
{1'd0, 4'd8}: s2wr2 <= 2;
{1'd0, 4'd9}: s2wr2 <= 3;
{1'd0, 4'd10}: s2wr2 <= 0;
{1'd0, 4'd11}: s2wr2 <= 1;
{1'd0, 4'd12}: s2wr2 <= 6;
{1'd0, 4'd13}: s2wr2 <= 7;
{1'd0, 4'd14}: s2wr2 <= 4;
{1'd0, 4'd15}: s2wr2 <= 5;

{1'd0, 4'd0}: s2wr3 <= 8;
{1'd0, 4'd1}: s2wr3 <= 9;
{1'd0, 4'd2}: s2wr3 <= 10;
{1'd0, 4'd3}: s2wr3 <= 11;
{1'd0, 4'd4}: s2wr3 <= 12;
{1'd0, 4'd5}: s2wr3 <= 13;
{1'd0, 4'd6}: s2wr3 <= 14;
{1'd0, 4'd7}: s2wr3 <= 15;
{1'd0, 4'd8}: s2wr3 <= 0;
{1'd0, 4'd9}: s2wr3 <= 1;
{1'd0, 4'd10}: s2wr3 <= 2;
{1'd0, 4'd11}: s2wr3 <= 3;
{1'd0, 4'd12}: s2wr3 <= 4;
{1'd0, 4'd13}: s2wr3 <= 5;
{1'd0, 4'd14}: s2wr3 <= 6;
{1'd0, 4'd15}: s2wr3 <= 7;

{1'd0, 4'd0}: s2wr4 <= 14;
{1'd0, 4'd1}: s2wr4 <= 15;
{1'd0, 4'd2}: s2wr4 <= 12;
{1'd0, 4'd3}: s2wr4 <= 13;
{1'd0, 4'd4}: s2wr4 <= 10;
{1'd0, 4'd5}: s2wr4 <= 11;
{1'd0, 4'd6}: s2wr4 <= 8;
{1'd0, 4'd7}: s2wr4 <= 9;
{1'd0, 4'd8}: s2wr4 <= 6;
{1'd0, 4'd9}: s2wr4 <= 7;
{1'd0, 4'd10}: s2wr4 <= 4;
{1'd0, 4'd11}: s2wr4 <= 5;
{1'd0, 4'd12}: s2wr4 <= 2;
{1'd0, 4'd13}: s2wr4 <= 3;
{1'd0, 4'd14}: s2wr4 <= 0;
{1'd0, 4'd15}: s2wr4 <= 1;

{1'd0, 4'd0}: s2wr5 <= 12;
{1'd0, 4'd1}: s2wr5 <= 13;
{1'd0, 4'd2}: s2wr5 <= 14;
{1'd0, 4'd3}: s2wr5 <= 15;
{1'd0, 4'd4}: s2wr5 <= 8;
{1'd0, 4'd5}: s2wr5 <= 9;
{1'd0, 4'd6}: s2wr5 <= 10;
{1'd0, 4'd7}: s2wr5 <= 11;
{1'd0, 4'd8}: s2wr5 <= 4;
{1'd0, 4'd9}: s2wr5 <= 5;
{1'd0, 4'd10}: s2wr5 <= 6;
{1'd0, 4'd11}: s2wr5 <= 7;
{1'd0, 4'd12}: s2wr5 <= 0;
{1'd0, 4'd13}: s2wr5 <= 1;
{1'd0, 4'd14}: s2wr5 <= 2;
{1'd0, 4'd15}: s2wr5 <= 3;

{1'd0, 4'd0}: s2wr6 <= 10;
{1'd0, 4'd1}: s2wr6 <= 11;
{1'd0, 4'd2}: s2wr6 <= 8;
{1'd0, 4'd3}: s2wr6 <= 9;
{1'd0, 4'd4}: s2wr6 <= 14;
{1'd0, 4'd5}: s2wr6 <= 15;
{1'd0, 4'd6}: s2wr6 <= 12;
{1'd0, 4'd7}: s2wr6 <= 13;
{1'd0, 4'd8}: s2wr6 <= 2;
{1'd0, 4'd9}: s2wr6 <= 3;
{1'd0, 4'd10}: s2wr6 <= 0;
{1'd0, 4'd11}: s2wr6 <= 1;
{1'd0, 4'd12}: s2wr6 <= 6;
{1'd0, 4'd13}: s2wr6 <= 7;
{1'd0, 4'd14}: s2wr6 <= 4;
{1'd0, 4'd15}: s2wr6 <= 5;

{1'd0, 4'd0}: s2wr7 <= 8;
{1'd0, 4'd1}: s2wr7 <= 9;
{1'd0, 4'd2}: s2wr7 <= 10;
{1'd0, 4'd3}: s2wr7 <= 11;
{1'd0, 4'd4}: s2wr7 <= 12;
{1'd0, 4'd5}: s2wr7 <= 13;
{1'd0, 4'd6}: s2wr7 <= 14;
{1'd0, 4'd7}: s2wr7 <= 15;
{1'd0, 4'd8}: s2wr7 <= 0;
{1'd0, 4'd9}: s2wr7 <= 1;
{1'd0, 4'd10}: s2wr7 <= 2;
{1'd0, 4'd11}: s2wr7 <= 3;
{1'd0, 4'd12}: s2wr7 <= 4;
{1'd0, 4'd13}: s2wr7 <= 5;
{1'd0, 4'd14}: s2wr7 <= 6;
{1'd0, 4'd15}: s2wr7 <= 7;

{1'd0, 4'd0}: s2wr8 <= 6;
{1'd0, 4'd1}: s2wr8 <= 7;
{1'd0, 4'd2}: s2wr8 <= 4;
{1'd0, 4'd3}: s2wr8 <= 5;
{1'd0, 4'd4}: s2wr8 <= 2;
{1'd0, 4'd5}: s2wr8 <= 3;
{1'd0, 4'd6}: s2wr8 <= 0;
{1'd0, 4'd7}: s2wr8 <= 1;
{1'd0, 4'd8}: s2wr8 <= 14;
{1'd0, 4'd9}: s2wr8 <= 15;
{1'd0, 4'd10}: s2wr8 <= 12;
{1'd0, 4'd11}: s2wr8 <= 13;
{1'd0, 4'd12}: s2wr8 <= 10;
{1'd0, 4'd13}: s2wr8 <= 11;
{1'd0, 4'd14}: s2wr8 <= 8;
{1'd0, 4'd15}: s2wr8 <= 9;

{1'd0, 4'd0}: s2wr9 <= 4;
{1'd0, 4'd1}: s2wr9 <= 5;
{1'd0, 4'd2}: s2wr9 <= 6;
{1'd0, 4'd3}: s2wr9 <= 7;
{1'd0, 4'd4}: s2wr9 <= 0;
{1'd0, 4'd5}: s2wr9 <= 1;
{1'd0, 4'd6}: s2wr9 <= 2;
{1'd0, 4'd7}: s2wr9 <= 3;
{1'd0, 4'd8}: s2wr9 <= 12;
{1'd0, 4'd9}: s2wr9 <= 13;
{1'd0, 4'd10}: s2wr9 <= 14;
{1'd0, 4'd11}: s2wr9 <= 15;
{1'd0, 4'd12}: s2wr9 <= 8;
{1'd0, 4'd13}: s2wr9 <= 9;
{1'd0, 4'd14}: s2wr9 <= 10;
{1'd0, 4'd15}: s2wr9 <= 11;

{1'd0, 4'd0}: s2wr10 <= 2;
{1'd0, 4'd1}: s2wr10 <= 3;
{1'd0, 4'd2}: s2wr10 <= 0;
{1'd0, 4'd3}: s2wr10 <= 1;
{1'd0, 4'd4}: s2wr10 <= 6;
{1'd0, 4'd5}: s2wr10 <= 7;
{1'd0, 4'd6}: s2wr10 <= 4;
{1'd0, 4'd7}: s2wr10 <= 5;
{1'd0, 4'd8}: s2wr10 <= 10;
{1'd0, 4'd9}: s2wr10 <= 11;
{1'd0, 4'd10}: s2wr10 <= 8;
{1'd0, 4'd11}: s2wr10 <= 9;
{1'd0, 4'd12}: s2wr10 <= 14;
{1'd0, 4'd13}: s2wr10 <= 15;
{1'd0, 4'd14}: s2wr10 <= 12;
{1'd0, 4'd15}: s2wr10 <= 13;

{1'd0, 4'd0}: s2wr11 <= 0;
{1'd0, 4'd1}: s2wr11 <= 1;
{1'd0, 4'd2}: s2wr11 <= 2;
{1'd0, 4'd3}: s2wr11 <= 3;
{1'd0, 4'd4}: s2wr11 <= 4;
{1'd0, 4'd5}: s2wr11 <= 5;
{1'd0, 4'd6}: s2wr11 <= 6;
{1'd0, 4'd7}: s2wr11 <= 7;
{1'd0, 4'd8}: s2wr11 <= 8;
{1'd0, 4'd9}: s2wr11 <= 9;
{1'd0, 4'd10}: s2wr11 <= 10;
{1'd0, 4'd11}: s2wr11 <= 11;
{1'd0, 4'd12}: s2wr11 <= 12;
{1'd0, 4'd13}: s2wr11 <= 13;
{1'd0, 4'd14}: s2wr11 <= 14;
{1'd0, 4'd15}: s2wr11 <= 15;

{1'd0, 4'd0}: s2wr12 <= 6;
{1'd0, 4'd1}: s2wr12 <= 7;
{1'd0, 4'd2}: s2wr12 <= 4;
{1'd0, 4'd3}: s2wr12 <= 5;
{1'd0, 4'd4}: s2wr12 <= 2;
{1'd0, 4'd5}: s2wr12 <= 3;
{1'd0, 4'd6}: s2wr12 <= 0;
{1'd0, 4'd7}: s2wr12 <= 1;
{1'd0, 4'd8}: s2wr12 <= 14;
{1'd0, 4'd9}: s2wr12 <= 15;
{1'd0, 4'd10}: s2wr12 <= 12;
{1'd0, 4'd11}: s2wr12 <= 13;
{1'd0, 4'd12}: s2wr12 <= 10;
{1'd0, 4'd13}: s2wr12 <= 11;
{1'd0, 4'd14}: s2wr12 <= 8;
{1'd0, 4'd15}: s2wr12 <= 9;

{1'd0, 4'd0}: s2wr13 <= 4;
{1'd0, 4'd1}: s2wr13 <= 5;
{1'd0, 4'd2}: s2wr13 <= 6;
{1'd0, 4'd3}: s2wr13 <= 7;
{1'd0, 4'd4}: s2wr13 <= 0;
{1'd0, 4'd5}: s2wr13 <= 1;
{1'd0, 4'd6}: s2wr13 <= 2;
{1'd0, 4'd7}: s2wr13 <= 3;
{1'd0, 4'd8}: s2wr13 <= 12;
{1'd0, 4'd9}: s2wr13 <= 13;
{1'd0, 4'd10}: s2wr13 <= 14;
{1'd0, 4'd11}: s2wr13 <= 15;
{1'd0, 4'd12}: s2wr13 <= 8;
{1'd0, 4'd13}: s2wr13 <= 9;
{1'd0, 4'd14}: s2wr13 <= 10;
{1'd0, 4'd15}: s2wr13 <= 11;

{1'd0, 4'd0}: s2wr14 <= 2;
{1'd0, 4'd1}: s2wr14 <= 3;
{1'd0, 4'd2}: s2wr14 <= 0;
{1'd0, 4'd3}: s2wr14 <= 1;
{1'd0, 4'd4}: s2wr14 <= 6;
{1'd0, 4'd5}: s2wr14 <= 7;
{1'd0, 4'd6}: s2wr14 <= 4;
{1'd0, 4'd7}: s2wr14 <= 5;
{1'd0, 4'd8}: s2wr14 <= 10;
{1'd0, 4'd9}: s2wr14 <= 11;
{1'd0, 4'd10}: s2wr14 <= 8;
{1'd0, 4'd11}: s2wr14 <= 9;
{1'd0, 4'd12}: s2wr14 <= 14;
{1'd0, 4'd13}: s2wr14 <= 15;
{1'd0, 4'd14}: s2wr14 <= 12;
{1'd0, 4'd15}: s2wr14 <= 13;

{1'd0, 4'd0}: s2wr15 <= 0;
{1'd0, 4'd1}: s2wr15 <= 1;
{1'd0, 4'd2}: s2wr15 <= 2;
{1'd0, 4'd3}: s2wr15 <= 3;
{1'd0, 4'd4}: s2wr15 <= 4;
{1'd0, 4'd5}: s2wr15 <= 5;
{1'd0, 4'd6}: s2wr15 <= 6;
{1'd0, 4'd7}: s2wr15 <= 7;
{1'd0, 4'd8}: s2wr15 <= 8;
{1'd0, 4'd9}: s2wr15 <= 9;
{1'd0, 4'd10}: s2wr15 <= 10;
{1'd0, 4'd11}: s2wr15 <= 11;
{1'd0, 4'd12}: s2wr15 <= 12;
{1'd0, 4'd13}: s2wr15 <= 13;
{1'd0, 4'd14}: s2wr15 <= 14;
{1'd0, 4'd15}: s2wr15 <= 15;

endmodule
// Latency: 8
// Gap: 16
module DirSum_23302(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
reg [3:0] i1;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;

i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 15)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock21444 codeBlockIsnt27609(.clk(clk), .reset(reset), .next_in(next),

.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3),
.X4_in(X4), .Y4(Y4),
.X5_in(X5), .Y5(Y5),
.X6_in(X6), .Y6(Y6),
.X7_in(X7), .Y7(Y7),
.X8_in(X8), .Y8(Y8),
.X9_in(X9), .Y9(Y9),
.X10_in(X10), .Y10(Y10),
.X11_in(X11), .Y11(Y11),
.X12_in(X12), .Y12(Y12),
.X13_in(X13), .Y13(Y13),
.X14_in(X14), .Y14(Y14),
.X15_in(X15), .Y15(Y15),
.X16_in(X16), .Y16(Y16),
.X17_in(X17), .Y17(Y17),
.X18_in(X18), .Y18(Y18),
.X19_in(X19), .Y19(Y19),
.X20_in(X20), .Y20(Y20),
.X21_in(X21), .Y21(Y21),
.X22_in(X22), .Y22(Y22),
.X23_in(X23), .Y23(Y23),
.X24_in(X24), .Y24(Y24),
.X25_in(X25), .Y25(Y25),
.X26_in(X26), .Y26(Y26),
.X27_in(X27), .Y27(Y27),
.X28_in(X28), .Y28(Y28),
.X29_in(X29), .Y29(Y29),
.X30_in(X30), .Y30(Y30),
.X31_in(X31), .Y31(Y31));
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h40;
2: out3 <= 8'h3f;
3: out3 <= 8'h3d;
4: out3 <= 8'h3b;
5: out3 <= 8'h38;
6: out3 <= 8'h35;
7: out3 <= 8'h31;
8: out3 <= 8'h2d;
9: out3 <= 8'h29;
10: out3 <= 8'h24;
11: out3 <= 8'h1e;
12: out3 <= 8'h18;
13: out3 <= 8'h13;
14: out3 <= 8'hc;
15: out3 <= 8'h6;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3f;
2: out3 <= 8'h3b;
3: out3 <= 8'h35;
4: out3 <= 8'h2d;
5: out3 <= 8'h24;
6: out3 <= 8'h18;
7: out3 <= 8'hc;
8: out3 <= 8'h0;
9: out3 <= 8'hf4;
10: out3 <= 8'he8;
11: out3 <= 8'hdc;
12: out3 <= 8'hd3;
13: out3 <= 8'hcb;
14: out3 <= 8'hc5;
15: out3 <= 8'hc1;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h40;
2: out3 <= 8'h3e;
3: out3 <= 8'h3d;
4: out3 <= 8'h3b;
5: out3 <= 8'h38;
6: out3 <= 8'h34;
7: out3 <= 8'h30;
8: out3 <= 8'h2c;
9: out3 <= 8'h27;
10: out3 <= 8'h22;
11: out3 <= 8'h1d;
12: out3 <= 8'h17;
13: out3 <= 8'h11;
14: out3 <= 8'hb;
15: out3 <= 8'h5;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3e;
2: out3 <= 8'h3a;
3: out3 <= 8'h33;
4: out3 <= 8'h2b;
5: out3 <= 8'h21;
6: out3 <= 8'h16;
7: out3 <= 8'h9;
8: out3 <= 8'hfd;
9: out3 <= 8'hf0;
10: out3 <= 8'he5;
11: out3 <= 8'hda;
12: out3 <= 8'hd1;
13: out3 <= 8'hc9;
14: out3 <= 8'hc4;
15: out3 <= 8'hc1;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3c;
2: out3 <= 8'h32;
3: out3 <= 8'h25;
4: out3 <= 8'h14;
5: out3 <= 8'h2;
6: out3 <= 8'hef;
7: out3 <= 8'hde;
8: out3 <= 8'hd0;
9: out3 <= 8'hc5;
10: out3 <= 8'hc0;
11: out3 <= 8'hc1;
12: out3 <= 8'hc7;
13: out3 <= 8'hd2;
14: out3 <= 8'he0;
15: out3 <= 8'hf2;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3f;
2: out3 <= 8'h3e;
3: out3 <= 8'h3c;
4: out3 <= 8'h3a;
5: out3 <= 8'h37;
6: out3 <= 8'h33;
7: out3 <= 8'h2f;
8: out3 <= 8'h2b;
9: out3 <= 8'h26;
10: out3 <= 8'h21;
11: out3 <= 8'h1b;
12: out3 <= 8'h16;
13: out3 <= 8'h10;
14: out3 <= 8'h9;
15: out3 <= 8'h3;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3d;
2: out3 <= 8'h38;
3: out3 <= 8'h31;
4: out3 <= 8'h29;
5: out3 <= 8'h1e;
6: out3 <= 8'h13;
7: out3 <= 8'h6;
8: out3 <= 8'hfa;
9: out3 <= 8'hed;
10: out3 <= 8'he2;
11: out3 <= 8'hd7;
12: out3 <= 8'hcf;
13: out3 <= 8'hc8;
14: out3 <= 8'hc3;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3f;
1: out3 <= 8'h3a;
2: out3 <= 8'h2f;
3: out3 <= 8'h21;
4: out3 <= 8'h10;
5: out3 <= 8'hfd;
6: out3 <= 8'hea;
7: out3 <= 8'hda;
8: out3 <= 8'hcd;
9: out3 <= 8'hc4;
10: out3 <= 8'hc0;
11: out3 <= 8'hc2;
12: out3 <= 8'hc9;
13: out3 <= 8'hd5;
14: out3 <= 8'he5;
15: out3 <= 8'hf7;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3f;
2: out3 <= 8'h3e;
3: out3 <= 8'h3c;
4: out3 <= 8'h39;
5: out3 <= 8'h36;
6: out3 <= 8'h32;
7: out3 <= 8'h2e;
8: out3 <= 8'h2a;
9: out3 <= 8'h25;
10: out3 <= 8'h20;
11: out3 <= 8'h1a;
12: out3 <= 8'h14;
13: out3 <= 8'he;
14: out3 <= 8'h8;
15: out3 <= 8'h2;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3f;
1: out3 <= 8'h3c;
2: out3 <= 8'h37;
3: out3 <= 8'h2f;
4: out3 <= 8'h26;
5: out3 <= 8'h1b;
6: out3 <= 8'h10;
7: out3 <= 8'h3;
8: out3 <= 8'hf7;
9: out3 <= 8'hea;
10: out3 <= 8'hdf;
11: out3 <= 8'hd5;
12: out3 <= 8'hcd;
13: out3 <= 8'hc6;
14: out3 <= 8'hc2;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h3e;
1: out3 <= 8'h38;
2: out3 <= 8'h2c;
3: out3 <= 8'h1d;
4: out3 <= 8'hb;
5: out3 <= 8'hf8;
6: out3 <= 8'he6;
7: out3 <= 8'hd6;
8: out3 <= 8'hca;
9: out3 <= 8'hc2;
10: out3 <= 8'hc0;
11: out3 <= 8'hc3;
12: out3 <= 8'hcc;
13: out3 <= 8'hd9;
14: out3 <= 8'he9;
15: out3 <= 8'hfb;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hfa;
2: out3 <= 8'hf4;
3: out3 <= 8'hed;
4: out3 <= 8'he8;
5: out3 <= 8'he2;
6: out3 <= 8'hdc;
7: out3 <= 8'hd7;
8: out3 <= 8'hd3;
9: out3 <= 8'hcf;
10: out3 <= 8'hcb;
11: out3 <= 8'hc8;
12: out3 <= 8'hc5;
13: out3 <= 8'hc3;
14: out3 <= 8'hc1;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule
input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hf4;
2: out3 <= 8'he8;
3: out3 <= 8'hdc;
4: out3 <= 8'hd3;
5: out3 <= 8'hcb;
6: out3 <= 8'hc5;
7: out3 <= 8'hc1;
8: out3 <= 8'hc0;
9: out3 <= 8'hc1;
10: out3 <= 8'hc5;
11: out3 <= 8'hcb;
12: out3 <= 8'hd3;
13: out3 <= 8'hdc;
14: out3 <= 8'he8;
15: out3 <= 8'hf4;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h0;
1: out3 <= 8'hed;
2: out3 <= 8'hdc;
3: out3 <= 8'hcf;
4: out3 <= 8'hc5;
5: out3 <= 8'hc0;
6: out3 <= 8'hc1;
7: out3 <= 8'hc8;
8: out3 <= 8'hd3;
9: out3 <= 8'he2;
10: out3 <= 8'hf4;
11: out3 <= 8'h6;
12: out3 <= 8'h18;
13: out3 <= 8'h29;
14: out3 <= 8'h35;
15: out3 <= 8'h3d;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfe;
1: out3 <= 8'hf8;
2: out3 <= 8'hf2;
3: out3 <= 8'hec;
4: out3 <= 8'he6;
5: out3 <= 8'he0;
6: out3 <= 8'hdb;
7: out3 <= 8'hd6;
8: out3 <= 8'hd2;
9: out3 <= 8'hce;
10: out3 <= 8'hca;
11: out3 <= 8'hc7;
12: out3 <= 8'hc4;
13: out3 <= 8'hc2;
14: out3 <= 8'hc1;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfd;
1: out3 <= 8'hf0;
2: out3 <= 8'he5;
3: out3 <= 8'hda;
4: out3 <= 8'hd1;
5: out3 <= 8'hc9;
6: out3 <= 8'hc4;
7: out3 <= 8'hc1;
8: out3 <= 8'hc0;
9: out3 <= 8'hc2;
10: out3 <= 8'hc6;
11: out3 <= 8'hcd;
12: out3 <= 8'hd5;
13: out3 <= 8'hdf;
14: out3 <= 8'hea;
15: out3 <= 8'hf7;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfb;
1: out3 <= 8'he9;
2: out3 <= 8'hd9;
3: out3 <= 8'hcc;
4: out3 <= 8'hc3;
5: out3 <= 8'hc0;
6: out3 <= 8'hc2;
7: out3 <= 8'hca;
8: out3 <= 8'hd6;
9: out3 <= 8'he6;
10: out3 <= 8'hf8;
11: out3 <= 8'hb;
12: out3 <= 8'h1d;
13: out3 <= 8'h2c;
14: out3 <= 8'h38;
15: out3 <= 8'h3e;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hf2;
1: out3 <= 8'he0;
2: out3 <= 8'hd2;
3: out3 <= 8'hc7;
4: out3 <= 8'hc1;
5: out3 <= 8'hc0;
6: out3 <= 8'hc5;
7: out3 <= 8'hd0;
8: out3 <= 8'hde;
9: out3 <= 8'hef;
10: out3 <= 8'h2;
11: out3 <= 8'h14;
12: out3 <= 8'h25;
13: out3 <= 8'h32;
14: out3 <= 8'h3c;
15: out3 <= 8'h40;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hf7;
1: out3 <= 8'hea;
2: out3 <= 8'hdf;
3: out3 <= 8'hd5;
4: out3 <= 8'hcd;
5: out3 <= 8'hc6;
6: out3 <= 8'hc2;
7: out3 <= 8'hc0;
8: out3 <= 8'hc1;
9: out3 <= 8'hc4;
10: out3 <= 8'hc9;
11: out3 <= 8'hd1;
12: out3 <= 8'hda;
13: out3 <= 8'he5;
14: out3 <= 8'hf0;
15: out3 <= 8'hfd;
default: out3 <= 0;
endcase
end
endmodule
input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfd;
1: out3 <= 8'hf7;
2: out3 <= 8'hf0;
3: out3 <= 8'hea;
4: out3 <= 8'he5;
5: out3 <= 8'hdf;
6: out3 <= 8'hda;
7: out3 <= 8'hd5;
8: out3 <= 8'hd1;
9: out3 <= 8'hcd;
10: out3 <= 8'hc9;
11: out3 <= 8'hc6;
12: out3 <= 8'hc4;
13: out3 <= 8'hc2;
14: out3 <= 8'hc1;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfb;
1: out3 <= 8'hf5;
2: out3 <= 8'hef;
3: out3 <= 8'he9;
4: out3 <= 8'he3;
5: out3 <= 8'hde;
6: out3 <= 8'hd9;
7: out3 <= 8'hd4;
8: out3 <= 8'hd0;
9: out3 <= 8'hcc;
10: out3 <= 8'hc8;
11: out3 <= 8'hc5;
12: out3 <= 8'hc3;
13: out3 <= 8'hc2;
14: out3 <= 8'hc0;
15: out3 <= 8'hc0;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hfa;
1: out3 <= 8'hed;
2: out3 <= 8'he2;
3: out3 <= 8'hd7;
4: out3 <= 8'hcf;
5: out3 <= 8'hc8;
6: out3 <= 8'hc3;
7: out3 <= 8'hc0;
8: out3 <= 8'hc0;
9: out3 <= 8'hc3;
10: out3 <= 8'hc8;
11: out3 <= 8'hcf;
12: out3 <= 8'hd7;
13: out3 <= 8'he2;
14: out3 <= 8'hed;
15: out3 <= 8'hfa;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'hf7;
1: out3 <= 8'he5;
2: out3 <= 8'hd5;
3: out3 <= 8'hc9;
4: out3 <= 8'hc2;
5: out3 <= 8'hc0;
6: out3 <= 8'hc4;
7: out3 <= 8'hcd;
8: out3 <= 8'hda;
9: out3 <= 8'hea;
10: out3 <= 8'hfd;
11: out3 <= 8'h10;
12: out3 <= 8'h21;
13: out3 <= 8'h2f;
14: out3 <= 8'h3a;
15: out3 <= 8'h3f;
default: out3 <= 0;
endcase
end
endmodule

input clk;
output [7:0] out;
input [3:0] addr;

out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 8'h40;
1: out3 <= 8'h3d;
2: out3 <= 8'h35;
3: out3 <= 8'h29;
4: out3 <= 8'h18;
5: out3 <= 8'h6;
6: out3 <= 8'hf4;
7: out3 <= 8'he2;
8: out3 <= 8'hd3;
9: out3 <= 8'hc8;
10: out3 <= 8'hc1;
11: out3 <= 8'hc0;
12: out3 <= 8'hc5;
13: out3 <= 8'hcf;
14: out3 <= 8'hdc;
15: out3 <= 8'hed;
default: out3 <= 0;
endcase
end
endmodule
// Latency: 8
// Gap: 1
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3,
X4_in, Y4,
X5_in, Y5,
X6_in, Y6,
X7_in, Y7,
X8_in, Y8,
X9_in, Y9,
X10_in, Y10,
X11_in, Y11,
X12_in, Y12,
X13_in, Y13,
X14_in, Y14,
X15_in, Y15,
X16_in, Y16,
X17_in, Y17,
X18_in, Y18,
X19_in, Y19,
X20_in, Y20,
X21_in, Y21,
X22_in, Y22,
X23_in, Y23,
X24_in, Y24,
X25_in, Y25,
X26_in, Y26,
X27_in, Y27,
X28_in, Y28,
X29_in, Y29,
X30_in, Y30,
X31_in, Y31);
output next_out;
reg next;
input [3:0] i1_in;
reg [3:0] i1;
input [7:0] X0_in,

X1_in,
X2_in,
X3_in,
X4_in,
X5_in,
X6_in,
X7_in,
X8_in,
X9_in,
X10_in,
X11_in,
X12_in,
X13_in,
X14_in,
X15_in,
X16_in,
X17_in,
X18_in,
X19_in,
X20_in,
X21_in,
X22_in,
X23_in,
X24_in,
X25_in,
X26_in,
X27_in,
X28_in,
X29_in,
X30_in,
X31_in;
reg [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;

assign a418 = X0;

assign a322 = a418;
assign a421 = X1;
assign a326 = a421;
assign a422 = X2;
assign a423 = X3;
assign a426 = X4;
assign a427 = X5;
assign a430 = X6;
assign a431 = X7;
assign a434 = X8;
assign a346 = a434;
assign a437 = X9;
assign a350 = a437;
assign a438 = X10;
assign a439 = X11;
assign a442 = X12;
assign a443 = X13;
assign a446 = X14;
assign a447 = X15;
assign a450 = X16;
assign a370 = a450;
assign a453 = X17;
assign a374 = a453;
assign a454 = X18;
assign a455 = X19;
assign a458 = X20;
assign a459 = X21;
assign a462 = X22;
assign a463 = X23;
assign a466 = X24;
assign a395 = a466;
assign a469 = X25;
assign a399 = a469;
assign a470 = X26;
assign a471 = X27;
assign a474 = X28;
assign a475 = X29;
assign a478 = X30;
assign a479 = X31;
assign a327 = tm53;
assign a329 = tm54;
assign a333 = tm55;
assign a335 = tm56;
assign a339 = tm57;
assign a341 = tm58;
assign a351 = tm61;
assign a353 = tm62;
assign a357 = tm63;
assign a359 = tm64;
assign a363 = tm65;
assign a365 = tm66;
assign a375 = tm69;
assign a377 = tm70;
assign a381 = tm71;
assign a383 = tm72;
assign a388 = tm73;
assign a390 = tm74;
assign a400 = tm77;
assign a402 = tm78;
assign a406 = tm79;
assign a408 = tm80;
assign a412 = tm81;
assign a414 = tm82;
assign Y0 = tm938;
assign Y1 = tm945;
assign Y8 = tm952;
assign Y9 = tm959;
assign Y16 = tm966;
assign Y17 = tm973;
assign Y24 = tm980;
assign Y25 = tm987;


.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));
.rst(reset));

tm152 <= 0;
tm743 <= 0;
tm153 <= 0;
tm747 <= 0;
tm153 <= 0;
tm743 <= 0;
tm152 <= 0;
tm747 <= 0;
tm156 <= 0;
tm759 <= 0;
tm157 <= 0;
tm763 <= 0;
tm157 <= 0;
tm759 <= 0;
tm156 <= 0;
tm763 <= 0;
tm160 <= 0;
tm775 <= 0;
tm161 <= 0;
tm779 <= 0;
tm161 <= 0;
tm775 <= 0;
tm160 <= 0;
tm779 <= 0;
tm168 <= 0;
tm791 <= 0;
tm169 <= 0;
tm795 <= 0;
tm169 <= 0;
tm791 <= 0;
tm168 <= 0;
tm795 <= 0;
tm172 <= 0;
tm807 <= 0;
tm173 <= 0;
tm811 <= 0;
tm173 <= 0;
tm807 <= 0;
tm172 <= 0;
tm811 <= 0;
tm176 <= 0;
tm823 <= 0;
tm177 <= 0;
tm827 <= 0;
tm177 <= 0;
tm823 <= 0;
tm176 <= 0;
tm827 <= 0;
tm184 <= 0;
tm839 <= 0;
tm185 <= 0;
tm843 <= 0;
tm185 <= 0;
tm839 <= 0;
tm184 <= 0;
tm843 <= 0;
tm188 <= 0;
tm855 <= 0;
tm189 <= 0;
tm859 <= 0;
tm189 <= 0;
tm855 <= 0;
tm188 <= 0;
tm859 <= 0;
tm192 <= 0;
tm871 <= 0;
tm193 <= 0;
tm875 <= 0;
tm193 <= 0;
tm871 <= 0;
tm192 <= 0;
tm875 <= 0;
tm200 <= 0;
tm887 <= 0;
tm201 <= 0;
tm891 <= 0;
tm201 <= 0;
tm887 <= 0;
tm200 <= 0;
tm891 <= 0;
tm204 <= 0;
tm903 <= 0;
tm205 <= 0;
tm907 <= 0;
tm205 <= 0;
tm903 <= 0;
tm204 <= 0;
tm907 <= 0;
tm208 <= 0;
tm919 <= 0;
tm209 <= 0;
tm923 <= 0;
tm209 <= 0;
tm919 <= 0;
tm208 <= 0;
tm923 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
X4 <= X4_in;
X5 <= X5_in;
X6 <= X6_in;
X7 <= X7_in;
X8 <= X8_in;
X9 <= X9_in;
X10 <= X10_in;
X11 <= X11_in;
X12 <= X12_in;
X13 <= X13_in;
X14 <= X14_in;
X15 <= X15_in;
X16 <= X16_in;
X17 <= X17_in;
X18 <= X18_in;
X19 <= X19_in;
X20 <= X20_in;
X21 <= X21_in;
X22 <= X22_in;
X23 <= X23_in;
X24 <= X24_in;
X25 <= X25_in;
X26 <= X26_in;
X27 <= X27_in;
X28 <= X28_in;
X29 <= X29_in;
X30 <= X30_in;
X31 <= X31_in;
next <= next_in;
tm740 <= a422;
tm744 <= a423;
tm756 <= a426;
tm760 <= a427;
tm772 <= a430;
tm776 <= a431;
tm788 <= a438;
tm792 <= a439;
tm804 <= a442;
tm808 <= a443;
tm820 <= a446;
tm824 <= a447;
tm836 <= a454;
tm840 <= a455;
tm852 <= a458;
tm856 <= a459;
tm868 <= a462;
tm872 <= a463;
tm884 <= a470;
tm888 <= a471;
tm900 <= a474;
tm904 <= a475;
tm916 <= a478;
tm920 <= a479;
tm932 <= a322;
tm939 <= a326;
tm946 <= a346;
tm953 <= a350;
tm960 <= a370;
tm967 <= a374;
tm974 <= a395;
tm981 <= a399;
tm741 <= tm740;
tm745 <= tm744;
tm757 <= tm756;
tm761 <= tm760;
tm773 <= tm772;
tm777 <= tm776;
tm789 <= tm788;
tm793 <= tm792;
tm805 <= tm804;
tm809 <= tm808;
tm821 <= tm820;
tm825 <= tm824;
tm837 <= tm836;
tm841 <= tm840;
tm853 <= tm852;
tm857 <= tm856;
tm869 <= tm868;
tm873 <= tm872;
tm885 <= tm884;
tm889 <= tm888;
tm901 <= tm900;
tm905 <= tm904;
tm917 <= tm916;
tm921 <= tm920;
tm933 <= tm932;
tm940 <= tm939;
tm947 <= tm946;
tm954 <= tm953;
tm961 <= tm960;
tm968 <= tm967;
tm975 <= tm974;
tm982 <= tm981;
tm742 <= tm741;
tm746 <= tm745;
tm758 <= tm757;
tm762 <= tm761;
tm774 <= tm773;
tm778 <= tm777;
tm790 <= tm789;
tm794 <= tm793;
tm806 <= tm805;
tm810 <= tm809;
tm822 <= tm821;
tm826 <= tm825;
tm838 <= tm837;
tm842 <= tm841;
tm854 <= tm853;
tm858 <= tm857;
tm870 <= tm869;
tm874 <= tm873;
tm886 <= tm885;
tm890 <= tm889;
tm902 <= tm901;
tm906 <= tm905;
tm918 <= tm917;
tm922 <= tm921;
tm934 <= tm933;
tm941 <= tm940;
tm948 <= tm947;
tm955 <= tm954;
tm962 <= tm961;
tm969 <= tm968;
tm976 <= tm975;
tm983 <= tm982;
tm152 <= a327;
tm153 <= a329;
tm156 <= a333;
tm157 <= a335;
tm160 <= a339;
tm161 <= a341;
tm168 <= a351;
tm169 <= a353;
tm172 <= a357;
tm173 <= a359;
tm176 <= a363;
tm177 <= a365;
tm184 <= a375;
tm185 <= a377;
tm188 <= a381;
tm189 <= a383;
tm192 <= a388;
tm193 <= a390;
tm200 <= a400;
tm201 <= a402;
tm204 <= a406;
tm205 <= a408;
tm208 <= a412;
tm209 <= a414;
tm743 <= tm742;
tm747 <= tm746;
tm759 <= tm758;
tm763 <= tm762;
tm775 <= tm774;
tm779 <= tm778;
tm791 <= tm790;
tm795 <= tm794;
tm807 <= tm806;
tm811 <= tm810;
tm823 <= tm822;
tm827 <= tm826;
tm839 <= tm838;
tm843 <= tm842;
tm855 <= tm854;
tm859 <= tm858;
tm871 <= tm870;
tm875 <= tm874;
tm887 <= tm886;
tm891 <= tm890;
tm903 <= tm902;
tm907 <= tm906;
tm919 <= tm918;
tm923 <= tm922;
tm935 <= tm934;
tm942 <= tm941;
tm949 <= tm948;
tm956 <= tm955;
tm963 <= tm962;
tm970 <= tm969;
tm977 <= tm976;
tm984 <= tm983;
tm936 <= tm935;
tm943 <= tm942;
tm950 <= tm949;
tm957 <= tm956;
tm964 <= tm963;
tm971 <= tm970;
tm978 <= tm977;
tm985 <= tm984;
tm937 <= tm936;
tm944 <= tm943;
tm951 <= tm950;
tm958 <= tm957;
tm965 <= tm964;
tm972 <= tm971;
tm979 <= tm978;
tm986 <= tm985;
tm938 <= tm937;
tm945 <= tm944;
tm952 <= tm951;
tm959 <= tm958;
tm966 <= tm965;
tm973 <= tm972;
tm980 <= tm979;
tm987 <= tm986;
end
end
endmodule
// Latency: 3
// Gap: 1
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3,
X4_in, Y4,
X5_in, Y5,
X6_in, Y6,
X7_in, Y7,
X8_in, Y8,
X9_in, Y9,
X10_in, Y10,
X11_in, Y11,
X12_in, Y12,
X13_in, Y13,
X14_in, Y14,
X15_in, Y15,
X16_in, Y16,
X17_in, Y17,
X18_in, Y18,
X19_in, Y19,
X20_in, Y20,
X21_in, Y21,
X22_in, Y22,
X23_in, Y23,
X24_in, Y24,
X25_in, Y25,
X26_in, Y26,
X27_in, Y27,
X28_in, Y28,
X29_in, Y29,
X30_in, Y30,
X31_in, Y31);
output next_out;
reg next;
input [7:0] X0_in,

X1_in,
X2_in,
X3_in,
X4_in,
X5_in,
X6_in,
X7_in,
X8_in,
X9_in,
X10_in,
X11_in,
X12_in,
X13_in,
X14_in,
X15_in,
X16_in,
X17_in,
X18_in,
X19_in,
X20_in,
X21_in,
X22_in,
X23_in,
X24_in,
X25_in,
X26_in,
X27_in,
X28_in,
X29_in,
X30_in,
X31_in;
reg [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;

assign a65 = X0;

assign a66 = X4;
assign a67 = X1;
assign a68 = X5;
assign a73 = X2;
assign a74 = X6;
assign a75 = X3;
assign a76 = X7;
assign a81 = X8;
assign a82 = X12;
assign a83 = X9;
assign a84 = X13;
assign a89 = X10;
assign a90 = X14;
assign a91 = X11;
assign a92 = X15;
assign a97 = X16;
assign a98 = X20;
assign a99 = X17;
assign a100 = X21;
assign a105 = X18;
assign a106 = X22;
assign a107 = X19;
assign a108 = X23;
assign a113 = X24;
assign a114 = X28;
assign a115 = X25;
assign a116 = X29;
assign a121 = X26;
assign a122 = X30;
assign a123 = X27;
assign a124 = X31;
assign Y0 = t410;
assign Y1 = t411;
assign Y4 = t412;
assign Y5 = t413;
assign Y2 = t414;
assign Y3 = t415;
assign Y6 = t416;
assign Y7 = t417;
assign Y8 = t426;
assign Y9 = t427;
assign Y12 = t428;
assign Y13 = t429;
assign Y10 = t430;
assign Y11 = t431;
assign Y14 = t432;
assign Y15 = t433;
assign Y16 = t442;
assign Y17 = t443;
assign Y20 = t444;
assign Y21 = t445;
assign Y18 = t446;
assign Y19 = t447;
assign Y22 = t448;
assign Y23 = t449;
assign Y24 = t458;
assign Y25 = t459;
assign Y28 = t460;
assign Y29 = t461;
assign Y26 = t462;
assign Y27 = t463;
assign Y30 = t464;
assign Y31 = t465;


end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
X4 <= X4_in;
X5 <= X5_in;
X6 <= X6_in;
X7 <= X7_in;
X8 <= X8_in;
X9 <= X9_in;
X10 <= X10_in;
X11 <= X11_in;
X12 <= X12_in;
X13 <= X13_in;
X14 <= X14_in;
X15 <= X15_in;
X16 <= X16_in;
X17 <= X17_in;
X18 <= X18_in;
X19 <= X19_in;
X20 <= X20_in;
X21 <= X21_in;
X22 <= X22_in;
X23 <= X23_in;
X24 <= X24_in;
X25 <= X25_in;
X26 <= X26_in;
X27 <= X27_in;
X28 <= X28_in;
X29 <= X29_in;
X30 <= X30_in;
X31 <= X31_in;
next <= next_in;
end
end
endmodule
// Latency: 39
// Gap: 16
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3,
X4, Y4,
X5, Y5,
X6, Y6,
X7, Y7,
X8, Y8,
X9, Y9,
X10, Y10,
X11, Y11,
X12, Y12,
X13, Y13,
X14, Y14,
X15, Y15,
X16, Y16,
X17, Y17,
X18, Y18,
X19, Y19,
X20, Y20,
X21, Y21,
X22, Y22,
X23, Y23,
X24, Y24,
X25, Y25,
X26, Y26,
X27, Y27,
X28, Y28,
X29, Y29,
X30, Y30,
X31, Y31);
output next_out;
input [7:0] X0,

X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31;
output [7:0] Y0,

Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11,
Y12,
Y13,
Y14,
Y15,
Y16,
Y17,
Y18,
Y19,
Y20,
Y21,
Y22,
Y23,
Y24,
Y25,
Y26,
Y27,
Y28,
Y29,
Y30,
Y31;
wire [15:0] t0;

wire [15:0] s0;
wire [15:0] t1;
wire [15:0] s1;
wire [15:0] t2;
wire [15:0] s2;
wire [15:0] t3;
wire [15:0] s3;
wire [15:0] t4;
wire [15:0] s4;
wire [15:0] t5;
wire [15:0] s5;
assign t5 = {X10, X11};
wire [15:0] t6;
wire [15:0] s6;
assign t6 = {X12, X13};
wire [15:0] t7;
wire [15:0] s7;
assign t7 = {X14, X15};
wire [15:0] t8;
wire [15:0] s8;
assign t8 = {X16, X17};
wire [15:0] t9;
wire [15:0] s9;
assign t9 = {X18, X19};
wire [15:0] t10;
wire [15:0] s10;
assign t10 = {X20, X21};
wire [15:0] t11;
wire [15:0] s11;
assign t11 = {X22, X23};
wire [15:0] t12;
wire [15:0] s12;
assign t12 = {X24, X25};
wire [15:0] t13;
wire [15:0] s13;
assign t13 = {X26, X27};
wire [15:0] t14;
wire [15:0] s14;
assign t14 = {X28, X29};
wire [15:0] t15;
wire [15:0] s15;
assign t15 = {X30, X31};
assign Y0 = s0[15:8];
assign Y2 = s1[15:8];
assign Y4 = s2[15:8];
assign Y6 = s3[15:8];
assign Y8 = s4[15:8];
assign Y10 = s5[15:8];
assign Y11 = s5[7:0];
assign Y12 = s6[15:8];
assign Y13 = s6[7:0];
assign Y14 = s7[15:8];
assign Y15 = s7[7:0];
assign Y16 = s8[15:8];
assign Y17 = s8[7:0];
assign Y18 = s9[15:8];
assign Y19 = s9[7:0];
assign Y20 = s10[15:8];
assign Y21 = s10[7:0];
assign Y22 = s11[15:8];
assign Y23 = s11[7:0];
assign Y24 = s12[15:8];
assign Y25 = s12[7:0];
assign Y26 = s13[15:8];
assign Y27 = s13[7:0];
assign Y28 = s14[15:8];
assign Y29 = s14[7:0];
assign Y30 = s15[15:8];
assign Y31 = s15[7:0];

.x1(t1), .y1(s1),
.x2(t2), .y2(s2),
.x3(t3), .y3(s3),
.x4(t4), .y4(s4),
.x5(t5), .y5(s5),
.x6(t6), .y6(s6),
.x7(t7), .y7(s7),
.x8(t8), .y8(s8),
.x9(t9), .y9(s9),
.x10(t10), .y10(s10),
.x11(t11), .y11(s11),
.x12(t12), .y12(s12),
.x13(t13), .y13(s13),
.x14(t14), .y14(s14),
.x15(t15), .y15(s15),
);
endmodule

, x0, y0
, x1, y1
, x2, y2
, x3, y3
, x4, y4
, x5, y5
, x6, y6
, x7, y7
, x8, y8
, x9, y9
, x10, y10
, x11, y11
, x12, y12
, x13, y13
, x14, y14
, x15, y15
);
input [3:0] ct;

input clk;
input [0:0] itr;
t0_10, t0_11, t0_12, t0_13, t0_14, t0_15;
t1_10, t1_11, t1_12, t1_13, t1_14, t1_15;
t2_10, t2_11, t2_12, t2_13, t2_14, t2_15;
t3_10, t3_11, t3_12, t3_13, t3_14, t3_15;
t4_10, t4_11, t4_12, t4_13, t4_14, t4_15;
t5_10, t5_11, t5_12, t5_13, t5_14, t5_15;
t6_10, t6_11, t6_12, t6_13, t6_14, t6_15;
t7_10, t7_11, t7_12, t7_13, t7_14, t7_15;
t8_10, t8_11, t8_12, t8_13, t8_14, t8_15;
t9_10, t9_11, t9_12, t9_13, t9_14, t9_15;
t10_9, t10_10, t10_11, t10_12, t10_13, t10_14, t10_15;
t11_9, t11_10, t11_11, t11_12, t11_13, t11_14, t11_15;
t12_9, t12_10, t12_11, t12_12, t12_13, t12_14, t12_15;
t13_9, t13_10, t13_11, t13_12, t13_13, t13_14, t13_15;
reg [15:0] control;

case(ct)
4'd0: control <= 16'b1100110011001100;
4'd1: control <= 16'b1100110011001100;
4'd2: control <= 16'b1100110011001100;
4'd3: control <= 16'b1100110011001100;
4'd4: control <= 16'b0011001111001100;
4'd5: control <= 16'b0011001111001100;
4'd6: control <= 16'b0011001111001100;
4'd7: control <= 16'b0011001111001100;
4'd8: control <= 16'b1100110000110011;
4'd9: control <= 16'b1100110000110011;
4'd10: control <= 16'b1100110000110011;
4'd11: control <= 16'b1100110000110011;
4'd12: control <= 16'b0011001100110011;
4'd13: control <= 16'b0011001100110011;
4'd14: control <= 16'b0011001100110011;
4'd15: control <= 16'b0011001100110011;
endcase
end

end
assign t0_0 = x0;
assign t0_1 = x8;
assign t0_2 = x1;
assign t0_3 = x9;
assign t0_4 = x2;
assign t0_5 = x10;
assign t0_6 = x3;
assign t0_7 = x11;
assign t0_8 = x4;
assign t0_9 = x12;
assign t0_10 = x5;
assign t0_11 = x13;
assign t0_12 = x6;
assign t0_13 = x14;
assign t0_14 = x7;
assign t0_15 = x15;
assign t1_0 = t0_0;
assign t1_1 = t0_1;
assign t1_2 = t0_2;
assign t1_3 = t0_3;
assign t1_4 = t0_5;
assign t1_5 = t0_4;
assign t1_6 = t0_7;
assign t1_7 = t0_6;
assign t1_8 = t0_8;
assign t1_9 = t0_9;
assign t1_10 = t0_10;
assign t1_11 = t0_11;
assign t1_12 = t0_13;
assign t1_13 = t0_12;
assign t1_14 = t0_15;
assign t1_15 = t0_14;
assign t2_0 = t1_0;
assign t2_1 = t1_8;
assign t2_2 = t1_1;
assign t2_3 = t1_9;
assign t2_4 = t1_2;
assign t2_6 = t1_3;
assign t2_8 = t1_4;
assign t2_11 = t1_13;
assign t2_13 = t1_14;
assign t2_15 = t1_15;
t3_0 <= t2_0;
t3_1 <= t2_1;
t3_2 <= t2_2;
t3_3 <= t2_3;
t3_4 <= t2_5;
t3_5 <= t2_4;
t3_6 <= t2_7;
t3_7 <= t2_6;
t3_8 <= t2_8;
t3_9 <= t2_9;
t3_10 <= t2_10;
t3_11 <= t2_11;
t3_12 <= t2_13;
t3_13 <= t2_12;
t3_14 <= t2_15;
t3_15 <= t2_14;
end
assign t4_0 = t3_0;
assign t4_1 = t3_8;
assign t4_2 = t3_1;
assign t4_3 = t3_9;
assign t4_4 = t3_2;
assign t4_6 = t3_3;
assign t4_8 = t3_4;
assign t4_11 = t3_13;
assign t4_13 = t3_14;
assign t4_15 = t3_15;
assign t5_0 = t4_0;
assign t5_1 = t4_1;
assign t5_2 = t4_2;
assign t5_3 = t4_3;
assign t5_4 = t4_4;
assign t5_5 = t4_5;
assign t5_6 = t4_6;
assign t5_7 = t4_7;
assign t5_8 = t4_8;
assign t5_9 = t4_9;
assign t5_10 = t4_10;
assign t5_11 = t4_11;
assign t5_12 = t4_12;
assign t5_13 = t4_13;
assign t5_14 = t4_14;
assign t5_15 = t4_15;
assign t6_0 = t5_0;
assign t6_1 = t5_8;
assign t6_2 = t5_1;
assign t6_3 = t5_9;
assign t6_4 = t5_2;
assign t6_6 = t5_3;
assign t6_8 = t5_4;
assign t6_11 = t5_13;
assign t6_13 = t5_14;
assign t6_15 = t5_15;
t7_0 <= t6_0;
t7_1 <= t6_1;
t7_2 <= t6_2;
t7_3 <= t6_3;
t7_4 <= t6_5;
t7_5 <= t6_4;
t7_6 <= t6_7;
t7_7 <= t6_6;
t7_8 <= t6_8;
t7_9 <= t6_9;
t7_10 <= t6_10;
t7_11 <= t6_11;
t7_12 <= t6_13;
t7_13 <= t6_12;
t7_14 <= t6_15;
t7_15 <= t6_14;
end
assign t8_0 = t7_0;
assign t8_1 = t7_2;
assign t8_2 = t7_4;
assign t8_3 = t7_6;
assign t8_4 = t7_8;
assign t8_8 = t7_1;
assign t8_9 = t7_3;
assign t8_13 = t7_11;
assign t8_14 = t7_13;
assign t8_15 = t7_15;
assign t9_0 = t8_0;
assign t9_1 = t8_1;
assign t9_2 = t8_2;
assign t9_3 = t8_3;
assign t9_4 = t8_5;
assign t9_5 = t8_4;
assign t9_6 = t8_7;
assign t9_7 = t8_6;
assign t9_8 = t8_8;
assign t9_9 = t8_9;
assign t9_10 = t8_10;
assign t9_11 = t8_11;
assign t9_12 = t8_13;
assign t9_13 = t8_12;
assign t9_14 = t8_15;
assign t9_15 = t8_14;
assign t10_5 = t9_10;
assign t10_6 = t9_12;
assign t10_7 = t9_14;
assign t10_10 = t9_5;
assign t10_11 = t9_7;
assign t10_12 = t9_9;
assign t10_13 = t9_11;
assign t10_14 = t9_13;
assign t10_15 = t9_15;
t11_0 <= (control2[15] == 0) ? t10_0 : t10_1;
t11_1 <= (control2[15] == 0) ? t10_1 : t10_0;
t11_2 <= (control2[14] == 0) ? t10_2 : t10_3;
t11_3 <= (control2[14] == 0) ? t10_3 : t10_2;
t11_4 <= (control2[13] == 0) ? t10_4 : t10_5;
t11_5 <= (control2[13] == 0) ? t10_5 : t10_4;
t11_6 <= (control2[12] == 0) ? t10_6 : t10_7;
t11_7 <= (control2[12] == 0) ? t10_7 : t10_6;
t11_8 <= (control2[11] == 0) ? t10_8 : t10_9;
t11_9 <= (control2[11] == 0) ? t10_9 : t10_8;
t11_10 <= (control2[10] == 0) ? t10_10 : t10_11;
t11_11 <= (control2[10] == 0) ? t10_11 : t10_10;
t11_12 <= (control2[9] == 0) ? t10_12 : t10_13;
t11_13 <= (control2[9] == 0) ? t10_13 : t10_12;
t11_14 <= (control2[8] == 0) ? t10_14 : t10_15;
t11_15 <= (control2[8] == 0) ? t10_15 : t10_14;
end
assign t12_0 = t11_0;
assign t12_1 = t11_2;
assign t12_2 = t11_4;
assign t12_3 = t11_6;
assign t12_4 = t11_8;
assign t12_5 = t11_10;
assign t12_6 = t11_12;
assign t12_7 = t11_14;
assign t12_8 = t11_1;
assign t12_9 = t11_3;
assign t12_10 = t11_5;
assign t12_11 = t11_7;
assign t12_12 = t11_9;
assign t12_13 = t11_11;
assign t12_14 = t11_13;
assign t12_15 = t11_15;
t13_0 <= (control3[7] == 0) ? t12_0 : t12_1;
t13_1 <= (control3[7] == 0) ? t12_1 : t12_0;
t13_2 <= (control3[6] == 0) ? t12_2 : t12_3;
t13_3 <= (control3[6] == 0) ? t12_3 : t12_2;
t13_4 <= (control3[5] == 0) ? t12_4 : t12_5;
t13_5 <= (control3[5] == 0) ? t12_5 : t12_4;
t13_6 <= (control3[4] == 0) ? t12_6 : t12_7;
t13_7 <= (control3[4] == 0) ? t12_7 : t12_6;
t13_8 <= (control3[3] == 0) ? t12_8 : t12_9;
t13_9 <= (control3[3] == 0) ? t12_9 : t12_8;
t13_10 <= (control3[2] == 0) ? t12_10 : t12_11;
t13_11 <= (control3[2] == 0) ? t12_11 : t12_10;
t13_12 <= (control3[1] == 0) ? t12_12 : t12_13;
t13_13 <= (control3[1] == 0) ? t12_13 : t12_12;
t13_14 <= (control3[0] == 0) ? t12_14 : t12_15;
t13_15 <= (control3[0] == 0) ? t12_15 : t12_14;
end
y0 <= t13_0;
y1 <= t13_2;
y2 <= t13_4;
y3 <= t13_6;
y4 <= t13_8;
y5 <= t13_10;
y6 <= t13_12;
y7 <= t13_14;
y8 <= t13_1;
y9 <= t13_3;
y10 <= t13_5;
y11 <= t13_7;
y12 <= t13_9;
y13 <= t13_11;
y14 <= t13_13;
y15 <= t13_15;
end
endmodule
// Latency: 39
// Gap: 16
x0, y0,
x1, y1,
x2, y2,
x3, y3,
x4, y4,
x5, y5,
x6, y6,
x7, y7,
x8, y8,
x9, y9,
x10, y10,
x11, y11,
x12, y12,
x13, y13,
x14, y14,
x15, y15);

output next_out;

wire [0:0] tm83;

assign tm83 = 0;






state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
end
endcase
end
end

state2 <= 0;
outFlip0_z <= 0;
end
s1rdloc <= 0;
state2 <= 1;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
end
1: begin
state2 <= 1;
end
endcase
end
end

state3 <= 0;
outFlip1 <= 0;
end
s2rdloc <= 0;
state3 <= 1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
end
1: begin
state3 <= 1;
end
endcase
end
end
{1'd0, 4'd0}: s1rd0 <= 3;
{1'd0, 4'd1}: s1rd0 <= 7;
{1'd0, 4'd2}: s1rd0 <= 11;
{1'd0, 4'd3}: s1rd0 <= 15;
{1'd0, 4'd4}: s1rd0 <= 2;
{1'd0, 4'd5}: s1rd0 <= 6;
{1'd0, 4'd6}: s1rd0 <= 10;
{1'd0, 4'd7}: s1rd0 <= 14;
{1'd0, 4'd8}: s1rd0 <= 1;
{1'd0, 4'd9}: s1rd0 <= 5;
{1'd0, 4'd10}: s1rd0 <= 9;
{1'd0, 4'd11}: s1rd0 <= 13;
{1'd0, 4'd12}: s1rd0 <= 0;
{1'd0, 4'd13}: s1rd0 <= 4;
{1'd0, 4'd14}: s1rd0 <= 8;
{1'd0, 4'd15}: s1rd0 <= 12;
endcase
end

{1'd0, 4'd0}: s1rd1 <= 2;
{1'd0, 4'd1}: s1rd1 <= 6;
{1'd0, 4'd2}: s1rd1 <= 10;
{1'd0, 4'd3}: s1rd1 <= 14;
{1'd0, 4'd4}: s1rd1 <= 3;
{1'd0, 4'd5}: s1rd1 <= 7;
{1'd0, 4'd6}: s1rd1 <= 11;
{1'd0, 4'd7}: s1rd1 <= 15;
{1'd0, 4'd8}: s1rd1 <= 0;
{1'd0, 4'd9}: s1rd1 <= 4;
{1'd0, 4'd10}: s1rd1 <= 8;
{1'd0, 4'd11}: s1rd1 <= 12;
{1'd0, 4'd12}: s1rd1 <= 1;
{1'd0, 4'd13}: s1rd1 <= 5;
{1'd0, 4'd14}: s1rd1 <= 9;
{1'd0, 4'd15}: s1rd1 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd2 <= 1;
{1'd0, 4'd1}: s1rd2 <= 5;
{1'd0, 4'd2}: s1rd2 <= 9;
{1'd0, 4'd3}: s1rd2 <= 13;
{1'd0, 4'd4}: s1rd2 <= 0;
{1'd0, 4'd5}: s1rd2 <= 4;
{1'd0, 4'd6}: s1rd2 <= 8;
{1'd0, 4'd7}: s1rd2 <= 12;
{1'd0, 4'd8}: s1rd2 <= 3;
{1'd0, 4'd9}: s1rd2 <= 7;
{1'd0, 4'd10}: s1rd2 <= 11;
{1'd0, 4'd11}: s1rd2 <= 15;
{1'd0, 4'd12}: s1rd2 <= 2;
{1'd0, 4'd13}: s1rd2 <= 6;
{1'd0, 4'd14}: s1rd2 <= 10;
{1'd0, 4'd15}: s1rd2 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd3 <= 0;
{1'd0, 4'd1}: s1rd3 <= 4;
{1'd0, 4'd2}: s1rd3 <= 8;
{1'd0, 4'd3}: s1rd3 <= 12;
{1'd0, 4'd4}: s1rd3 <= 1;
{1'd0, 4'd5}: s1rd3 <= 5;
{1'd0, 4'd6}: s1rd3 <= 9;
{1'd0, 4'd7}: s1rd3 <= 13;
{1'd0, 4'd8}: s1rd3 <= 2;
{1'd0, 4'd9}: s1rd3 <= 6;
{1'd0, 4'd10}: s1rd3 <= 10;
{1'd0, 4'd11}: s1rd3 <= 14;
{1'd0, 4'd12}: s1rd3 <= 3;
{1'd0, 4'd13}: s1rd3 <= 7;
{1'd0, 4'd14}: s1rd3 <= 11;
{1'd0, 4'd15}: s1rd3 <= 15;
endcase
end

{1'd0, 4'd0}: s1rd4 <= 3;
{1'd0, 4'd1}: s1rd4 <= 7;
{1'd0, 4'd2}: s1rd4 <= 11;
{1'd0, 4'd3}: s1rd4 <= 15;
{1'd0, 4'd4}: s1rd4 <= 2;
{1'd0, 4'd5}: s1rd4 <= 6;
{1'd0, 4'd6}: s1rd4 <= 10;
{1'd0, 4'd7}: s1rd4 <= 14;
{1'd0, 4'd8}: s1rd4 <= 1;
{1'd0, 4'd9}: s1rd4 <= 5;
{1'd0, 4'd10}: s1rd4 <= 9;
{1'd0, 4'd11}: s1rd4 <= 13;
{1'd0, 4'd12}: s1rd4 <= 0;
{1'd0, 4'd13}: s1rd4 <= 4;
{1'd0, 4'd14}: s1rd4 <= 8;
{1'd0, 4'd15}: s1rd4 <= 12;
endcase
end

{1'd0, 4'd0}: s1rd5 <= 2;
{1'd0, 4'd1}: s1rd5 <= 6;
{1'd0, 4'd2}: s1rd5 <= 10;
{1'd0, 4'd3}: s1rd5 <= 14;
{1'd0, 4'd4}: s1rd5 <= 3;
{1'd0, 4'd5}: s1rd5 <= 7;
{1'd0, 4'd6}: s1rd5 <= 11;
{1'd0, 4'd7}: s1rd5 <= 15;
{1'd0, 4'd8}: s1rd5 <= 0;
{1'd0, 4'd9}: s1rd5 <= 4;
{1'd0, 4'd10}: s1rd5 <= 8;
{1'd0, 4'd11}: s1rd5 <= 12;
{1'd0, 4'd12}: s1rd5 <= 1;
{1'd0, 4'd13}: s1rd5 <= 5;
{1'd0, 4'd14}: s1rd5 <= 9;
{1'd0, 4'd15}: s1rd5 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd6 <= 1;
{1'd0, 4'd1}: s1rd6 <= 5;
{1'd0, 4'd2}: s1rd6 <= 9;
{1'd0, 4'd3}: s1rd6 <= 13;
{1'd0, 4'd4}: s1rd6 <= 0;
{1'd0, 4'd5}: s1rd6 <= 4;
{1'd0, 4'd6}: s1rd6 <= 8;
{1'd0, 4'd7}: s1rd6 <= 12;
{1'd0, 4'd8}: s1rd6 <= 3;
{1'd0, 4'd9}: s1rd6 <= 7;
{1'd0, 4'd10}: s1rd6 <= 11;
{1'd0, 4'd11}: s1rd6 <= 15;
{1'd0, 4'd12}: s1rd6 <= 2;
{1'd0, 4'd13}: s1rd6 <= 6;
{1'd0, 4'd14}: s1rd6 <= 10;
{1'd0, 4'd15}: s1rd6 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd7 <= 0;
{1'd0, 4'd1}: s1rd7 <= 4;
{1'd0, 4'd2}: s1rd7 <= 8;
{1'd0, 4'd3}: s1rd7 <= 12;
{1'd0, 4'd4}: s1rd7 <= 1;
{1'd0, 4'd5}: s1rd7 <= 5;
{1'd0, 4'd6}: s1rd7 <= 9;
{1'd0, 4'd7}: s1rd7 <= 13;
{1'd0, 4'd8}: s1rd7 <= 2;
{1'd0, 4'd9}: s1rd7 <= 6;
{1'd0, 4'd10}: s1rd7 <= 10;
{1'd0, 4'd11}: s1rd7 <= 14;
{1'd0, 4'd12}: s1rd7 <= 3;
{1'd0, 4'd13}: s1rd7 <= 7;
{1'd0, 4'd14}: s1rd7 <= 11;
{1'd0, 4'd15}: s1rd7 <= 15;
endcase
end

{1'd0, 4'd0}: s1rd8 <= 3;
{1'd0, 4'd1}: s1rd8 <= 7;
{1'd0, 4'd2}: s1rd8 <= 11;
{1'd0, 4'd3}: s1rd8 <= 15;
{1'd0, 4'd4}: s1rd8 <= 2;
{1'd0, 4'd5}: s1rd8 <= 6;
{1'd0, 4'd6}: s1rd8 <= 10;
{1'd0, 4'd7}: s1rd8 <= 14;
{1'd0, 4'd8}: s1rd8 <= 1;
{1'd0, 4'd9}: s1rd8 <= 5;
{1'd0, 4'd10}: s1rd8 <= 9;
{1'd0, 4'd11}: s1rd8 <= 13;
{1'd0, 4'd12}: s1rd8 <= 0;
{1'd0, 4'd13}: s1rd8 <= 4;
{1'd0, 4'd14}: s1rd8 <= 8;
{1'd0, 4'd15}: s1rd8 <= 12;
endcase
end

{1'd0, 4'd0}: s1rd9 <= 2;
{1'd0, 4'd1}: s1rd9 <= 6;
{1'd0, 4'd2}: s1rd9 <= 10;
{1'd0, 4'd3}: s1rd9 <= 14;
{1'd0, 4'd4}: s1rd9 <= 3;
{1'd0, 4'd5}: s1rd9 <= 7;
{1'd0, 4'd6}: s1rd9 <= 11;
{1'd0, 4'd7}: s1rd9 <= 15;
{1'd0, 4'd8}: s1rd9 <= 0;
{1'd0, 4'd9}: s1rd9 <= 4;
{1'd0, 4'd10}: s1rd9 <= 8;
{1'd0, 4'd11}: s1rd9 <= 12;
{1'd0, 4'd12}: s1rd9 <= 1;
{1'd0, 4'd13}: s1rd9 <= 5;
{1'd0, 4'd14}: s1rd9 <= 9;
{1'd0, 4'd15}: s1rd9 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd10 <= 1;
{1'd0, 4'd1}: s1rd10 <= 5;
{1'd0, 4'd2}: s1rd10 <= 9;
{1'd0, 4'd3}: s1rd10 <= 13;
{1'd0, 4'd4}: s1rd10 <= 0;
{1'd0, 4'd5}: s1rd10 <= 4;
{1'd0, 4'd6}: s1rd10 <= 8;
{1'd0, 4'd7}: s1rd10 <= 12;
{1'd0, 4'd8}: s1rd10 <= 3;
{1'd0, 4'd9}: s1rd10 <= 7;
{1'd0, 4'd10}: s1rd10 <= 11;
{1'd0, 4'd11}: s1rd10 <= 15;
{1'd0, 4'd12}: s1rd10 <= 2;
{1'd0, 4'd13}: s1rd10 <= 6;
{1'd0, 4'd14}: s1rd10 <= 10;
{1'd0, 4'd15}: s1rd10 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd11 <= 0;
{1'd0, 4'd1}: s1rd11 <= 4;
{1'd0, 4'd2}: s1rd11 <= 8;
{1'd0, 4'd3}: s1rd11 <= 12;
{1'd0, 4'd4}: s1rd11 <= 1;
{1'd0, 4'd5}: s1rd11 <= 5;
{1'd0, 4'd6}: s1rd11 <= 9;
{1'd0, 4'd7}: s1rd11 <= 13;
{1'd0, 4'd8}: s1rd11 <= 2;
{1'd0, 4'd9}: s1rd11 <= 6;
{1'd0, 4'd10}: s1rd11 <= 10;
{1'd0, 4'd11}: s1rd11 <= 14;
{1'd0, 4'd12}: s1rd11 <= 3;
{1'd0, 4'd13}: s1rd11 <= 7;
{1'd0, 4'd14}: s1rd11 <= 11;
{1'd0, 4'd15}: s1rd11 <= 15;
endcase
end

{1'd0, 4'd0}: s1rd12 <= 3;
{1'd0, 4'd1}: s1rd12 <= 7;
{1'd0, 4'd2}: s1rd12 <= 11;
{1'd0, 4'd3}: s1rd12 <= 15;
{1'd0, 4'd4}: s1rd12 <= 2;
{1'd0, 4'd5}: s1rd12 <= 6;
{1'd0, 4'd6}: s1rd12 <= 10;
{1'd0, 4'd7}: s1rd12 <= 14;
{1'd0, 4'd8}: s1rd12 <= 1;
{1'd0, 4'd9}: s1rd12 <= 5;
{1'd0, 4'd10}: s1rd12 <= 9;
{1'd0, 4'd11}: s1rd12 <= 13;
{1'd0, 4'd12}: s1rd12 <= 0;
{1'd0, 4'd13}: s1rd12 <= 4;
{1'd0, 4'd14}: s1rd12 <= 8;
{1'd0, 4'd15}: s1rd12 <= 12;
endcase
end

{1'd0, 4'd0}: s1rd13 <= 2;
{1'd0, 4'd1}: s1rd13 <= 6;
{1'd0, 4'd2}: s1rd13 <= 10;
{1'd0, 4'd3}: s1rd13 <= 14;
{1'd0, 4'd4}: s1rd13 <= 3;
{1'd0, 4'd5}: s1rd13 <= 7;
{1'd0, 4'd6}: s1rd13 <= 11;
{1'd0, 4'd7}: s1rd13 <= 15;
{1'd0, 4'd8}: s1rd13 <= 0;
{1'd0, 4'd9}: s1rd13 <= 4;
{1'd0, 4'd10}: s1rd13 <= 8;
{1'd0, 4'd11}: s1rd13 <= 12;
{1'd0, 4'd12}: s1rd13 <= 1;
{1'd0, 4'd13}: s1rd13 <= 5;
{1'd0, 4'd14}: s1rd13 <= 9;
{1'd0, 4'd15}: s1rd13 <= 13;
endcase
end

{1'd0, 4'd0}: s1rd14 <= 1;
{1'd0, 4'd1}: s1rd14 <= 5;
{1'd0, 4'd2}: s1rd14 <= 9;
{1'd0, 4'd3}: s1rd14 <= 13;
{1'd0, 4'd4}: s1rd14 <= 0;
{1'd0, 4'd5}: s1rd14 <= 4;
{1'd0, 4'd6}: s1rd14 <= 8;
{1'd0, 4'd7}: s1rd14 <= 12;
{1'd0, 4'd8}: s1rd14 <= 3;
{1'd0, 4'd9}: s1rd14 <= 7;
{1'd0, 4'd10}: s1rd14 <= 11;
{1'd0, 4'd11}: s1rd14 <= 15;
{1'd0, 4'd12}: s1rd14 <= 2;
{1'd0, 4'd13}: s1rd14 <= 6;
{1'd0, 4'd14}: s1rd14 <= 10;
{1'd0, 4'd15}: s1rd14 <= 14;
endcase
end

{1'd0, 4'd0}: s1rd15 <= 0;
{1'd0, 4'd1}: s1rd15 <= 4;
{1'd0, 4'd2}: s1rd15 <= 8;
{1'd0, 4'd3}: s1rd15 <= 12;
{1'd0, 4'd4}: s1rd15 <= 1;
{1'd0, 4'd5}: s1rd15 <= 5;
{1'd0, 4'd6}: s1rd15 <= 9;
{1'd0, 4'd7}: s1rd15 <= 13;
{1'd0, 4'd8}: s1rd15 <= 2;
{1'd0, 4'd9}: s1rd15 <= 6;
{1'd0, 4'd10}: s1rd15 <= 10;
{1'd0, 4'd11}: s1rd15 <= 14;
{1'd0, 4'd12}: s1rd15 <= 3;
{1'd0, 4'd13}: s1rd15 <= 7;
{1'd0, 4'd14}: s1rd15 <= 11;
{1'd0, 4'd15}: s1rd15 <= 15;
endcase
end

swNet24140 sw(tm83_d, clk, muxCycle, t0, s0, t1, s1, t2, s2, t3, s3, t4, s4,
t5, s5, t6, s6, t7, s7, t8, s8, t9, s9, t10, s10, t11, s11, t12, s12, t13, s13,
t14, s14, t15, s15);

{1'd0, 4'd0}: s2wr0 <= 12;
{1'd0, 4'd1}: s2wr0 <= 13;
{1'd0, 4'd2}: s2wr0 <= 14;
{1'd0, 4'd3}: s2wr0 <= 15;
{1'd0, 4'd4}: s2wr0 <= 8;
{1'd0, 4'd5}: s2wr0 <= 9;
{1'd0, 4'd6}: s2wr0 <= 10;
{1'd0, 4'd7}: s2wr0 <= 11;
{1'd0, 4'd8}: s2wr0 <= 4;
{1'd0, 4'd9}: s2wr0 <= 5;
{1'd0, 4'd10}: s2wr0 <= 6;
{1'd0, 4'd11}: s2wr0 <= 7;
{1'd0, 4'd12}: s2wr0 <= 0;
{1'd0, 4'd13}: s2wr0 <= 1;
{1'd0, 4'd14}: s2wr0 <= 2;
{1'd0, 4'd15}: s2wr0 <= 3;

{1'd0, 4'd0}: s2wr1 <= 12;
{1'd0, 4'd1}: s2wr1 <= 13;
{1'd0, 4'd2}: s2wr1 <= 14;
{1'd0, 4'd3}: s2wr1 <= 15;
{1'd0, 4'd4}: s2wr1 <= 8;
{1'd0, 4'd5}: s2wr1 <= 9;
{1'd0, 4'd6}: s2wr1 <= 10;
{1'd0, 4'd7}: s2wr1 <= 11;
{1'd0, 4'd8}: s2wr1 <= 4;
{1'd0, 4'd9}: s2wr1 <= 5;
{1'd0, 4'd10}: s2wr1 <= 6;
{1'd0, 4'd11}: s2wr1 <= 7;
{1'd0, 4'd12}: s2wr1 <= 0;
{1'd0, 4'd13}: s2wr1 <= 1;
{1'd0, 4'd14}: s2wr1 <= 2;
{1'd0, 4'd15}: s2wr1 <= 3;

{1'd0, 4'd0}: s2wr2 <= 12;
{1'd0, 4'd1}: s2wr2 <= 13;
{1'd0, 4'd2}: s2wr2 <= 14;
{1'd0, 4'd3}: s2wr2 <= 15;
{1'd0, 4'd4}: s2wr2 <= 8;
{1'd0, 4'd5}: s2wr2 <= 9;
{1'd0, 4'd6}: s2wr2 <= 10;
{1'd0, 4'd7}: s2wr2 <= 11;
{1'd0, 4'd8}: s2wr2 <= 4;
{1'd0, 4'd9}: s2wr2 <= 5;
{1'd0, 4'd10}: s2wr2 <= 6;
{1'd0, 4'd11}: s2wr2 <= 7;
{1'd0, 4'd12}: s2wr2 <= 0;
{1'd0, 4'd13}: s2wr2 <= 1;
{1'd0, 4'd14}: s2wr2 <= 2;
{1'd0, 4'd15}: s2wr2 <= 3;

{1'd0, 4'd0}: s2wr3 <= 12;
{1'd0, 4'd1}: s2wr3 <= 13;
{1'd0, 4'd2}: s2wr3 <= 14;
{1'd0, 4'd3}: s2wr3 <= 15;
{1'd0, 4'd4}: s2wr3 <= 8;
{1'd0, 4'd5}: s2wr3 <= 9;
{1'd0, 4'd6}: s2wr3 <= 10;
{1'd0, 4'd7}: s2wr3 <= 11;
{1'd0, 4'd8}: s2wr3 <= 4;
{1'd0, 4'd9}: s2wr3 <= 5;
{1'd0, 4'd10}: s2wr3 <= 6;
{1'd0, 4'd11}: s2wr3 <= 7;
{1'd0, 4'd12}: s2wr3 <= 0;
{1'd0, 4'd13}: s2wr3 <= 1;
{1'd0, 4'd14}: s2wr3 <= 2;
{1'd0, 4'd15}: s2wr3 <= 3;

{1'd0, 4'd0}: s2wr4 <= 8;
{1'd0, 4'd1}: s2wr4 <= 9;
{1'd0, 4'd2}: s2wr4 <= 10;
{1'd0, 4'd3}: s2wr4 <= 11;
{1'd0, 4'd4}: s2wr4 <= 12;
{1'd0, 4'd5}: s2wr4 <= 13;
{1'd0, 4'd6}: s2wr4 <= 14;
{1'd0, 4'd7}: s2wr4 <= 15;
{1'd0, 4'd8}: s2wr4 <= 0;
{1'd0, 4'd9}: s2wr4 <= 1;
{1'd0, 4'd10}: s2wr4 <= 2;
{1'd0, 4'd11}: s2wr4 <= 3;
{1'd0, 4'd12}: s2wr4 <= 4;
{1'd0, 4'd13}: s2wr4 <= 5;
{1'd0, 4'd14}: s2wr4 <= 6;
{1'd0, 4'd15}: s2wr4 <= 7;

{1'd0, 4'd0}: s2wr5 <= 8;
{1'd0, 4'd1}: s2wr5 <= 9;
{1'd0, 4'd2}: s2wr5 <= 10;
{1'd0, 4'd3}: s2wr5 <= 11;
{1'd0, 4'd4}: s2wr5 <= 12;
{1'd0, 4'd5}: s2wr5 <= 13;
{1'd0, 4'd6}: s2wr5 <= 14;
{1'd0, 4'd7}: s2wr5 <= 15;
{1'd0, 4'd8}: s2wr5 <= 0;
{1'd0, 4'd9}: s2wr5 <= 1;
{1'd0, 4'd10}: s2wr5 <= 2;
{1'd0, 4'd11}: s2wr5 <= 3;
{1'd0, 4'd12}: s2wr5 <= 4;
{1'd0, 4'd13}: s2wr5 <= 5;
{1'd0, 4'd14}: s2wr5 <= 6;
{1'd0, 4'd15}: s2wr5 <= 7;

{1'd0, 4'd0}: s2wr6 <= 8;
{1'd0, 4'd1}: s2wr6 <= 9;
{1'd0, 4'd2}: s2wr6 <= 10;
{1'd0, 4'd3}: s2wr6 <= 11;
{1'd0, 4'd4}: s2wr6 <= 12;
{1'd0, 4'd5}: s2wr6 <= 13;
{1'd0, 4'd6}: s2wr6 <= 14;
{1'd0, 4'd7}: s2wr6 <= 15;
{1'd0, 4'd8}: s2wr6 <= 0;
{1'd0, 4'd9}: s2wr6 <= 1;
{1'd0, 4'd10}: s2wr6 <= 2;
{1'd0, 4'd11}: s2wr6 <= 3;
{1'd0, 4'd12}: s2wr6 <= 4;
{1'd0, 4'd13}: s2wr6 <= 5;
{1'd0, 4'd14}: s2wr6 <= 6;
{1'd0, 4'd15}: s2wr6 <= 7;

{1'd0, 4'd0}: s2wr7 <= 8;
{1'd0, 4'd1}: s2wr7 <= 9;
{1'd0, 4'd2}: s2wr7 <= 10;
{1'd0, 4'd3}: s2wr7 <= 11;
{1'd0, 4'd4}: s2wr7 <= 12;
{1'd0, 4'd5}: s2wr7 <= 13;
{1'd0, 4'd6}: s2wr7 <= 14;
{1'd0, 4'd7}: s2wr7 <= 15;
{1'd0, 4'd8}: s2wr7 <= 0;
{1'd0, 4'd9}: s2wr7 <= 1;
{1'd0, 4'd10}: s2wr7 <= 2;
{1'd0, 4'd11}: s2wr7 <= 3;
{1'd0, 4'd12}: s2wr7 <= 4;
{1'd0, 4'd13}: s2wr7 <= 5;
{1'd0, 4'd14}: s2wr7 <= 6;
{1'd0, 4'd15}: s2wr7 <= 7;

{1'd0, 4'd0}: s2wr8 <= 4;
{1'd0, 4'd1}: s2wr8 <= 5;
{1'd0, 4'd2}: s2wr8 <= 6;
{1'd0, 4'd3}: s2wr8 <= 7;
{1'd0, 4'd4}: s2wr8 <= 0;
{1'd0, 4'd5}: s2wr8 <= 1;
{1'd0, 4'd6}: s2wr8 <= 2;
{1'd0, 4'd7}: s2wr8 <= 3;
{1'd0, 4'd8}: s2wr8 <= 12;
{1'd0, 4'd9}: s2wr8 <= 13;
{1'd0, 4'd10}: s2wr8 <= 14;
{1'd0, 4'd11}: s2wr8 <= 15;
{1'd0, 4'd12}: s2wr8 <= 8;
{1'd0, 4'd13}: s2wr8 <= 9;
{1'd0, 4'd14}: s2wr8 <= 10;
{1'd0, 4'd15}: s2wr8 <= 11;

{1'd0, 4'd0}: s2wr9 <= 4;
{1'd0, 4'd1}: s2wr9 <= 5;
{1'd0, 4'd2}: s2wr9 <= 6;
{1'd0, 4'd3}: s2wr9 <= 7;
{1'd0, 4'd4}: s2wr9 <= 0;
{1'd0, 4'd5}: s2wr9 <= 1;
{1'd0, 4'd6}: s2wr9 <= 2;
{1'd0, 4'd7}: s2wr9 <= 3;
{1'd0, 4'd8}: s2wr9 <= 12;
{1'd0, 4'd9}: s2wr9 <= 13;
{1'd0, 4'd10}: s2wr9 <= 14;
{1'd0, 4'd11}: s2wr9 <= 15;
{1'd0, 4'd12}: s2wr9 <= 8;
{1'd0, 4'd13}: s2wr9 <= 9;
{1'd0, 4'd14}: s2wr9 <= 10;
{1'd0, 4'd15}: s2wr9 <= 11;

{1'd0, 4'd0}: s2wr10 <= 4;
{1'd0, 4'd1}: s2wr10 <= 5;
{1'd0, 4'd2}: s2wr10 <= 6;
{1'd0, 4'd3}: s2wr10 <= 7;
{1'd0, 4'd4}: s2wr10 <= 0;
{1'd0, 4'd5}: s2wr10 <= 1;
{1'd0, 4'd6}: s2wr10 <= 2;
{1'd0, 4'd7}: s2wr10 <= 3;
{1'd0, 4'd8}: s2wr10 <= 12;
{1'd0, 4'd9}: s2wr10 <= 13;
{1'd0, 4'd10}: s2wr10 <= 14;
{1'd0, 4'd11}: s2wr10 <= 15;
{1'd0, 4'd12}: s2wr10 <= 8;
{1'd0, 4'd13}: s2wr10 <= 9;
{1'd0, 4'd14}: s2wr10 <= 10;
{1'd0, 4'd15}: s2wr10 <= 11;

{1'd0, 4'd0}: s2wr11 <= 4;
{1'd0, 4'd1}: s2wr11 <= 5;
{1'd0, 4'd2}: s2wr11 <= 6;
{1'd0, 4'd3}: s2wr11 <= 7;
{1'd0, 4'd4}: s2wr11 <= 0;
{1'd0, 4'd5}: s2wr11 <= 1;
{1'd0, 4'd6}: s2wr11 <= 2;
{1'd0, 4'd7}: s2wr11 <= 3;
{1'd0, 4'd8}: s2wr11 <= 12;
{1'd0, 4'd9}: s2wr11 <= 13;
{1'd0, 4'd10}: s2wr11 <= 14;
{1'd0, 4'd11}: s2wr11 <= 15;
{1'd0, 4'd12}: s2wr11 <= 8;
{1'd0, 4'd13}: s2wr11 <= 9;
{1'd0, 4'd14}: s2wr11 <= 10;
{1'd0, 4'd15}: s2wr11 <= 11;

{1'd0, 4'd0}: s2wr12 <= 0;
{1'd0, 4'd1}: s2wr12 <= 1;
{1'd0, 4'd2}: s2wr12 <= 2;
{1'd0, 4'd3}: s2wr12 <= 3;
{1'd0, 4'd4}: s2wr12 <= 4;
{1'd0, 4'd5}: s2wr12 <= 5;
{1'd0, 4'd6}: s2wr12 <= 6;
{1'd0, 4'd7}: s2wr12 <= 7;
{1'd0, 4'd8}: s2wr12 <= 8;
{1'd0, 4'd9}: s2wr12 <= 9;
{1'd0, 4'd10}: s2wr12 <= 10;
{1'd0, 4'd11}: s2wr12 <= 11;
{1'd0, 4'd12}: s2wr12 <= 12;
{1'd0, 4'd13}: s2wr12 <= 13;
{1'd0, 4'd14}: s2wr12 <= 14;
{1'd0, 4'd15}: s2wr12 <= 15;

{1'd0, 4'd0}: s2wr13 <= 0;
{1'd0, 4'd1}: s2wr13 <= 1;
{1'd0, 4'd2}: s2wr13 <= 2;
{1'd0, 4'd3}: s2wr13 <= 3;
{1'd0, 4'd4}: s2wr13 <= 4;
{1'd0, 4'd5}: s2wr13 <= 5;
{1'd0, 4'd6}: s2wr13 <= 6;
{1'd0, 4'd7}: s2wr13 <= 7;
{1'd0, 4'd8}: s2wr13 <= 8;
{1'd0, 4'd9}: s2wr13 <= 9;
{1'd0, 4'd10}: s2wr13 <= 10;
{1'd0, 4'd11}: s2wr13 <= 11;
{1'd0, 4'd12}: s2wr13 <= 12;
{1'd0, 4'd13}: s2wr13 <= 13;
{1'd0, 4'd14}: s2wr13 <= 14;
{1'd0, 4'd15}: s2wr13 <= 15;

{1'd0, 4'd0}: s2wr14 <= 0;
{1'd0, 4'd1}: s2wr14 <= 1;
{1'd0, 4'd2}: s2wr14 <= 2;
{1'd0, 4'd3}: s2wr14 <= 3;
{1'd0, 4'd4}: s2wr14 <= 4;
{1'd0, 4'd5}: s2wr14 <= 5;
{1'd0, 4'd6}: s2wr14 <= 6;
{1'd0, 4'd7}: s2wr14 <= 7;
{1'd0, 4'd8}: s2wr14 <= 8;
{1'd0, 4'd9}: s2wr14 <= 9;
{1'd0, 4'd10}: s2wr14 <= 10;
{1'd0, 4'd11}: s2wr14 <= 11;
{1'd0, 4'd12}: s2wr14 <= 12;
{1'd0, 4'd13}: s2wr14 <= 13;
{1'd0, 4'd14}: s2wr14 <= 14;
{1'd0, 4'd15}: s2wr14 <= 15;

{1'd0, 4'd0}: s2wr15 <= 0;
{1'd0, 4'd1}: s2wr15 <= 1;
{1'd0, 4'd2}: s2wr15 <= 2;
{1'd0, 4'd3}: s2wr15 <= 3;
{1'd0, 4'd4}: s2wr15 <= 4;
{1'd0, 4'd5}: s2wr15 <= 5;
{1'd0, 4'd6}: s2wr15 <= 6;
{1'd0, 4'd7}: s2wr15 <= 7;
{1'd0, 4'd8}: s2wr15 <= 8;
{1'd0, 4'd9}: s2wr15 <= 9;
{1'd0, 4'd10}: s2wr15 <= 10;
{1'd0, 4'd11}: s2wr15 <= 11;
{1'd0, 4'd12}: s2wr15 <= 12;
{1'd0, 4'd13}: s2wr15 <= 13;
{1'd0, 4'd14}: s2wr15 <= 14;
{1'd0, 4'd15}: s2wr15 <= 15;

endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;

output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];

wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-

1];
assign q_unsc =
res[WIDTH-1:0];
assign q_sc =
{res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};

q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;

input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;

res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;

input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;

res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule

FFT Verilog

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FFT Verilog

Uploaded by

Copyright:

Available Formats

/*

* This source file contains a Verilog description of an IP core

// Input/output stream: 16 complex words per cycle

// Generated on Tue Apr 03 08:08:38 EDT 2018

// Latency: 165 clock cycles

// We use an interleaved complex data format. X0 represents the

// The design uses a system of flag signals to indicate the

// This system has a 'gap' of 16 cycles. This means that

// The output signal 'next_out' (also asserted high) indicates

// The system has a latency of 165 cycles. This means that

always #10000 clk = ~clk;

// Instantiate top-level module of core 'X' signals are system inputs

// On the next cycle, begin loading input vector.

// On the next cycle, we will start the next data vector

// Start entering next input vector

for (m=0; m < 15; m=m+1) begin

for (m=0; m < 15; m=m+1) begin

input [7:0] X0,

output [7:0] Y0,

wire [7:0] t0_0;

input [7:0] X0,

output [7:0] Y0,

wire [15:0] t0;

perm17610 instPerm27493(.x0(t0), .y0(s0),

module swNet17610(itr, clk, ct

input [3:0] ct;

reg [31:0] control;

always @(posedge clk) begin

// synthesis attribute rom_style of control is "distributed"

parameter depth = 16;

input [width-1:0] x0;

reg [addrbits-1:0] s1wr0;

wire [0:0] tm0;

memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0},

nextReg #(15, 4) nextReg_27510(.X(next), .Y(next2), .reset(reset), .clk(clk));

wire [addrbits-1:0] muxCycle, writeCycle;

wire readInt, s2wr_en;

shiftRegFIFO #(7, 1) writeIntReg(readInt, s2wr_en, clk);

memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0},

always @(posedge clk) begin

always @(posedge clk) begin

// synthesis attribute rom_style of s1rd0 is "block"

// synthesis attribute rom_style of s1rd1 is "block"

// synthesis attribute rom_style of s1rd2 is "block"

// synthesis attribute rom_style of s1rd3 is "block"

// synthesis attribute rom_style of s1rd4 is "block"

// synthesis attribute rom_style of s1rd5 is "block"

// synthesis attribute rom_style of s1rd6 is "block"

// synthesis attribute rom_style of s1rd7 is "block"

// synthesis attribute rom_style of s1rd8 is "block"

// synthesis attribute rom_style of s1rd9 is "block"

// synthesis attribute rom_style of s1rd10 is "block"

// synthesis attribute rom_style of s1rd11 is "block"

// synthesis attribute rom_style of s1rd12 is "block"

// synthesis attribute rom_style of s1rd13 is "block"

// synthesis attribute rom_style of s1rd14 is "block"

// synthesis attribute rom_style of s1rd15 is "block"

always @(posedge clk) begin

// synthesis attribute rom_style of s2wr0 is "block"

// synthesis attribute rom_style of s2wr1 is "block"

// synthesis attribute rom_style of s2wr2 is "block"

// synthesis attribute rom_style of s2wr3 is "block"

// synthesis attribute rom_style of s2wr4 is "block"