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Phase Shift
PWM PWM
VOUT1 Controller Controller VOUT2
1 2
APW7159A
APW7159A
APW7159A K: XXXXX XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
FB1 1 20 RT
COMP1 2 19 SS
OCSET1 3 18 FB2
GND 4 17 COMP2
VCC 5 16 OCSET2
BOOT1 6 15 BOOT2
UGATE1 7 14 UGATE2
PHASE1 8 13 PHASE2
LGATE1 9 12 LGATE2
PGND 10 11 NC
SOP-20
(Top View)
Thermal Characteristics
Symbol Parameter Typical Value Unit
Junction-to-Ambient Thermal Resistance in Free Air (Note 2)
θJA 100 °C/W
SOP-20
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V, VOUT= 3.3V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
APW7159A
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
VCC Supply Current (Shutdown
VVCC<5V, SS=GND - 0.5 1 mA
Mode)
VCC Supply Current (Shutdown
5V< VVCC <9V, SS=GND - 0.8 1.6 mA
Mode)
UGATE1/UGATE2 and
IVCC VCC Supply Current - 5 10 mA
LGATE1/LGATE2 open
POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS
Rising VCC Threshold 9 9.5 10 V
Falling VCC Threshold 1 7.5 8 8.5 V
Falling VCC Threshold 2 - 4.6 - V
Rising VOCSET1/VOCSET2 Threshold - 1.6 - V
Falling VOCSET1/VOCSET2 Threshold - 1.0 - V
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
VIN1= VIN2=Vvcc
1 1 VOUT1
VOUT2
VOUT1
2 2
VOUT2
3 3
Enable Shutdown
VOUT1
VOUT1
2 2
VOUT2
VOUT2
3 3
VIN=V VCC
1 1
VOUT
VOUT
2 2
VPHASE
3 3
VPHASE
IL
4 4
IL
VUGATE
1,2 1,2
VPHASE
VPHASE
3 3
VOUT2 VOUT1
1 1
IOUT2 I OUT1
2 2
Pin Description
PIN
FUNCTION
NO. NAME
Feedback Input of Channel 1. The Buck converter senses feedback voltage via FB1 and regulates the
1 FB1 FB1 voltage at 1.0V. Connecting FB1 with a resistor-divider from the output sets the output voltage of
the Buck converter.
Error Amplifier Output of Channel 1. It is used to compensate the regulation control loop. Refer to the
2 COMP1
section “Application Information” for details.
This pin is used to set the maximum inductor current of channel 1. Refer to the section in “Function
3 OCSET1
Description” for detail.
4 GND Signal Ground.
Power Supply Input. Connect a nominal 10V to 13.2V power supply voltage to this pin. A
5 VCC power-on-reset function monitors the input voltage at this pin. It is recommended that a decoupling
capacitor (1 to 10µF) should be connected to the GND for noise decoupling.
This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET.
6 BOOT1 An external capacitor from PHASE1 to BOOT1, an internal diode, and the power supply voltage VCC,
generate the bootstrap voltage for the high-side gate driver (UGATE1).
7 UGATE1 High-Side Gate Driver Output of Channel 1. This pin is the gate driver for high-side MOSFET.
This pin is the return path for the high-side gate driver 1. Connect this pin to the high-side MOSFET
8 PHASE1 source and connect a capacitor to BOOT1 for the bootstrap voltage. This pin is also used to monitor
the voltage drop across the MOSFET for over-current protection.
Block Diagram
VCC
Regulator
Power-On-
Reset I SS
(30µA typ.)
V REF
SS
(1.0V typ.)
OCSET2 OCSET1
I OCSET2 I OCSET1
BOOT2 BOOT1
Gate Gate
LGATE2 Control Control LGATE1
15k 15k
PGND2 Over-Voltage Over-Voltage PGND1
Comparator Comparator
2 1
1.2 1.2
Under-Voltage Under-Voltage
Comparator Comparator
2 1
0.5 0.5
FB2 FB1
Error Error
VREF PWM PWM
Amplifier Amplifier V REF
Comparator Comparator
2 1
2 1
COMP2 COMP1
Oscillator
RT GND
2k 2k VIN
OCSET1 OCSET2
10µF 1µF 1µF 10µF
470µF
1nF BOOT1 BOOT2 1nF
(option) (option)
100nF 100nF
UGATE1 UGATE2
VOUT1 L1 APM3109 APM3109 VOUT2
7.2µH L2
5V/30A PHASE1 PHASE2 7.2µH 3.3V/30A
(option)
(option) APM3106 APM3106
2200µFx2 LGATE1 LGATE2 2200µFx2
4R7 4R7 ESR=30mΩ
ESR=30mΩ
COMP1 COMP2
15nF 33nF 33nF 15nF
12k 12k
6.8nF APW7159 6.8nF
1k 12k 12k 1k
FB1 FB2
VVCC 5R1
3k VCC RT 5.2k
1µF
GND SS
RT
47nF
Function Description
VCC Power-On-Reset (POR)
VSS
Voltage
The Power-On-Reset (POR) function of APW7159A con-
tinually monitors the voltage on VCC and OCSET1/
OCSET2 pin. When the voltage on VCC and OCSET1/
OCSET2 exceeds their rising POR threshold voltage re- 1.4
spectively (9.5V and 1.6V typical), the POR function ini- VFB
tiates soft-start operation. Where the voltage at OCSET1/ 1 1
FOSC (kHz ) = 50 +
Under-Voltage Protection 7550
R T (kΩ )
The under-voltage function monitors the voltage on FB by
Under-Voltage comparator to protect the PWM converter
against short-circuit conditions. When the VFB falls below
the falling UVP threshold (50% VREF), a fault signal is in-
ternally generated and the device turns off high-side
and low-side MOSFETs. The converter is shutdown and
the output is latched to be floating.
600
Oscillator Frequency (kHz)
500
400
300
200
100
0
0 100 200 300 400 500 600
RT Resistance (k)
Application Information
Output Voltage Selection Output Capacitor Selection
The output voltage can be programmed with a resistive Higher capacitor value and lower ESR reduce the output
divider. Use 1% or better resistors for the resistive divider ripple and the load transient drop. Therefore, selecting high
is recommended. The FB pin is the inverter input of the performance low ESR capacitors is intended for switch-
error amplifier, and the reference voltage is 1V. The out- ing regulator applications. In some applications, mul-
put voltage is determined by: tiple capacitors have to be parallelled to achieve the
desired ESR value. A small decoupling capacitor in
R
VOUT = 1× 1 + OUT
parallel for bypassing the noise is also recommended,
R GND
and the voltage rating of the output capacitors also must
Where ROUT is the resistor connected from VOUT to FB and be considered. If tantalum capacitors are used, make
RGND is the resistor connected from FB to the GND. sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Output Inductor Selection
Input Capacitor Selection
The inductor value determines the inductor ripple current
The input capacitor is chosen based on the voltage rating
and affects the load transient response. Higher inductor
and the RMS current rating. For reliable operation, select
value reduces the inductor’s ripple current and induces
the capacitor voltage rating to be at least 1.3 times higher
lower output ripple voltage. The ripple current and ripple
than the maximum input voltage. The RMS current of the
voltage can be approximated by:
bulk input capacitor is calculated as the following equation:
VIN − VOUT VOUT
IRIPPLE = ×
FS × L VIN IRMS = IOUT ⋅ D ⋅ (1 − D )
∆VOUT = IRIPPLE × ESR During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors are
where Fs is the switching frequency of the regulator.
used, make sure they are surge tested by the
Although increase of the inductor value and frequency manufactures. If in doubt, consult the capacitors
reduces the ripple current and voltage, a tradeoff will manufacturer. For high frequency decoupling, a ceramic
exist between the inductor’s ripple current and the capacitor 1µF can be connected between the drain of
regulator load transient response time. upper MOSFET and the source of lower MOSFET.
A smaller inductor will give the regulator a faster load MOSFET Selection
transient response at the expense of higher ripple current.
The selection of the N-channel power MOSFETs are
Increasing the switching frequency (FS) also reduces the
determined by the RDS(ON), reverse transfer capacitance
ripple current and voltage, but it will increase the
(CRSS) and maximum output current requirement. There
switching loss of the MOSFET and the power dissipation
are two components of loss in the MOSFETs: conduction
of the converter. The maximum ripple current occurs at
loss and transition loss. For the upper and lower
the maximum input voltage. A good starting point is to
MOSFET, the losses are approximately given by the fol-
choose the ripple current to be approximately 30% of
lowing equations:
the maximum output current. Once the inductance value
2
has been chosen, select an inductor is capable of carry- PUPPER = IOUT ( 1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS
ing the required peak current without going into 2
PLOWER = IOUT (1+ TC)(RDS(ON))(1-D)
saturation. In some types of inductors, especially core
Where IOUT is the load current
that is made of ferrite, the ripple current will increase
TC is the temperature dependency of RDS(ON)
abruptly when it saturates. This will result in a larger out-
FS is the switching frequency
put ripple voltage.
tSW is the switching interval
D is the duty cycle
1
FESR FP2 =
2 × π × R3 × C3
C1
-20dB/dec
R3 C3 R2 C2
V OUT
R1 FB V COMP
Frequency(Hz)
V REF
Figure 4. The LC Filter GAIN and Frequency Figure 6. Compensation Network
4. Set the pole at the ESR zero frequency FESR: Figure 7. Converter Gain and Frequency
FP1 = FESR
Layout Consideration
Calculate the C1 by the equation:
In any high switching frequency converter, a correct lay-
C2
C1 = out is important to ensure proper operation of the
2 × π × R2 × C2 × FESR − 1
regulator. With power devices switching at 200kHz, the
5. Set the second pole FP2 at the half of the switching resulting current transient will cause voltage spike across
frequency and also set the second zero FZ2 at the output LC the interconnecting impedance and parasitic circuit
filter double pole FLC. The compensation gain should not elements. As an example, consider the turn-off transition
exceed the error amplifier open loop gain, check the of the PWM MOSFET. Before turn-off, the MOSFET is car-
compensation gain at FP2 with the capabilities of the error rying the full load current. During turn-off, current stops
amplifier. flowing in the MOSFET and is free-wheeling by the lower
FP2 = 0.5 X FS MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
FZ2 = FLC
switching interval. In general, using short and wide printed
Combine the two equations will get the following component circuit traces should minimize interconnecting imped-
calculations: ances and the magnitude of voltage spike. And signal
1 + s × ESR × COUT
GAINLC = and power grounds are to be kept separating till com-
s × L × COUT + s × ESR × COUT + 1
2
bined using the ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
Package Information
SOP-20
SEE VIEW A
E1
E
h X 45o c
e b
0.25
A2
A
GAUGE PLANE
SEATING PLANE
L
0
A1
VIEW A
S SOP-20
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 2.65 0.104
A2 2.05 0.081
b 0.31 0.51 0.012 0.020
c 0.20 0.33 0.008 0.013
D 12.60 13.00 0.496 0.512
0 0o 8o 0o 8o
OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 OD1 B A
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
24.40+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10
-0.00 -0.20
SOP-20 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 12.0±0.10 2.0±0.10 1.5 MIN. 10.9±0.20 13.3±0.20 3.1±0.20
-0.00 -0.40
(mm)
Classification Profile
Customer Service
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838