Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator

Version 7.2.0.442.isr15 32bit -- 13 Dec 2010

Copyright (C) 1989-2010 Cadence Design Systems, Inc. All rights reserved worldwide.
Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems,
Inc. All others are the property of their respective holders.

Protected by U.S. Patents:

5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238;
6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964;
6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839;
6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782;
7,085,700; 7,143,021; 7,493,240; 7,571,401.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA

Security, Inc.

User: pkamat Host: vlsi29.ee.iitb.ac.in HostID: 7F0100 PID: 17296

Memory available: 1.7524 GB physical: 8.2824 GB
CPU Type: Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz
Processor PhysicalID CoreID Frequency
0 0 0 3301.0
1 0 1 1600.0
2 0 2 3301.0
3 0 3 1600.0

Simulating `input.scs' on vlsi29.ee.iitb.ac.in at 9:48:18 PM, Thur Sep 26, 2013

(process id: 17296).
Environment variable:
SPECTRE_DEFAULTS=-I.
Command line:
/cad/cadence/MMSIM72/tools.lnx86/spectre/bin/32bit/spectre -env \
artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre0_16378_10 -format sst2 -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5 input.scs
spectre pid = 17296

Loading /cad/cadence/MMSIM72/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...

Loading /cad/cadence/MMSIM72/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /cad/cadence/MMSIM72/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /cad/cadence/MMSIM72/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Auto-loading AHDL component.
Finished loading AHDL component in 0 s (elapsed).
Installed AHDL simulation interface.
Time for NDB Parsing: CPU = 50.991 ms, elapsed = 154.375 ms.
Time accumulated: CPU = 50.991 ms, elapsed = 154.375 ms.
Peak resident memory used = 24.7 Mbytes.

Time for Elaboration: CPU = 46.993 ms, elapsed = 59.7332 ms.

Time accumulated: CPU = 97.984 ms, elapsed = 214.196 ms.
Peak resident memory used = 32.1 Mbytes.

Time for EDB Visiting: CPU = 2 ms, elapsed = 2.75087 ms.

Time accumulated: CPU = 99.984 ms, elapsed = 217.081 ms.
Peak resident memory used = 32.4 Mbytes.

Circuit inventory:
 nodes 135
bert_2 9
capacitor 9
clk_3 9
dfe_model_veriloga_1 9
inductor 9
resistor 63
rn_1 9
vcvs 54
vsource 27

Time for parsing: CPU = 1 ms, elapsed = 11.0888 ms.

Time accumulated: CPU = 100.984 ms, elapsed = 228.25 ms.
Peak resident memory used = 32.9 Mbytes.

Entering remote command mode using MPSC service (spectre, ipi, v0.0,
spectre0_16378_10, ).

************************************************
Transient Analysis `tran': time = (0 s -> 50 ns)
************************************************
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 50 ns
step = 50 ps
maxstep = 500 ps
ic = all
skipdc = no
reltol = 100e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

tran: time = 1.25 ns (2.5 %), step = 145.1 fs (290 u%)

tran: time = 3.75 ns (7.5 %), step = 182.4 fs (365 u%)
tran: time = 6.25 ns (12.5 %), step = 197.5 fs (395 u%)
tran: time = 8.75 ns (17.5 %), step = 47.77 fs (95.5 u%)
tran: time = 11.25 ns (22.5 %), step = 640.5 fs (1.28 m%)
tran: time = 13.75 ns (27.5 %), step = 447.9 fs (896 u%)
tran: time = 16.25 ns (32.5 %), step = 665.4 fs (1.33 m%)
tran: time = 18.75 ns (37.5 %), step = 401 fs (802 u%)
tran: time = 21.25 ns (42.5 %), step = 46.71 fs (93.4 u%)
tran: time = 23.75 ns (47.5 %), step = 542.2 fs (1.08 m%)
tran: time = 26.25 ns (52.5 %), step = 134.5 fs (269 u%)
tran: time = 28.75 ns (57.5 %), step = 692.6 fs (1.39 m%)
tran: time = 31.25 ns (62.5 %), step = 192.8 fs (386 u%)
tran: time = 33.75 ns (67.5 %), step = 349.8 fs (700 u%)
tran: time = 36.25 ns (72.5 %), step = 454.5 fs (909 u%)
tran: time = 38.75 ns (77.5 %), step = 195.4 fs (391 u%)
tran: time = 41.25 ns (82.5 %), step = 32.68 fs (65.4 u%)
 tran: time = 43.75 ns (87.5 %), step = 319.9 fs (640 u%)
tran: time = 46.25 ns (92.5 %), step = 28.99 fs (58 u%)
tran: time = 48.75 ns (97.5 %), step = 148.1 fs (296 u%)
bit error rate = 4.308617 %% 1000 43 60.000000
bit error rate = 8.817635 %% 1000 88 80.000000
bit error rate = 21.342685 %% 1000 213 0.000000
bit error rate = 4.709419 %% 1000 47 20.000000
bit error rate = 12.424850 %% 1000 124 120.000000
bit error rate = 15.531062 %% 1000 155 100.000000
bit error rate = 24.849699 %% 1000 248 140.000000
bit error rate = 32.164329 %% 1000 321 160.000000
bit error rate = 4.208417 %% 1000 42 40.000000
bit error rate = 0.049951%%
bit error rate = -0.031274%%
bit error rate = -0.018823%%
bit error rate = -0.026440%%
bit error rate = 0.050244%%
bit error rate = -0.031567%%
bit error rate = -0.029590%%
bit error rate = 0.070972%%
bit error rate = -0.003882%%
Number of accepted tran steps = 507981
Initial condition solution time: CPU = 999 us, elapsed = 1.019 ms.
Intrinsic tran analysis time: CPU = 142.116 s, elapsed = 204.956 s.
Total time required for tran analysis `tran': CPU = 142.118 s (2m 22.1s), elapsed
= 204.975 s (3m 25.0s).
Time accumulated: CPU = 142.222 s (2m 22.2s), elapsed = 206.499 s (3m 26.5s).
Peak resident memory used = 37.5 Mbytes.

finalTimeOP: writing operating point information to rawfile.

modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.