INSTRUCTION SET PIN FUNCTIONS

ADuC812

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Arithmetic Operations 1 P1.0 / ADC0 / T2

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ADD A,source 1,2 12 Rn register addressing using R0-R7 2 P1.1 / ADC1 / T2EX
add source to A
ADD A,#data 2 12 direct 8bit internal address (00h-FFh) 3 P1.2 / ADC2
@Ri indirect addressing using R0 or R1 1 pin 1 identifier 39
ADDC A,source 1,2 12 4 P1.3 / ADC3 2 38
add with carry source any of [Rn, direct, @Ri] 3 37
ADDC A,#data 2 12 5 AVDD

G3697-5-10/99
MicroConverter®
4 36
dest any of [Rn, direct, @Ri] 5 ADuC812 35
SUBB A,source subtract from A 1,2 12 6 AGND 6 34
with borrow #data 8bit constant included in instruction 7
52pin PQFP 33
SUBB A,#data 2 12 7 CREF
INC A 1 12
#data16 16bit constant included in instruction
bit 8bit direct address of bit 8 VREF
8
9
10
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TOP VIEW
(not to scale)
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Quick Reference Guide
INC source increment 1,2 12 rel signed 8bit offset 9 DAC0 12 28
13 27
INC DPTR * 1 24 addr11 11bit address in current 2K page 10 DAC1
DEC A 1 12 addr16 16bit address 11 P1.4 / ADC4
decrement

14
15
16
17
18
19
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22
23
24
25
26
DEC source 1,2 12 * INC DPTR increments the 24bit value DPP/DPH/DPL 12 P1.5 / ADC5 / SS
MUL AB multiply A by B 1 48 13 P1.6 / ADC6 a “Data Acquisition System on a Chip”

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Logical Operations

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DIV AB divide A by B 1 48
ANL A,source 1,2 12
DA A decimal adjust 1 12 14 P1.7 / ADC7 27 SDATA / MOSI 40 EA
ANL A,#data 2 12
logical AND 15 RESET 28 P2.0 / A8 / A16 41 PSEN
d s

the ADuC812 is: ADC:

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rio
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12bit, 5µs, 8channel, self calibrating

te

Data Transfer Operations ANL direct,A 2 12

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16 P3.0 / RxD 29 P2.1 / A9 / A17 42 ALE

MOV A,source 1,2 12 ANL direct,#data 3 24 0.5LSB INL & 70dB SNR
17 P3.1 / TxD 30 P2.2 / A10 / A18 43 P0.0 / AD0
MOV A,#data 2 12 ORL A,source 1,2 12
MOV dest,A move source 1,2 12 ORL A,#data 2 12
18 P3.2 / INT0 31 P2.3 / A11 / A19 44 P0.1 / AD1 DAC: dual, 12bit, 15µs, voltage output
to destination logical OR 19 P3.3 / INT1 / MISO 32 XTAL1 (in) 45 P0.2 / AD2 1LSB DNL
MOV dest,source 1,2,3 24 ORL direct,A 2 12
20 DVDD 33 XTAL2 (out) 46 P0.3 / AD3
MOV dest,#data 2,3 12,24 ORL direct,#data 3 24
21 DGND 34 DVDD 47 DGND
Flash/EEPROM: 8K bytes Flash/EE program memory
MOV DPTR,#data16 3 24 XRL A,source 1,2 12 640 bytes Flash/EE data memory
22 P3.4 / T0 35 DGND 48 DVDD
MOVC A,@A+DPTR move from 1 24 XRL A,#data 2 12
MOVC A,@A+PC
code memory
1 24 XRL direct,A
logical XOR
2 12
23 P3.5 / T1 / CONVST 36 P2.4 / A12 / A20 49 P0.4 / AD4 microcontroller: industry standard 8052
24 P3.6 / WR 37 P2.5 / A13 / A21 50 P0.5 / AD5 DC to 16MHz, up to 1.3MIPS, 32 I/O lines
MOVX A,@Ri 1 24 XRL direct,#data 3 24
25 P3.7 / RD 38 P2.6 / A14 / A22 51 P0.6 / AD6
MOVX A,@DPTR move to/from 1 24 CLR A clear A to zero 1 12
data memory 26 SCLOCK 39 P2.7 / A15 / A23 52 P0.7 / AD7
MOVX @Ri,A 1 24 CPL A complement A 1 12 other on-chip features: temperature sensor, power supply monitor,
MOVX @DPTR,A 1 24 RL A rotate A left 1 12
watchdog timer, flexible serial interface ports,
precision voltage reference
PUSH direct push onto stack 2 24 RLC A ...through C 1 12
POP direct pop from stack 2 24 RR A rotate A right 1 12 PROGRAM MEMORY SPACE (read only)
XCH A,source exchange bytes 1,2 12 RRC A ...through C 1 12
XCHD A,@Ri exchg low digits 1 12 SWAP A swap nibbles 1 12 FUNCTIONAL BLOCK DIAGRAM
FFFFh
s

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P3.5 (T1 / CONVST)

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P1.1 (ADC1 / T2EX)

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Program Branching Boolean Variable Manipulation

P3.3 (INT1 / MISO)

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P1.5 (ADC5 / SS)

P1.0 (ADC0 / T2)

P2.2 (A10 / A18)

P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
P2.0 (A8 / A16)
P2.1 (A9 / A17)
ACALL addr11 2 24 CLR C 1 12

P1.2 (ADC2)
P1.3 (ADC3)
P1.4 (ADC4)

P1.6 (ADC6)
P1.7 (ADC7)
call subroutine clear bit to zero

P3.2 (INT0)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

P3.0 (RxD)
external

P3.1 (TxD)

P3.6 (WR)
P3.7 (RD)
LCALL addr16 3 24 CLR bit 2 12

P3.4 (T0)
program
RET return from sub. 1 24 SETB C 1 12 memory
set bit to one
RETI return from int. 1 24 SETB bit 2 12

43
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46
49
50
51
52

11
12
13
14

28
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30
31
36
37
38
39

16
17
18
19
22
23
24
25
1
2
3
4
AJMP addr11 2 24 CPL C 1 12
complement bit 64K bytes
hardware
LJMP addr16 3 24 CPL bit 2 12
2000h addressable
jump
CONVST 23
ADuC812
SJMP rel 2 24 ANL C,bit AND bit with C 2 24
JMP @A+DPTR 1 24 ANL C,/bit ...NOTbit with C 2 24 ADC0 1
ADC1 2 DAC1 BUF 9 DAC0
ADC2 3 ADC
JZ rel jump if A = 0 2 24 ORL C,bit OR bit with C 2 24 control DAC
ADC3 4 T/H 12bit ADC & control
JNZ rel jump if A not 0 2 24 ORL C,/bit ...NOTbit with C 2 24 1FFFh ADC4 11 AIN calibration
MUX
EA=1 ADC5 12 DAC1 BUF 10 DAC1
CJNE A,direct,rel 3 24 MOV C,bit 2 12 internal EA=0 ADC6 13
move bit to bit ADC7 14
8K bytes external
CJNE A,#data,rel compare and 3 24 MOV bit,C 2 24
jump if not Flash/EE
CJNE Rn,#data,rel equal 3 24 JC rel jump if C set 2 24 0000h 640 x 8 256 x 8
TEMP (-3 mV/oC) data user RAM
sensor 22 T0
CJNE @Ri,#data,rel 2 24 JNC rel jmp if C not set 2 24 Flash/EE
16bit 23 T1
DJNZ Rn,rel decrement and 2 24 JB bit,rel jump if bit set 3 24 counter
jump if not zero INTERRUPT VECTOR ADDRESSES 2.5V
bandgap 8K x 8
8052 timers 1 T2
DJNZ direct, rel 3 24 JNB bit,rel jmp if bit not set 3 24 reference program MCU watchdog 2 T2EX
Flash/EE core timer
NOP no operation 1 12 JBC bit, rel jmp&clear if set 3 24
Interrupt Vector Priority
within VREF 8 BUF downloader power supply
Interrupt Name Address Level debugger monitor
Bit 18 INT0

ASSEMBLER DIRECTIVES PRINTED IN U.S.A. CREF 7 19 INT1

single-pin
emulator
asynchronous synchronous
PSMCON.5 Power Supply Monitor Interrupt 43h 1 serial port serial interface
OSC
(UART) (SPI or I2C)
IE0 External Interrupt 0 03h 2
EQU define symbol DW store word values in program memory
ADCI End of ADC Conversion Interrupt 33h 3

16
17

42
41
40
15
DATA define internal memory symbol ORG set segment location counter

20
34
48
21
35
47

26
27
19
12

32
33
5

6
IDATA define indirect addressing symbol END end of assembly source file TF0 Timer0 Overflow Interrupt 0Bh 4

RxD
TxD

ALE
PSEN
EA
RESET

SDATA / MOSI
AVDD

MISO
AGND

SCLOCK

SS

XTAL1
XTAL2
IE1 External Interrupt 1 13h 5

DVDD

DGND
XDATA define external memory symbol CSEG select program memory space
BIT define internal bit memory symbol XSEG select external data memory space TF1 Timer1 Overflow Interrupt 1Bh 6
CODE define program memory symbol DSEG select internal data memory space
DS reserve bytes of data memory ISEG select indirectly addressed internal ISPI/I2CI SPI/I2C Interrupt 3Bh 7
DBIT reserve bits of bit memory data memory space RI/TI UART Interrupt 23h 8
DB store byte values in program memory BSEG select bit addressable memory space TF2/EXF2 Timer2 Interrupt 2Bh 9 www.analog.com/microconverter REV. B
 DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)
SFR DESCRIPTIONS
SFR MAP & RESET VALUES
ADCCON1 ADC Control register #1 IE Interrupt Enable register #1
ADCCON1.7 ADC power control bits EA enable inturrupts (0=all inturrupts disabled)

ADCCON1
00h

20h

DEh

00h

00h
PSMCON
ADCCON1.6 [shtdn, norm, autoshtdn, autostby] EADC enable ADCI (ADC interrupt)

EDATA4
(reserved)

(reserved)

(reserved)

(reserved)
(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)
SPIDAT

PCON
ADCCON1.5 conversion time = 15.5 / ADCclk ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
ADCCON1.4 ADCclk = Mclk / [1,2,4,8] ES enable RI/TI (serial port interrupt)
LOWER RAM
address

address
decimal

ADCCON1.3 acquisition time select bits ET1 enable TF1 (Timer1 overflow interrupt)

DFh
EFh

00h BFh
ADCCON1.2 acq time = [1,2,3,4] / ADCclk EX1 enable IE1 (external interrupt 1)

F7h

87h
HEX

ADCCON1.1 Timer2 convert enable ET0 enable TF0 (Timer0 overflow interrupt)
ADCCON1.0 external CONVST enable EX0 enable IE0 (external interrupt 0)

00h
127 7Fh ADCCON2 ADC Control register #2 IE2 Interrupt Enable register #2

EDATA3
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
(not used)

(not used)

(not used)

(not used)

(not used)

(not used)
EADRL
address

address
General Purpose ADCI ADC interrupt flag IE2.1 enable PSMI (power supply monitor interrupt)
... ... Area DMA DMA mode enable IE2.0 enable ISPI/I2CI (serial interface interrupt)

MSB

LSB
(bit addresses) CCONV continuous conversion enable bit
IP

00h BEh
C6h
48 30h SCONV single conversion start bit Interrupt Priority register
CS3 input channel select bits PSI priority of ISPI/I2CI (serial interface interrupt)
47 2Fh 7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h CS2 0000 - 0111 = ADC0 - ADC7 PADC priority of ADCI (ADC interrupt)

ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3

04h

00h

00h

00h
DACCON
CS1 1000 = temperature sensor PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)

EDATA2
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
(not used)

(not used)

(not used)

(not used)

(not used)
46 2Eh 77h 76h 75h 74h 73h 72h 71h 70h CS0 1111 = “HALT” command (DMA mode only) PS priority of RI/TI (serial port interrupt)

TH2

TH1
PT1 priority of TF1 (Timer1 overflow interrupt)
45 2Dh 6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h ADCCON3 ADC Control register #3 PX1 priority of IE1 (external INT1)

00h CDh

00h BDh
00h FDh

00h 8Dh
ADCCON3.7 busy indicator flag (0=ADC not active) PT0 priority of TF0 (Timer0 overflow interrupt)

*00h F5h
44 2Ch 67h 66h 65h 64h 63h 62h 61h 60h ADCCON3.6 (this bit must contain zero) PX0 priority of IE0 (external INT0)
ADCCON3.5 (this bit must contain zero)
43 2Bh 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h TMOD Timer Mode register

00h

C9h

00h
ADCCON3.4 (this bit must contain zero)

EDATA1
(reserved)

(reserved)

(reserved)

(not used)

(not used)

(not used)

(not used)

(not used)
DAC1H
ADCCON3.3 (this bit must contain zero) TMOD.3/.7 gate control bit (0=ignore INTx)

DMAP

ETIM3

DPP
42 2Ah 57h 56h 55h 54h 53h 52h 51h 50h

TH0
TL2
ADCCON3.2 (this bit must contain zero) TMOD.2/.6 counter/timer select bit (0=timer)
ADCCON3.1 (this bit must contain zero) TMOD.1/.5 timer mode selecton bits
41 29h Bit Addressable 4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h ADCCON3.0 (this bit must contain zero) TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]

00h CCh

04h BCh
00h FCh

00h D4h

C4h

00h 8Ch
*00h F4h

00h 84h
Area (upper nibble = Timer1, lower nibble = Timer0)
40 28h 47h 46h 45h 44h 43h 42h 41h 40h ADCDATAH
ADC Data registers TCON Timer Control register
ADCDATAL

55h
39 27h 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h

RCAP2H
(reserved)

(reserved)

ADCCON2 ADCDATAL ADCDATAH (reserved)

(not used)

(not used)

(not used)

(not used)

(not used)
I2CADD
TF1 Timer1 overflow flag (auto cleared on vector to ISR)

DAC1L

DMAH

ETIM2
TR1 Timer1 run control (0=off, 1=run)

DPH
TL1
38 26h 37h 36h 35h 34h 33h 32h 31h 30h DMAP,DMAH,DMAL DMA address pointer TF0 Timer0 overflow flag (auto cleared on vector to ISR)
37 25h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h TR0 Timer0 run control (0=off, 1=run)

00h CBh
ADCGAINH

52h BBh
00h FBh

00h D3h

00h 9Bh

00h 8Bh
*20h F3h

00h 83h
ADC Gain IE1 external INT1 flag (auto cleared on vector to ISR)
36 24h 27h 26h 25h 24h 23h 22g 21h 20h calibration coefficients IT1 IE1 type (0=level trig, 1=edge trig)
ADCGAINL IE0 external INT0 flag (auto cleared on vector to ISR)

00h
IT0 IE0 type (0=level trig, 1=edge trig)

RCAP2L
35 23h 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h

(reserved)

(reserved)

(not used)

(not used)

(not used)

(not used)

(not used)
I2CDAT
ADCOFSH

DAC0H

ETIM1
DMAL
ADC Offset TH0,TL0 Timer0 registers

DPL
TL0
34 22h 17h 16h 15h 14h 13h 12h 11g 10h ADCOFSL calibration coefficients
TH1,TL1 Timer1 registers

00h DAh

CAh

00h BAh
D2h
00h FAh

00h 9Ah

00h 8Ah
*00h F2h
33 21h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h

07h 82h
DACCON DAC Control register
32 20h 07h 06h 05h 04h 03h 02h 01h 00h DACCON.7 ModeSelect (0=12bit, 1=8bit) T2CON Timer2 Control register

00h
DACCON.6 DAC1 RangeSelect (0=VREF, 1=VDD) TF2 overflow flag

(reserved)

(reserved)

(reserved)

(reserved)

(not used)

(not used)

(not used)

(not used)
DAC0L
31 1Fh R7 DACCON.5 DAC0 RangeSelect (0=VREF, 1=VDD)

TMOD
ECON
EXF2 external flag

SBUF
DACCON.4 Clear DAC1 (0=0V, 1=normal operation)

IE2
RCLK receive clock enable (0=Timer1 used for RxD clk)

SP
30 1Eh R6 DACCON.3 Clear DAC0 (0=0V, 1=normal operation) TCLK transmit clock enable (0=Timer1 used for TxD clk)
DACCON.2 SynchronousUpdate (1=asynchronous) EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)

00h D9h

00h B9h

00h A9h
00h F9h

00h F1h

00h 99h

00h 89h

FFh 81h
29 1Dh R5 DACCON.1 PowerDown DAC1 (0=off, 1=on) TR2 run control (0=stop, 1=run)
DACCON.0 PowerDown DAC0 (0=off, 1=on) CNT2 timer/counter select (0=timer, 1=counter)
28 1Ch R4 Register DATA MEMORY SPACE DAC1H,DAC1L CAP2 capture/reload select (0=reload, 1=capture)

FFh

FFh

FFh
00h

00h

00h

00h

00h
DAC1 data registers
SPICON

Bank 3

I2CCON

WDCON
(read/write area)

T2CON
TH2,TL2 Timer2 register

SCON

TCON
27 1Bh R3

PSW
ACC
DAC0H,DAC0L DAC0 data registers

P3

P2

P1

P0
IP

IE
B

26 1Ah R2 RCAP2H,RCAP2L Timer2 Reload/Capture

ECON

D8h

D0h

C8h

C0h
data EE/FLASH comand register
E8h

E0h

B8h

B0h

A8h

A0h
F8h

F0h

98h

90h

88h

80h
25 19h R1 01h READ 04h VERIFY P0 Port0 register (also A0-A7 & D0-D7)
FFFFFFh 02h WRITE 05h ERASE
24 18h R0 9Fh ( page 159 ) 03h (reserved) 06h ERASE ALL P1 Port1 register (analog & digital inputs)
23 17h R7 EADRL data EE/FLASH address register T2EX timer/counter 2 capture/reload trigger
T2 timer/counter 2 external input
0

1
22 16h R6 EDATA1,EDATA2,EDATA3,EDATA4 P2

CAP2
SPR0

Port2 register (also A8-A15 & A16-A23)

WDE

RXD
CS0

PX0

EX0
I2CI

IT0
T2
RI
640 bytes
P
21 15h R5 data EE/FLASH Data registers
P3 Port3 register
D8h

D0h

C8h

C0h
E8h

E0h

B8h

B0h

A8h

A0h
(160 pages)
F8h

F0h

98h

90h

88h

80h
20 14h R4 Register data ETIM1,ETIM2,ETIM3 EE/FLASH timing regs RD external data memory read strobe
Bank 2 WR external data memory write strobe
0

1
Flash/EE
I2CTX
SPR1

CNT2

T2EX
19 13h R3 SPICON

WDS
SPI Control register T1 timer/counter 1 external input

TXD
CS1

PT0

ET0

IE0
(accessible
F1

T0 timer/counter 0 external input

TI
18 12h R2 ISPI SPI inturrupt (set at end of SPI transfer)
through INT1 external interrupt 1
D9h

D1h

C9h

C1h
E9h

E1h

B9h

B1h

A9h

A1h
F9h

F1h

99h

91h

89h

81h
WCOL write collision error flag
INT0 external interrupt 0
17 11h R1 SFRs) external SPE SPI enable (0=disable SPI & enable I2C)
TxD serial port transmit data line
data SPIM master mode select (0=slave)
0

1
I2CRS

WDR2
RxD serial port receive data line
CPHA

INT0
CPOL clock polarity select (0=SCLK idles low)

RB8
CS2

TR2

PX1

EX1
16 10h R0 memory
OV

IT1
CPHA clock phase select (0=leading edge latch) SCON Serial communications Control register
DAh

CAh
EAh

BAh

AAh
SPR1 SPI bitrate select bits
D2h

C2h
FAh

E2h

B2h

A2h

9Ah

8Ah
F2h

92h

82h
15 0Fh R7 00h ( page 0 ) SM0 UART mode control bits baud rate:
(16MEG SPR0 bitrate = Fosc / [4, 8, 32, 64]
SM1 00 - 8bit shift register - FOSC/12
14 0Eh R6 addressable) SPIDAT SPI Data register 01 - 8bit UART - TimerOverflowRate/32(x2)
0

1
EXEN2

WDR1
CPOL

I2CM

INT1 10 - 9bit UART - FOSC/64(x2)

CS3

RS0

TB8
PT1

ET1

IE1
13 0Dh R5 I2CCON I2C Control register 11 - 9bit UART - TimerOverflowRate/32(x2)
DBh

CBh
EBh

BBh

ABh
SM2 in modes 2&3, enables multiprocessor communication
FBh

D3h

C3h
E3h

B3h

A3h

9Bh

8Bh
F3h

93h

83h
12 0Ch R4 Register MDO master mode SDATA output bit REN receive enable control bit
Bank 1 FFh MDE master mode SDATA output enable TB8 in modes 2&3, 9th bit transmitted
128 bytes
CCONV SCONV
0

1
11 0Bh R3 SFRs MCO master mode SCLK bit RB8 in modes 2&3, 9th bit received
TCLK
SPIM

REN
upper RAM
RS1

TR0
MDI

MDI master mode SDATA input bit TI transmit interrupt flag

PS

ES

(direct
T0

10 0Ah R2 I2CM master mode select

(indirect RI receive interrupt flag
DCh

CCh
ECh

BCh

ACh

addressing
FCh

D4h

C4h

9Ch

8Ch
E4h

B4h

A4h
F4h

94h

84h
I2CRS serial port reset
9 09h R1 addressing only) I2CTX transmission direction status SBUF Serial port Buffer register
only) I2CI serial interface interrupt
0

1
PCON Power Control register
RCLK

PRE0

8 08h R0
MCO

I2CADD
SM2
SPE

I2C Address register

PT2

ET2

TF0
F0

T1

128 bytes PCON.7 double baud rate control

7 07h R7
DDh

CDh
EDh

BDh

ADh
FDh

D5h

C5h

9Dh

8Dh
E5h

B5h

A5h
F5h

95h

85h
I2CDAT I2C Data register PCON.4 ALE disable (0=normal, 1=forces ALE high)
lower RAM PCON.3 general purpose flag
6 06h R6 (direct or PCON.2 general purpose flag
WDCON
0

1
Watchdog Timer control register
WCOL

EADC
PADC
PRE1

PCON.1 power-down control bit (recoverable with hard reset)

EXF2

indirect
DMA
MDE

SM1

TR1
5 05h R5
WR
AC

PRE2 watchdog timeout selection bits PCON.0 idle-mode control (recoverable with enabled interrupt)
00h addressing) 000000h PRE1 timeout=[16,32,64,128,256,512,1024,2048]ms
DEh

CEh
EEh

BEh

AEh

PSW
FEh

D6h

C6h
E6h

B6h

A6h

9Eh

8Eh
F6h

96h

86h
4 04h R4 Register PRE0 Program Status Word
Bank 0 WDR1 watchdog timer refresh bits CY carry flag
3 03h R3
0

1
WDR2 set sequentialy to refresh watchdog AC auxiliary carry flag
PRE2
ADCI
MDO

SM0
ISPI

TF2

TF1

WDS watchdog status flag F0 general purpose flag 0

PSI

RD
CY

EA

2 02h R2 WDE watchdog enable RS1 register bank select control bits
DFh

CFh
EFh

D7h

C7h

BFh

AFh
FFh

E7h

B7h

A7h
F7h

9Fh

8Fh
97h

87h

RS0 active register bank = [0,1,2,3]

1 01h R1 PSMCON Power Supply Monitor control register OV overflow flag
PSMCON.7 (not used) F1 general purpose flag 1
0 00h R0 PSMCON.6 PSM status bit (1=normal / 0=fault) P parity of ACC
MAP KEY

these bits are contained in this byte PSMCON.5 PSM interrupt bit
PSMCON.4 trip point select bits DPP Data Pointer Page
mnemonic mnemonic PSMCON.3 [4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
SPR1 SPR0 SPICON PSMCON.2 DPH,DPL (DPTR) Data Pointer
address F9h 0 F8h 0 F8h 00h reset value PSMCON.1 AVDD/DVDD fault indicator (1=AVDD / 0=DVDD)
lower RAM PSMCON.0 PSM powerdown control (1=on / 0=off) ACC Accumulator
details SFR details reset value address
SP Stack Pointer
* calibration coefficients are preconfigured at power-up to factory calibrated values
B auxiliary math register