IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO.
8, AUGUST 2014 2281
A Integrated Noise 4 MHz Bandwidth
Second-Order Time-to-Digital Converter With
Gated Switched-Ring Oscillator
Wonsik Yu, Student Member, IEEE, KwangSeok Kim, Student Member, IEEE, and
SeongHwan Cho, Senior Member, IEEE
Abstract—This paper presents a second-order time-to-dig-
ital converter (TDC) by using a switched-ring oscillator (SRO)
and a gated switched-ring oscillator (GSRO). Unlike conventional
multi-stage noise-shaping (MASH) TDC using SROs, the pro-
posed TDC does not require complex calibration to compensate
for the error from frequency difference between the oscillators.
Furthermore, the performance of the proposed TDC is analyzed,
including non-idealities such as phase noise, mismatch, and PVT
variations. The prototype 1-1 MASH TDC achieves
integrated noise in 4 MHz signal bandwidth at 400 MS/s while
consuming 6.55 mW in a 65 nm CMOS process.
Index Terms—Delta-sigma modulation, gain error, gated
switched-ring oscillator (GSRO), gated-ring oscillator (GRO),
multi-stage-noise-shaping (MASH), noise shaping, oversampling,
switched-ring oscillator (SRO), time-domain, time-to-digital con-
verter (TDC).
I. INTRODUCTION
T IME-TO-DIGITAL converters (TDCs) have traditionally
been used in experimental physics as a time interval mea-
surement unit. Recently, with the continued scaling of CMOS
process, applications of TDC have been extended to all-digital
phase-locked loops (ADPLLs) [1], time-domain analog-to-dig-
ital converters (ADCs) [2], and jitter measurement circuits
[3], [4]. In these applications, TDC serves as the fundamental
building block that is critical to the overall performance.
Therefore, much research has been conducted to implement
high-performance TDCs which can achieve high-resolution,
high-linearity, and large bandwidth. Such efforts led to various
types of TDC architecture such as 2-D Vernier TDCs, two-step,
pipelined, cyclic, and SAR [5]–[11]. The architectures of these
TDCs mimic their Nyquist counterpart and thus do not achieve
as large a dynamic range and high resolution as the oversam-
pling architecture.
Manuscript received December 12, 2013; revised February 25, 2014 and
March 31, 2014; accepted April 15, 2014. Date of publication May 09, 2014;
date of current version July 24, 2014. This research was supported by the Basic
Science Research Program from the NRF of Korea funded by the Ministry of
Education (NRF-2013R1A2A1A01014872) and IDEC of KAIST. This paper
was recommended by Associate Editor J. M. de la Rosa.
W. Yu and S. Cho are with the Department of Electrical Engineering, KAIST,
Daejeon 305-701, Korea (e-mail: wonsik.yu@gmail.com; chosta@ee.kaist.ac.
kr).
K. Kim is with Broadcom Corporation, Irvine, CA 92618 USA (e-mail:
kskim@broadcom.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2014.2321195
1549-8328 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Recently, TDCs exploiting noise-shaping property have
also been proposed. In [12], [13], TDC is implemented by
using a time-to-voltage converter (T2V) that converts input time
to voltage and a conventional voltage-domain modulator to
process the converted voltage. As T2V and modulator both
require high-performance analog circuitries such as integrators
and DACs, it is difficult for such architecture to benefit from
advanced CMOS scaling. In order to overcome such problems,
methods that avoid analog circuitries have been introduced for
TDC, where digital circuits are exploited to achieve the de-
sired noise-shaping. In [14], a gated-ring oscillator based TDC
(GRO-TDC) has been introduced as a first-order TDC. Un-
like the T2V-based TDC, it consists mostly of digital circuits
such as counters and gated-ring oscillator and does not require
an explicit feedback loop. Unfortunately, oversampling ratio
(OSR) of a GRO-TDC is limited by the rate at which the
input pulse comes in since sampling frequency must be
the same as . Thus, time-resolution is limited if the input
pulse rate is low. To achieve high OSRs for low input pulse
rates, a switched-ring oscillator based TDC (SRO-TDC) [15]
has been proposed, where can be higher than , resulting
in a higher OSR and thus a finer time-resolution. However,
its noise-shaping order is limited to first-order and thus a very
high OSR is necessary when both high resolution and wide
bandwidth are required. To further improve the time-resolution
and signal bandwidth, a second-order multi-stage-noise-shaping
(MASH) TDC using two SROs has been proposed [16]. Unfor-
tunately, a high-order TDC using SROs requires complex
calibration to compensate for the systematic error that results
from the different operating frequencies of the SROs. As a re-
sult, it consumes additional power and area as well as a long
settling time [16].
This paper describes the detailed operation principle and IC
implementation of a novel second-order MASH TDC [17].
The proposed TDC achieves a fine time-resolution with low
complexity by using gated switched-ring oscillators (GSROs)
[17] which not only remove the need for complex calibration in
a high-order TDC but also allow high OSR.
This paper is organized as follows. In Section II, the archi-
tecture of the proposed second-order TDC is described. In
Section III, implementation details are presented. In Section IV,
we analyze the effect of non-idealities including the phase noise
and the mismatch of the GSRO as well as PVT variations. The
experimental results obtained from the prototype TDC are dis-
cussed in Section V. Finally, conclusions are drawn in Sec-
tion VI.
2282 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 8, AUGUST 2014

A. SRO-TDC
A simplified architecture of an SRO-TDC along with its op-
eration principle is shown in Fig. 1. The input pulse is
fed to the SRO which translates an input time interval
to frequency as shown in Fig. 1(b). The oscillation frequency
of the SRO is at a maximum when the input
pulse is high and at a minimum when it is low. Thus, the
average frequency of SRO during the input pulse period
can be described as

Fig. 1. (a) Block diagram of an SRO-TDC; (b) timing diagram of an SRO- (1)
TDC.
where
(2)
As a reset counter measures by counting the output edges
of the SRO during a sampling period , the average
of the digital output represents the input time interval.
An interesting property of the SRO-TDC is that first-order
noise-shaping can be achieved. This property can be explained
in the phase domain as shown in Fig. 2. The phase change of the
SRO due to the input pulse is given by

(3)

where is the phase-domain quantization error and can be

represented in form of a pulse. Thus, taking the -transform of
(3) gives

Fig. 2. The detailed operation principle of the SRO-TDC. (4)

It is evident from (4) that the SRO-TDC achieves first-order

noise-shaping.
II. PROPOSED 1-1 MASH TDC USING GSRO
B. 1-1 MASH TDC Using Two Cascaded SRO-TDCs
For modulators, there are two ways to realize high-order
By cascading two SRO-TDCs, a 1-1 MASH TDC can be
noise-shaping: single-loop and MASH. For single-loop struc-
implemented as shown in Fig. 3. The first-stage SRO-TDC that
ture, a second-order and a third-order noise-shaping TDC have
performs first-order noise shaping is followed by a quantization
been reported in [12], [13]. Both employ T2V and voltage-do-
error generator (QEGen) that produces a quantization error
main modulator, requiring precise analog circuitries not fa-
pulse every cycle. This first stage quantization error
vorable to scaled CMOS process. By contrast, MASH archi-
of width is fed to the second-stage SRO-TDC. At the
tecture exploits multiple low-order noise-shaping TDCs and in-
back-end of the TDC, a digital cancellation filter used in typical
creases the order of noise-shaping by simply cascading the mod-
MASH modulators is employed so that the first-stage quanti-
ulators. In [19], a 1-1-1 MASH TDC using the relaxation os-
zation error is removed and only the second-stage quantization
cillator has been introduced, which achieves third-order noise-
noise with second-order noise-shaping remains. The detailed
shaping. Unfortunately, its performance is limited by relaxation
operation principle of the 1-1 MASH can be explained as
oscillator’s low operating frequency and thus its time-resolution
shown in Fig. 4. Using (4), the output can be derived as
is no better than that of GRO-TDC or SRO-TDC which can op-
erate at much higher frequency.
In this work, we propose a novel MASH TDC which can ob- (5)
tain both high-resolution and wide bandwidth by using an SRO
and a GSRO. As SRO-TDC and GSRO serve as fundamental
building blocks of the proposed TDC, their operation principle
(6)
will first be analyzed.
YU et al.: A INTEGRATED NOISE 4 MHz BANDWIDTH SECOND-ORDER TIME-TO-DIGITAL CONVERTER 2283

Fig. 3. A simplified architecture of 1-1 MASH TDC using two identical SRO-
TDCs. and are the outputs of the SRO in the first and second stage, re-
spectively.

where

(7)

(8)

It is clear from (6) that is second-order noise-shaped. How-

ever, will appear at and severely deteriorate the Fig. 4. The timing diagram of the 1-1 MASH TDC using two identical SRO-
TDCs.
noise performance of the TDC unless . That is, a
non-zero undesired gain is multiplied to and it causes
to leak at the overall output. Unfortunately, having
is impossible because during , while the frequency of
SRO1 is controlled by , the frequency of SRO2 is controlled
by the . Hence, there is inevitable frequency difference be-
tween the first and second stage oscillators during as shown
in Fig. 4. During , while , since
an SRO2 generates additional phase during . In sum-
mary, when two SRO-TDCs are cascaded to form a 1-1 MASH, Fig. 5. Gated switched-ring oscillator (GSRO) [17]. (a) Block diagram and (b)
Timing diagram. represents the oscillation frequency of GSRO.
leakage is unavoidable and thus SNR is limited. In [16], this
problem is solved by using an off-chip calibration based on an the GSRO. Hence, the first stage operates as a conventional
LMS filter which typically takes long settling time. As a result, SRO-TDC. Using the input pulse, sampling clock, and output
it consumes additional power and area as well as a long settling of the GSRO1, QEGen produces a quantization error pulse of
time [16]. the first stage and a frequency sync pulse every
C. Proposed Second-Order TDC Architecture Using cycle which control the inputs of the second stage. Note that
GSRO the QEGen adds an offset of to to avoid narrow pulse
width which leads to a deadzone problem. Such offset is easily
As noted above, the main problem of cascading SRO-TDCs subtracted in the digital cancellation filter. Since controls
is that the phase-domain quantization error is not preserved, but the gates of the GSRO2 and controls the frequency of
is multiplied with an undesired gain owing to the frequency dif- the GSRO2, oscillation frequencies of the first stage SRO and
ference between the two SROs. We overcome this problem by second stage GSRO are the same during as shown in Fig. 7.
exploiting GSRO [17] whose operation principle is shown in Thus, the phase change of the second-stage GSRO
Fig. 5. As can be seen, a GSRO is basically an SRO whose is obtained as
frequency can be voltage-controlled (thus the name, VC-GRO
[18]), or an SRO with phase-holding gates added to its supply
and ground (thus the name, Gated-SRO or GSRO [17]). Hence,
the GSRO acts as an SRO when the gates are closed and holds
its phase like a GRO when the gates are open. In summary, there
are 3 oscillation frequencies of a GSRO: , and 0.
Using the GSRO, a calibration-free second-order noise-
(9)
shaping TDC is proposed as shown in Fig. 6, where identical
GSROs are placed in both the first and second stage. The From (9), it is evident that when a GSRO is employed in the
detailed operation principle is shown in Fig. 7. At the front-end second stage, leakage can be perfectly removed since (7) and
of the TDC, an on-chip pulse generator (PulseGen) produces (8) are the same. Hence, compared with the SRO-SRO MASH,
the input pulse from Start and Stop signals. In the first stage, the gain calibration is not needed and second-order noise
a GSRO is configured as an SRO by closing the EN gates of shaping can be achieved. To verify the proposed concept, a
2284 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 8, AUGUST 2014
Fig. 6. Implementation of the proposed second-order TDC architecture using GSRO.
respectively.
Fig. 7. The timing diagram of the proposed TDC using GSRO.
represent the oscillation frequency of the first-stage and the second-
stage GSRO, respectively.
behavior simulation using VerilogA is performed. The result is
shown in Fig. 8, where it can be seen that while the SRO-SRO
MASH TDC fails to achieve second-order noise-shaping due
to leakage, the proposed TDC achieves desired second-order
noise-shaping.
Although the first stage looks similar to the circuit shown in
[15], there are a couple of key differences that are noteworthy.
First, the frequency of the GSRO is designed to be higher than
so that there exists at least one rising edge during a sam-
pling period. This is because a residue pulse must be generated
every cycle to complete the second-order noise-shaping. This
and are the outputs of the GSRO in the first and second stage,
Fig. 8. Output spectrum of the SRO-SRO MASH and proposed TDC in Ver-
ilogA simulation. It is assumed that , ,
, , and . Note that all non-ide-
alities such as phase noise of GSRO, and sampling clock jitter does not exist in
this simulation to verify the effect of quantization error leakage due to system-
atic error.
is in contrast to [15] where the frequency of the SRO can be
smaller than and hence a residue pulse may not be produced
every cycle. Thus, the relationship between the frequency of
GSRO and as well as , is summarized as
. Second, the first stage counter counts only one of
the multi-phase outputs of the GSRO instead of counting all the
phases. As quantization error of the first stage is removed in the
final digital output, there is no need to count all the phases. As a
result, complexity and power consumption of the first stage are
and significantly reduced.
III. IMPLEMENTATION DETAILS
A. Gated Switched-Ring Oscillator (GSRO)
The circuit schematic of the GSRO is shown in Fig. 9,
which is basically a gated delay-line with frequency control via
CTRL. An important implementation issue of the GSRO is the
gating skew error due to the circuit non-idealities. Ideally, when
a GSRO is gated, the phase of GSRO must be held perfectly.
In practice, however, there exists several circuit non-idealities
such as leakage current and charge redistribution, which disrupt
the held phase and degrade the SNR [21]. In this work, a
multi-path structure [14] is applied to resolve the gating skew
error. Another benefit of the multi-phase structure is that it
YU et al.: A INTEGRATED NOISE 4 MHz BANDWIDTH SECOND-ORDER
Fig. 9. The circuit schematic of the proposed 9-stage GSRO.
Fig. 10. (a) Schematic of the QEGen and (b) Timing diagram of the QEGen.
allows the reduction of time-delay in the unit delay-cell. As
a result, the resolution of the proposed TDC can be further
improved by the reduced unit delay.
B. Quantization Error Generator (QEGen)
The proposed QEGen generates quantization error pulse
and a frequency sync pulse every cycle as shown in Fig.
10. In practice, the input pulse width of GSRO2 depends on
the quantization error of the first stage and thus can be very
narrow. Thus, the output pulse of PulseGen can disappear if the
pulse width of the quantization error is smaller than the rising
time of the PulseGen. Furthermore, as gates of the GSRO have
finite turn-on and turn-off time, a narrow pulse incurs deadzone
problem. To solve this issue, a static offset of is added to
by adding a flip-flop , as shown in Fig. 10. The static
offset can be easily subtracted in the digital cancellation filter
and does not affect the performance of the proposed TDC.
C. Multi-Bit Counter and Delayed Clock Generator
(DCLK-Gen)
As noted in previous section, of the GSRO must be de-
signed to be higher than so that a residue pulse appears every
cycle. Since , there can be more than one rising edge
during , and therefore a multi-bit counter is necessary instead
of a one-bit counter. One drawback of the multi-bit counter is
that there could be a large error when sampling occurs during
the transition of the counter output [20]. An example for a 4-bit
counter is shown in Fig. 11(b), where Reg1 samples
during the transition from 15 to 0. To reduce such error, a de-
layed sampling clock is employed as shown in Fig. 11(a) so
TIME-TO-DIGITAL CONVERTER 2285
Fig. 11. The proposed multi-bit counter with the delayed clock generator. (a)
Schematic of multi-bit counter and delayed clock generator, and (b) timing di-
agram.
that sampling occurs only after has settled. As a re-
sult, error is significantly reduced.
IV. EFFECT OF NON-IDEALITIES
For the practical GSRO, there exist non-idealities which can
limit the performance of the TDC such as phase noise and mis-
match of GSRO. In this section, such non-ideal effects of the
GSRO are analyzed and verified using Spectre and behavior
simulation. Throughout the simulation, we assume that
and are 1 GHz and 2.5 GHz and that and are 100
MHz and 200 MS/s, respectively.
A. Effect of GSRO’s Phase Noise
A practical GSRO suffers from the phase noise due to the
thermal and 1/f noise. That is, time-domain jitter is introduced
at the output of the GSRO, which can degrade the performance
of the proposed TDC. To see the effect of the phase noise, Ver-
ilogA simulation of the proposed circuit shown in Fig. 6 has
been performed when both GSRO1 and GSRO2 have a phase
noise of 95 dBc at a 1 MHz offset. The result is shown in
Fig. 13, where it can be seen that while the second-order quanti-
zation noise-shaping is preserved well, white noise floor is gen-
erated by the phase noise, resulting in the degradation of inte-
grate noise from to . Note that when we con-
figure the GSRO2 without the phase noise, the integrated noise
of is achieved. Thus, the result reveals that overall
noise performance does not depend on the second-stage. To ex-
plain such relationship, the proposed architecture is simplified
with its functional block as shown in Fig. 12, where the phase
noise of the GSRO is modeled as the output phase noise .
Assuming that the GSRO has a phase noise with a slope of 20
dB/decade, all of the phase noise is converted to the white noise
floor (i.e. 0 dB/decade) as the phase noise is first-order differen-
tiated by the counter. Thus, has negligible effect on the per-
formance of the TDC as it is first-order differentiated again by
2286 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 8, AUGUST 2014
Fig. 12. Simplified model of the proposed TDC with the phase noise of the
GSRO.
Fig. 13. Output spectrum of the proposed TDC with the phase noise of the
GSRO. It is assumed that the GSRO has a phase noise with a slope of 20
dB/decade and 95 dBc at 1 MHz offset.
the DCF as shown in Fig. 12. Unfortunately, cannot ben-
efit from the DCF. It is because in the first stage, the DCF does
not provide first-order difference operation as shown in Fig. 12.
Thus, it can be concluded that the low-noise GSRO must be de-
signed to obtain the desired performance.
B. Effect of Mismatch
As with any other analog circuits, the proposed TDC is
affected by mismatch. There are two types of mismatch
that needs to be considered in the proposed TDC: mismatch
between the GSRO delay cells and mismatch between the
first-stage and second-stage GSROs. First, regarding the
delay-cell mismatch in a GSRO, it does not have much effect
on the performance of the TDC. This is because only the
second-stage GSRO uses multi-phase outputs and thus, the
delay-cell mismatch occurs only in the second stage. Hence, the
effect of delay-cell mismatch is first-order noise-shaped by the
DCF. Furthermore, since the delay-cell mismatch is inherently
first-order noise-shaped [20], the delay-cell mismatch is overall
second-order noise-shaped.
Second, regarding the mismatch between the two GSROs that
cause frequency difference, it will have much severer effect.
This is because first-stage quantization error cannot be com-
pletely removed in the second stage as there is frequency dif-
ference and (9) cannot be satisfied. To see the effect of this
mismatch, we performed a monte-carlo simulation and the re-
sults are shown in Fig. 14, where is the standard deviation of
GSRO’s and divided by the nominal frequency of
the GSRO. It can be seen that the integrated noise as well as
the spread is increased with . Thus, it is important to employ
careful layout techniques to minimize the frequency mismatch
between the two GSROs.
Fig. 14. Monte-Carlo simulation for mismatch between two GSROs.
Fig. 15. Simulation results for PVT variations.
Fig. 16. Chip micrograph.
C. Effect of PVT Variation
In the preceding section, we have assumed that there are no
PVT variations in any of the circuits. However, in practice, the
performance of the proposed TDC will change according to dif-
ferent PVT conditions. To see the effect on the proposed TDC,
Spectre simulation has been performed. Fig. 15 shows simula-
tion results of the integrated noise under PVT variations, where
the simulation is conducted for different process (ss, nn, and ff),
voltage (1 V 0.1 V), and temperature
variations. The results reveal that the distribution range is much
smaller than the variation due to frequency mismatch. Also,
simulated integrated noise changes 25% compared to nom-
inal PVT condition (Process:nn, Voltage:1 V, Temperature:27
). Based on the simulation results including the mismatch
and phase noise, it can be concluded that performance limita-
tion mainly comes from frequency mismatch rather than PVT
variations.
In the aforementioned analysis, we have assumed that the
power supply of the GSRO is noiseless. In a practical scenario,
supply variation will cause drift of GSRO frequency. To alle-
viate this problem, a pseudo-differential architecture [15] can
YU et al.: A INTEGRATED NOISE 4 MHz BANDWIDTH SECOND-ORDER TIME-TO-DIGITAL CONVERTER 2287

Fig. 17. Measured output spectrums. 65,536pt FFT is performed with a Hanning window. Each of the output spectrums have been averaged for 4 sequential
sequences to reduce the variance of the noise measurement. (a) Output spectrum for and with 190 kHz 48 ps input. (b) Output
spectrum for and with 390 kHz 28 ps input. (c) Output spectrum for and with 390 kHz 19
ps input.

be applied to the proposed TDC as the effect of supply noise

can be canceled out at the final output.

V. EXPERIMENTAL RESULTS
A prototype of the proposed TDC was fabricated in a 65
nm CMOS process. It occupies an active area of
(0.053 ) as shown in Fig. 16. The proposed TDC is capable
of operating at input pulse rates up to 200 MHz and sampling
rates up to 400 MS/s. The power consumption of the proposed
TDC depends on the input pulse width . The upper limit
is 6.55 mW, which is when the input is always high. When the
average input pulse width is 1 ns, the power consumption is 5.35
mW. The power consumption of the DCF has not been included
as it was implemented off-chip. Thus, the power consumption
of the proposed TDC will be slightly increased with an on-chip
DCF which consists of three 8 bit adders, one 6 bit register, and
two 8 bit registers. To estimate the power consumption of the
DCF, Spectre simulation has been performed and the result is
0.08 mW and 0.17 mW at and , SRO-TDC, the performance of the proposed TDC can be fur-
respectively.
To verify the performance of the proposed TDC, three types
of measurement are performed. The first is a dynamic test to
measure the noise performance, the second is a single-shot pre-
cision test to measure the noise contribution of the TDC, and
the third is a static performance test to measure the linearity.
For dynamic performance, two input signals, Start and Stop,
are generated using the rising edge of a clock and the rising
edge of a phase-modulated clock, respectively. The phase-mod-
ulated clock is generated by modulating the power supply of an
off-chip delay-line. As phase modulation using supply voltage
is a nonlinear operation, harmonics of the input will appear
at the output. To avoid these spurs, input amplitude is chosen
to be very small. Then, an on-chip pulse-generator combines
these clocks and the output pulse goes to the input of the TDC.
An static offset of approximately 1 ns is added to the input to
avoid the deadzone of the on-chip pulse-generator. The output
spectrum of the proposed TDC is shown in Fig. 17(a) for the
case when , with a 48 ps
peak-to-peak sinusoidal input. It can be seen that second-order
noise-shaping is achieved with noise dominating at low
frequencies. The measured integrated noise from 10
kHz to 4 MHz is 70.8 dB, which translates to at
100 MHz input pulse rate. The performance of the TDC can be
further improved when is increased. The measured result for
Fig. 18. Measured integrated noise for different OSRs. The integrated noise is
varied by changing signal bandwidth.
twice the (400 MS/s) is shown in Fig. 17(b). The measured
within 4 MHz bandwidth is 73.3 dB, which trans-
lates to at 100 MHz input pulse rate. Similar to an
ther increased when is increased. It can be seen from (4)
that is a gain multiplied to . Hence, when
is increased, a higher SNR can be obtained for the same OSR.
To see this effect, the prototype chip is also measured at
, when the input is 19 ps peak-to-peak
sinusoidal input. The measured output spectrum is shown in
Fig. 17(c), where within 4 MHz bandwidth is 74.6
dB, which translates to at of 200 MHz.
The measured integrated noise versus OSR for different
is shown in Fig. 18, together with the result from [15]. It can
be seen that the integrated noise is improved with a higher .
Furthermore, it can be seen that the proposed TDC achieves
better performance than a conventional SRO-TDC under the
same OSR. The integrated noise of the proposed TDC is lim-
ited by thermal and noise at higher OSRs ( 100).
The noise contribution of the proposed TDC can also be veri-
fied throughout a single-shot precision (SSP) test which applies
a constant input time. The SSP test involves splitting one clock
signal into two clock signals by using a power splitter. Then,
one of the two clock signals is delayed by using a RF signal
cable. This setup removes the input jitter for the SSP test as two
rising edges of the clocks are generated from the same clock
signal. After low-pass filtering at 4 MHz, measured SSP results
for different and are shown in Fig. 19, where it can be
seen that these results correspond reasonably to the result of the
2288 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 8, AUGUST 2014
Fig. 19. Single-shot precision measurement. A constant input (approximately
2.5 ns) is applied to the TDC. (a) and .
(b) and . (c) and
.
Fig. 20. Measured static performance. The static measurement has been aver-
aged 8 times to remove the effect of the clock jitter. (a) DC transfer curve, (b)
INL.
measured integrated noise. Note that the discrepancy between
the measured and SSP results from different measure-
ment setup. It is because the off-chip delay-line for dynamic
testing provides additional jitter to the input, compared to SSP
test setup.
To measure the linearity of the proposed TDC, a static test is
performed by applying a ramp input [7], [15]. Again, the reason
why linearity cannot be measured by dynamic testing is because
of the difficulty in generating a phase modulated input with high
linearity. A 100 MHz signal and a 99.999 MHz signal are used to
generate a ramp input. For 200 MS/s of with 4 MHz low-pass
filtering, the measured result of DC transfer curve is shown in
Fig. 20(a), where it can be seen that the proposed TDC achieves
a measurement range of 4 ns. Assuming that our proposed TDC
becomes an 11-bit converter after 4 MHz low-pass filtering, the
maximum integral non-linearity (INL) is 1.96 LSB as shown in
Fig. 20(b).
The performance of the proposed TDC is summarized and
compared with the recent state-of-the-art TDCs in Table I.
The proposed TDC achieves the widest bandwidth while
achieving a good FoM.
VI. CONCLUSION
A novel second-order TDC has been introduced. Using
a GSRO and an SRO, the order of noise-shaping is increased
TABLE I
PERFORMANCE SUMMARY AND COMPARISON WITH OTHER STATE-OF-THE
ART TDCS
, where raw resolution is 6 ps and
range is 11 bit.
Estimated integrated noise .
Estimated resolution .
Maximum power consumption.
Estimated power consumption of DCF.
[dB], where
.
easily without any calibration. The proposed TDC is imple-
mented in 65 nm CMOS process and achieves integrated noise
of at 4 MHz signal bandwidth while consuming 6.55
mW.
We believe the proposed architecture is promising since
the speed of GSRO is expected to improve with scaled
CMOS process. Finally, it should be noted that higher-order
noise-shaping can be achieved by simply cascading more
GSRO-TDCs, which improves time-resolution and signal
bandwidth even further.
REFERENCES
[1] D.-W. Jee et al., “A 2 GHz fractional-N digital PLL with 1 b noise
shaping TDC,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp.
875–883, Dec. 2010.
[2] S. Naraghi et al., “A 9-bit, 14 and 0.06 pulse position mod-
ulation ADC in 90 nm digital CMOS,” IEEE J. Solid-State Circuits,
vol. 45, no. 9, pp. 1870–1880, Sep. 2010.
[3] K. Nose et al., “A 1 ps-resolution jitter-measurement macro using in-
terpolated jitter oversampling,” in Proc. IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2006, pp. 2112–2121.
[4] S. Henzler et al., “90 nm 4.7 ps-resolution 0.7-LSB single-shot preci-
sion and 19 pJ-per-shot local passive interpolation time-to-digital con-
verter with on-chip characterization,” in Proc. IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 548–635.
[5] A. Liscidini et al., “Time to digital converter based on a 2-dimensions
Vernier architecture,” in Proc. IEEE CICC, Sep. 2009, pp. 45–48.
[6] M. Lee and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-
digital converter in 90 nm CMOS that amplifies a time residue,” in
Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp.
168–169.
[7] K.-S. Kim et al., “A 7 bit, 3.75 ps resolution two-step time-to-digital
converter in 65 nm CMOS using pulse-train time amplifier,” IEEE J.
Solid-State Circuits, vol. 48, no. 4, pp. 1009–1017, Apr. 2013.
[8] J. S. Kim et al., “A 300-MS/s, 1.76-ps-resolution, 10-b asynchronous
pipelined time-to-digital converter with on-chip digital background
calibration in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol. 48,
no. 2, pp. 516–526, Feb. 2013.
YU et al.: A INTEGRATED NOISE 4 MHz BANDWIDTH SECOND-ORDER
[9] K.-S. Kim et al., “A 9 b, 1.12 ps resolution 2.5 b/stage pipelined
time-to-digital converter in 65 nm CMOS using time-register,” in
Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2013, pp.
136–137.
[10] Y. H. Seo et al., “A 1.25 ps resolution 8 b cyclic TDC in 0.13
CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 736–743, Mar.
2012.
[11] H. Chung et al., “A 10-Bit 80-MS/s decision-select successive approx-
imation TDC in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47,
no. 5, pp. 1232–1241, May 2012.
[12] M. Gande et al., “A 71 dB dynamic range third-order TDC using
charge-pump,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers,
Jun. 2012, pp. 168–169.
[13] B. Young et al., “A 2.4 ps resolution 2.1 mW second-order noise-
shaped time-to-digital converter with 3.2 ns range in 1 MHz band-
width,” in Proc. IEEE CICC, Sep. 2010, pp. 1–4.
[14] M. Z. Straayer et al., “A multi-path gated ring oscillator TDC with
first-order noise shaping,” IEEE J. Solid-State Circuits, vol. 44, no. 4,
pp. 1089–1098, Apr. 2009.
[15] A. Elshazly et al., “A 13 b 315 fsrms 2 mW 500 MS/s 1 MHz bandwidth
highly digital time-to-digital converter using switched ring oscillators,”
in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2012, pp. 464–466.
[16] T. Konishi et al., “A 61-dB SNDR 700 second-order all-digital
TDC with low-jitter frequency shift oscillator and dynamic flipflops,”
in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp.
190–191.
[17] W. Yu et al., “A 148 fsrms integrated noise 4 MHz bandwidth all-digital
second-order time-to-digital converter using gated switched-ring
oscillator,” in Proc. IEEE CICC, Sep. 2013, pp. 1–4.
[18] W. Yu et al., “A time-domain high-order MASH ADC using
voltage-controlled gated-ring oscillator,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 60, pp. 856–866, Apr. 2013.
[19] Y. Cao et al., “1-1-1 MASH time-to-digital converter with 6 ps
resolution and third-order noise-shaping,” IEEE J. Solid-State Circuits,
vol. 47, no. 9, pp. 2093–2106, Sep. 2012.
[20] J. Kim et al., “Analysis and design of voltage-controlled oscillator
based analog-to-digital converter,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 57, pp. 18–30, Jan. 2010.
[21] M. Z. Straayer, “Noise shaping techniques for analog and time to dig-
ital converters using voltage controlled oscillators,” Ph.D. dissertation,
MIT, Cambridge, MA, 2008.
TIME-TO-DIGITAL CONVERTER 2289
Wonsik Yu received the B.S. degree in electrical
engineering from Ajou University, Suwon, Korea,
in 2010, and received the M.S. degree in electrical
engineering from the KAIST, Daejeon, Korea, in
2012. He is currently working toward the Ph.D. de-
gree in electrical engineering at KAIST. His current
research interests include time-based analog-to-dig-
ital converter, time-to-digital converter, and digital
RF receivers.
KwangSeok Kim received the B.S. degree in EECS
from Hanyang University, Seoul, Korea, in 2009, and
received the Ph.D. degree in electrical engineering,
from KAIST, Daejeon, Korea, in 2013.
He is currently with Broadcom Corporation,
Irvine, CA, USA, as a Sr. Staff Scientist, where he
develops a frequency synthesizer including XOSCs
and LDOs.
SeongHwan Cho received the B.S. degree in elec-
trical engineering from KAIST, Korea, in 1995, and
the S.M. and Ph.D. degrees in EECS from MIT,
Cambridge, MA, in 1997 and 2002, respectively. In
2002, he joined Engim, Inc., where he was involved
in data converters and phased-locked loop (PLL) de-
sign for IEEE 802.11abg WLANs. Since November
2004, he has been with KAIST in the department
of EE, where he is now an Associate Professor. His
research interests include analog and mixed-signal
circuits for low power communication systems,
bio/health-care devices and CMOS sensors. Prof. Cho was the co-recipient of
the 2009 IEEE Transactions on Circuits and System Society Guillemin-Cauer
Best Paper Award and 2012 ISSCC Takuo Sugano Award for Outstanding
Far-East Paper. Prof. Cho serves on the Technical Program Committee on
several IEEE conferences, including ISSCC, Symp. on VLSI and A-SSCC.
He has served as Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS I from 2010 to 2011 and Guest Editor of JSSC. He has twice received
Outstanding Lecturer Award from the department of EE and KAIST.