Chapter 8 13

CHAPTER 8
DELTA
DEMODULATOR
8-1 Curriculum Objective
1. To understand the theory of delta demodulation.
2. To understand the signal waveforms of delta demodulation.
3. Design and implementation of delta demodulator.
4. Measurement and adjustment of delta demodulator.
8-2 Curriculum Theory
1. The Basic Theory of Delta Demodulation
As a result of the delta modulation excludes the encoder, therefore, the structure of delta
modulation is simpler than the structure of PCM. On the other hand, the DM signal only
consists of a single bit of estimated error value (Ɛq(k)), so, the required transmitted
bandwidth of DM signal is smaller than the PCM system.
In chapter 8, we know that the DM signal ( Xq(t))is a series diversity signal (Δ(t)),
therefore, the structure of the delta demodulator will be easier to achieve. Figure 8-1 is
the block diagram of delta demodulation. As a result of DM signal is a series diversity
signal, so we use the integrator to accumulate the series signal, then we get
yq (t) = Δ(t) + Δ(t – Ts) + Δ(t-2Ts) + Δ(t – 3Ts)+……. (8-1)
where
Δ(t) : The diversity signal, i.e. the magnitude of step value.

However, the accumulated series signal consists of high frequency harmonics, therefore,
we use the low-pass filter to remove the high frequency parts. Then we can demodulate
the DM signal and recover the low frequency signal, as shown in equation (8-2).
yD(t)=Lp {yq (t)} = x(t) (8-2)
From figure 8-1, the bipolar square wave will pass through the integrator and obtain
a waveform, which is similar to the audio signal. Then the output signal will pass through a
low-pass filter and finally, we can obtain the audio signal.
UNIPOLAR LOW- ANALOG

DM SAMPLING INTEGRATOR
TO PASS O/P
I/P
BIPOLAR FILTER
Figure 8-1 Block diagram of delta demodulation.
2. Implementation of Delta Demodulator
Figure 8-2 is the basic circuit diagram of delta demodulator. The D-type flip-flop is
the sampler. The input CLK signal of the delta demodulator must be synchronized with
the CLK signal of the delta modulator, which is the TTL signal. U1 :A is the
unipolar to bipolar converted circuit. As a result of the unipolar square wave signal is unable
to integrate to the original audio signal, therefore, we must convert the unipolar
signal to bipolar signal. U1 :B is the invert integrator, which can integrate the bipolar
square wave. If without adding resistor R 16 , the theoutput is
1 1 Vi 1
V0= -VC= - C ∫ idt= - C ∫ R dt= - RC ∫ Vi dt (8-3)
If the two terminals of the capacitor of the integrator shunt with a resistor, the
objective is to improve the low frequency response of the integrator, which utilizes
close loop gain of the inverter. Resistor R 16 and capacitor C1 can be assumed as a equivalent
impedance, then we get
1 𝑅16 𝑅16
𝑉0 𝑅16// 𝑠𝐶1 1+𝑠𝑅16𝐶1 𝑅15
= − = − = 𝑠 (8-4)
𝑉𝑖 𝑅15 𝑅15 1+
𝜔𝐻
Where
1
𝜔𝐻 =
𝑅16 𝐶1
U1:C, R7 , R10, C1, and C3 comprise a second order low-pass filter. Resistors R 5 and R 8
comprise a negative feedback, which its main function is to provide gain.
Figure 8-3 is the circuit diagram of delta demodulator, which is modified

from the basic circuit diagram in figure 8 -2. In figure 8-3, we added an analog switch.
It is similar to the delta modulator that we have added a multiplexer. The main
function is to control the gain of the integrator. Since the gain will affect the slope of
the integrator, therefore, by using the method, we can improve the problem of slope
overloading. The analog switch is similar to the structure of multiplexer. When AB=00,
the signal will be sent into the integrator through resistors R 4 , R 5 , R 6 , R 7 . When AB=11,
the signal will be sent into the integrator through resistor R
Figure 8-2 Basic circuit diagram of delta demodulator.
Figure 8-3 Circuit diagram of delta demodulator.

8-3: Experiment Items
Experiment 1: Delta demodulator
1. To implement a delta modulator circuit as shown in figure 7-3 or refer to figure DCT7-1 on
GOTT DCT-6000-04 module to produce the modulated delta signal. Let J2 and J3 be
short circuit, i.e. the connection between Xo and X is on. At the signal input port (I/P 1),
input a 2 V amplitude and 500 Hz sine wave frequency. Then at the CLK input port (I/P2),
input a 5 V amplitude and 32 kHz TTL signal.
2. To implement a delta demodulator circuit as shown in figure 8-3 or refer to figure DCT8-1
on GOTT DCT-6000-04 module.
3. In figure DCT8-1, let J2 and J3 be short circuit, i.e. the connection between Xo and X
is on. Then connect the modulated delta signal (O/P) in figure DCT7-1 to the input terminal
(I/P 1) of the delta demodulator in figure DCT8-1. At the CLK input port (I/P2) of the delta
demodulator, input a 5V amplitude and 32 kHz TTL signal. Then by using
oscilloscope, observe on the output signal waveforms of sampling signal output port (T1),
unipolar-to-bipolar (T2), tunable gain (T3), low-pass filter (T4), integrator (T5) and signal
output port (O/P). Finally, record the measured results in table 8-1.
4. According to the input signals in table 8-1, repeat step 3 and record the measured results in
table 8-1.
5. Let J2 and J4 in figure DCT7-1 and DCT8-1 be short circuit, i.e. the connection
between X 1 and X is on. At the signal input port (I/P 1) in figure DCT7-1, input a 2 V
amplitude and 1 kHz sine wave frequency. Next at the CLK input port (I/P2) in figure
DCT7-1, input a 5 V amplitude and 64 kHz TTL signal. Then connect the modulated
delta signal (O/P) in figure DCT7-1 to the input terminal (I/Pl) of the delta
demodulator in figure DCT8-1. At the CLK input port (I/P2) of the delta demodulator,
input a 53V amplitude and 64 kHz TTL signal. Then by using oscilloscope, observe on the
output signal waveforms of TI, T2, T3, T4, T5 and O/P. Finally, record the measured
results in table 8-2.
6. According to the input signals in table 8-2, repeat step 5 and record the measured results
in table 8-2.
amplitude and 1.5 kHz sine wave frequency. Next at the CLK input port (I/P2) in figure
DCT7-1, input a 5 V amplitude and 128 kHz TTL signal. Then connect the modulated delta
signal (O/P) in figure DCT7-1 to the input terminal (I/P 1) of the delta demodulator in
figure DCT8-1. At the CLK input port (I/P2) of the delta demodulator, input a 5 V
amplitude and 128 kHz TTL signal. Then by using oscilloscope, observe on the output
signal waveforms of TI, T2, T3, T4, T5 and O/P. Finally, record the measured results in
table 8-3.
8. According to the input signals in table 8-3, repeat step 7 and record the measured results
in table 8-3.
amplitude and 2 kHz sine wave frequency. Next at the CLK input port (I/P2) in figure
DCT7-1, input a 5 V amplitude and 256 kHz TTL signal. Then connect the modulated
delta signal (O/P) in figure DCT7-1 to the input terminal (I/Pl) of the delta demodulator
in figure DCT8-1. At the CLK input port (I/P2) of the delta demodulator, input a 5V
amplitude and 256 kHz TTL signal. Then by using oscilloscope, observe on the output
signal waveforms of TI, T2, T3, T4, T5 and O/P. Finally, record the measured results in
table 8-4.
10. According to the input signals in table 8-4, repeat step 9 and record the measured
8-4 : Measured Results
Table 8-1 Measured results of delta demodulation with 32 kHz CLK signal.
Measured Results
Input Signal
T1 T2
T3 T4
500 Hz
2V
T5 Audio O/P
Table 8-1 Measured results of delta demodulation with 32 kHz CLK signal.(Continue)
Measured Results
Input Signal
T1 T2
T3 T4
2 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
3 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
4 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
1 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
2 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
3 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
4 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
1.5 kHz
2V
T5 Audio O/P
Table 8-3 Measured results of delta demodulation with 128 kHz CLK signal. (Continue)
Measured Results
Input Signal
T1 T2
T3 T4
3 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
5 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
7 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
2 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
3 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
4 kHz
2V
T5 Audio O/P
Measured Results
Input Signal
T1 T2
T3 T4
5 kHz
2V
T5 Audio O/P
8-5 : Problem Discussion
1. Try to sketch the block diagram of delta demodulation.
2. If the signal of CLK is not TTL signal, then describe what will the output signal be.
3. If the input amplitude is smaller than 2 V, then describe what will the output
signal be.
4. If the channel selection of the analog switch for the modulator and demodulator are
different, then describe what will the output signal be after demodulation.
Chapter 9
Adaptive Delta
Modulator
9-1 : Curriculum Objectives
1. To understand the operation theory of adaptive delta modulation (ADM).
2. To understand the signal waveforms of ADM modulation.
3. Design and implementation of ADM modulator.
4. Measurement and adjustment of ADM modulator.
9-2 : Curriculum Theory
1. The Operation Theory of ADM Modulation
From previous chapter, we know that the disadvantage of delta modulation is when the
input audio signal frequency exceeded the limitation of delta modulator, i.e.
𝑑𝑥(𝑡)
fsΔ≥ | |
𝑑𝑡
Then this situation will produce the occurrence of slope overload and cause signal distortion.
However, the adaptive delta modulation (ADM) is the modification of delta modulation to
improve the disadvantage of the occurrence of slope overload.
Figure 9-1 is the block diagram of ADM modulator. In figure 9-1, we can see that the delta
modulator is comprised by comparator, sampler and integrator, then the slope controller and the
level detect algorithm comprise a quantization level adjuster, which can control the gain of the
integrator in the delta modulator. ADM modulator is the modification of delta modulator,
therefore, due to the delta modulator has the problem of slope overload at low and high
frequencies. The reason is the magnitude of the Δ(t) of delta modulator is fixed, i.e. the
increment of Δ or -Δ is unable to follow the variation of the slope of the input signal. When the
variation of the slope of the input signal is large, the magnitude of Δ(t) still can increase by
following the variation, then this situation will not occur the problem of slope overload. On the
other hand, there is another technique, which is known as continuous variable slope delta (CVSD)
modulation. This technique is commonly used in Bluetooth application. CVSD modulator is also
the modification of delta modulator, use to improve the occurrence of slope overload. The
different between the CVSD and ADM modulators are the quantization level adjuster A . ADM
modulator is discrete values and the quantization level adjuster of CVSD modulator is
continuous. Simply, the quantization value of ADM modulator is the variation of digital, such as
the quantization values of +1, +2, +3, -2, -3 and so on. As for CVSD modulator, the quantization
value is the variation of analog, such as the quantization values of +1, +1.1, +1.2, -1.5, -0.3, -0.9
and so on.
Figure 9-1 Block diagram of ADM modulator.
2. The Implementation of ADM Modulator
Figure 9-2 is the basic circuit diagram of ADM modulator. In figure 9-2, the audio
signal will pass through a low-pass filter, which can remove all the unwanted signal and
only obtain the audio signal. The input signals of the comparator are the audio signal and
triangle wave signal, then the output of the comparator is the square wave signal. The D-
type flip flop is used as sampling, then the output signal of the flip flop is the modulated
ADM signal. After that the signal will feedback to tunable gain amplifier and level
adjuster. In accordance with the different between the input signal x (t) and the reference
signal Xs(t), we can change the magnitude of the gain of the tunable amplifier. If the
different of the input signal and the reference signal is very large, then the level adjuster
will change the gain of the tunable amplifier so that the value of Δ(t) will become large.
On the other hand, if the different of the input signal and the reference signal is very
small, then the level adjuster will change the gain of the tunable amplifier so that the value
of Δ(t) will become small. With this advantage, when the frequency variation of the
input signal is large, then we can increase the value of Δ(t) to prevent the occurrence of
slope overload. And when the frequency variation of the input signal is small, then we
can decrease the value of Δ(t) to reduce the error.
Figure 9-2 Basic circuit of ADM modulator
Figure 9-3 is part of the circuit diagram of ADM modulator. The main reason is the
circuit diagram in figure 9-3 is similar to the circuit diagram of delta modulator in
chapter 7, therefore, please refer to chapter 7 for the operation theory of this
circuit. Since the ADM modulator is the modification of delta modulator, which is
used to improve the occurrence of slope overload, so, in this chapter, we will focus on
the implementation of auto alteration of the value Δ(t).
Figure 9-4 is the controlled circuit of Δ(t) value of ADM modulator. In figure 9-4, connect
the point A and point B in figure 9-4(a) to the point A and point B of the analog switch in
figure 9-3. Since by changing the values of point A and point B, we can change the gain of
the integrator, and then we can also change the magnitude of the period between the
output slope of the integrator and the output of the delta modulator. In figure 9-4(a), U1 is the
inverter. U5 and U6 comprise a synchronous counter, however, the CLK of the flip-flop is
positive edge trigger and the CLK of the counter is negative edge trigger. Therefore, in
order to synchronize the flip-flop and the counter, we need to add an inverter. Figure 9 -4(b)
is the output signal waveforms of each test points. Test point A is the modulated ADM
signal; test point B is the output signal waveform of Q of U5, which will operate with
test point A by "exclusion OR" (XOR), i.e. D = A G + (U5)Q . As a result of the circuit in
figure 9-4(a) utilize synchronous counter as the pulse detector and latch, so, the results of
test point C and test point F will be similar to each others. Test point G is the "AND"
between test point D and test point E. When the test point G is zero, the counter will
reset. At this moment, the output of the counter is zero and refer to the integrator in figure 9-3,
the gain will be
Figure 9-4(a) Circuit diagram of auto gain controller.
Figure 9-4(b) Output signal waveforms of each test point of the auto gain controller.
Figure 9-4 Circuit diagram and output signal waveforms of the auto gain controller.
From the above-mentioned equations, we know that when the value of .he counter
become larger, the gain of the integrator also become larger. If the output value of the
counter is larger than 3 but not yet reset to zero, then the counter will load the output
value into the counter, which means the increment will always maximum. The counter will
only reset until the pin CLR is "LOW". With this method, we can achieve the auto gain
control of the integrator. The different between the delta modulator and adaptive delta
modulator is that the gain of the integrator of the delta modulator is fixed. However, the
adaptive delta modulator will change the gain of the integrator according to the
modulated signal in present and past. In this chapter, the counter that we use is a 2 -bits
counter, therefore, there are only 4 variations of the increment values. In order to obtain
more increment values, we just need to change the counter and the analog switch.
9-3 : Experiment Items
Experiment 1: Adaptive Delta Modulator
1. To implement an adaptive delta modulator circuit as shown in figure 9-3 and figure 9-4 or
refer to figure DCT9-1 on GOTT DCT-6000-05 module.
2. At the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave
frequency. Next at the CLK input port (CLK I/P), input a 5 V amplitude and 32 kHz
TTL signal. Then observe the input signal (TP1), the output port of comparator
(TP2), the output port of the conversion from unipolar to bipolar (TP3), the gain
selection A (TP4), the output port of tunable gain (T6), the output port of slope
controller (TP7), the output port of integrator (T8) and the output port of adaptive
delta modulation signal (ADM O/P) by using oscilloscope. Finally record the
measured results in table 9-1.
table 9-1.
4. At the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave
TTL signal. Then observe the output signal waveforms of TP1, TP2, TP3, TP4, TP6,
TP7, TP8 and ADM O/P. Finally record the measured results in table 9 -2.
table 9-2.
Table 9-1 Measured results of ADM modulator with 32 kHz CLK signal.
INPUT SIGNAL OUTPUT SIGNAL WAVEFORMS
TP1 TP2
TP3 TP4
TP6 TP7
500 Hz
1V
TP8
ADM O/P
Table 9-1 Measured results of ADM modulator with 32 kHz CLK signal.(Continue)
TP1 TP2
TP3 TP4
TP6 TP7
1 kHz
1V
TP8
ADM O/P
Table 9-2 Measured results of ADM modulator with 128 kHz CLK signal.
TP1 TP2
TP3 TP4
TP6 TP7
500 Hz
1V
TP8
ADM O/P
Table 9-2 Measured results of ADM modulator with 128 kHz CLK signal. (Continue)
TP1 TP2
TP3 TP4
TP6 TP7
1 kHz
1V
TP8
ADM O/P
9-5: Problems Discussion
1. Explain the differences between adaptive delta modulation (ADM) and continuous variable
slope delta modulation (CVSD).
2. Explain the differences between delta modulation (DM) and adaptive delta modulation
(ADM).
3. Refer to figure 9-3, explain the functions of the integrator.
4. Refer to figure 9-4, explain how the circuit achieve auto gain control.
Chapter 10
Adaptive
Delta Demodulator
10-1 Curriculum Objective
1. To understand the operation theory of adaptive delta demodulation.
2. To understand the signal waveforms of ADM demodulation.
3. Design and implementation of ADM demodulator.
4. Measurement and adjustment of ADM demodulator.
10-2 Curriculum Theory
1. The Operation Theory of ADM Demodulation
In chapter 9, we utilized the structure of delta modulator and Δ(t) controlled circuit to
implement the ADM modulator and we also know that the modulated ADM signal is a kind of
TTL signal. Figure 10-1 is the block diagram of ADM demodulator. In figure 10-1, we can see
that the ADM demodulator is comprised by sampling, slope controller, level detect
algorithm, integrator and low-pass filter. The slope controller and the level detect algorithm
comprise a quantization level adjuster, which can control the gain of the integrator in the delta
demodulator. Since the gain of the integrator will affect the distortion of the recovered signal,
and the gain of
the integrator is controlled by the quantization level adjuster, therefore, in order to obtain the
recovered signal with low distortion, we need to design a good quantization level adjuster.
The main objective of the design of ADM is to reduce the slope overload effect.
On the other words, that means when the slope of the input signal is too large, then the ADM
will increase the quantization level (Δ), which can reduce the slope overload effect. Besides,
when the variation of the input signal is slow, the ADM will decrease the quantization level to
reduce the error. Therefore, ADM is an technique which utilizes the increment of the
dynamic range of quantization level to reduce the signal distortion.
CLK
I/P
ADM Sampling Quantization Level Integrator Audio

I/P Adjuster O/P
Figure 10-1 Block diagram of ADM demodulator
2. The Implementation of ADM Demodulator
Figure 10-2 is the basic circuit of ADM demodulator. The modulated ADM signal is inputted
from the D-type flip-flop, which the D-type flip-flop is the sampler. After that the output
signal of the flip-flop will be

sent into the tunable amplifier and level adjuster. The objective is to change the gain of
the tunable amplifier according to the difference between the input signal x(t) and the
reference signal Xs (t). If the difference between the input signal and the reference signal
is very large, then the level adjuster will change the gain of the tunable amplifier so
that the value of Δ(t) will become large. On the other hand, if the difference between the
input signal and the reference signal is very small, then the level adjuster will reduce the
gain of the tunable amplifier so that the value of Δ(t) will become small. With this
advantage, when the frequency variation of the input signal is large, then we can
increase the value of Δ(t) to prevent the occurrence of slope overload. And when the
frequency variation of the input signal is small, then we can decrease the value of Δ(t)
to reduce the error. Therefore, finally, we can obtain the recovered signal, which is
similar to the original signal at the integrator.
Figure 10-2 Basic circuit diagram of CVSD demodulator.

Figure 10-3 Circuit diagram of adaptive delta demodulator.
Figure 10-3 is part of the circuit diagram of ADM demodulator. The main reason is
the circuit diagram in figure 10-3 is similar to the circuit diagram of delta demodulator
in chapter 8, therefore, please refer to chapter 8 for the operation theory of this circuit.
In this chapter, we are mainly discussed the auto controlled of Δ(t) value. Since the
ADM modulator is the modification of delta modulator, which is used to improve the
occurrence of slope overload. And then the slope-controlled circuit is related to the gain
of the integrator and the gain of the integrator is related to the analog switch. The reason
is the channels of the analog switch are related to the resistors R4 to R7 whether series
with resistor R 8 or not. At the same time, the switching of channels of the analog
switch is controlled by the pin A and pin B.

Therefore, as similar to chapter 9, we will focus on the implementation of the controlled
circuit of the Δ(t) value by adding the circuit to pin A and. pin B.
Figure 10-4(a) is the controlled circuit of Δ(t) value. In figure 10 -4(a), UI is
the inverter. U5 and U6 comprise a synchronous counter, however, the CLK of the
flip-flop is positive edge trigger and the CLK of the counter is negative edge trigger.
Therefore, in order to synchronize the flip-flop and the counter, we need to add an
inverter. Connect the point A and point B in figure 10-4(a) to the point A and point B
of the analog switch in figure 10-3. Since by changing the values of point A and point B, we
can change the gain of the integrator, and then we can also change the magnitude of
the period between the output slope of the integrator and the output of the delta
modulator. Figure 10-4(b) is the output signal waveforms of each test points. Test point A
is the modulated ADM signal; test point B is the output signal waveform of Q of U5,
which will operate with test point A by "exclusion OR" (XOR), i.e. D = A +
(U5)Q .Asa result of the circuit in figure 10-4(a) utilize synchronous counter as the
pulse detector and latch, so, the results of test point C and test point F will be similar to
each others. Test point G is the "AND" between test point D and test point E. When
the test point G is zero, the counter will reset. At this moment, the output of the
counter is zero and refer to the integrator in figure 10-3, the gain will be
R11
Av = (10-1)
R4+R5+R6+R7+R8
When A:B = 01, the gain is
R11
Av = (10-2)
R5+R6+R7+R8
R11
Av = (10-3)
R6+R7+R8
R11
Av = (10-4)
R7+R8
Figure 10-4(a) Circuit diagram of auto gain controller.

Figure 10-4(b) Output signal waveforms of each test point of the auto gain controller.
Figure 10-4 Circuit diagram and output signal waveforms of the auto gain controller.
From the above-mentioned equations, we know that when the value of the counter
become larger, the gain of the integrator also become larger. If the output value of the
counter is larger than 3 but not yet reset to zero, then the counter will load the output
value into the counter, which means the increment will always maximum. The counter
will only reset until the pin CLR is "LOW". With this method, we can achieve the auto gain
control of the integrator. The different between the delta modulator and adaptive delta
modulator is that the gain of the integrator of the delta modulator is fixed. However, the
adaptive delta modulator will change the gain of the integrator according to the modulated
signal in present and past. In this chapter, the counter that we use is a 2 -bits counter,
therefore, there are only 4 variations of the increment values. In order to obtain more
increment values, we just need to change the counter and the analog switch.
Experiment 1: Adaptive Delta Demodulator
1. To implement a adaptive delta modulator circuit as shown in figure 9 -3 or refer to

figure DCT9-1 on GOTT DCT-6000-05 module to produce the modulated delta signal.
At the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave
TTL signal.
2. To implement a adaptive delta demodulator circuit as shown in figure 10-3 or refer to

figure DCT 10-1 on GOTT DCT-6000-05 module.
3. Connect the modulated delta signal (ADM O/P) in figure DCT9-1 to the input
port (ADM I/P) of the adaptive delta demodulator in figure DCTI0-1. At the CLK
input port (CLK I/P) of the adaptive delta demodulator, input a 5 V amplitude and 64
kHz TTL signal. Then by using oscilloscope, observe on the output signal waveforms of
sampling signal output port (TP1), unipolar-to-bipolar (TP2), the gain selection A
(TP3), the output port of slope controller (TP5), the input port of low-pass filter (TP6)
and the output port of audio signal (Audio O/P). Finally, record the measured results in
table 10-1.
4. According to the input signals in table 10-1, repeat step 3 and record the
5. To implement a adaptive delta modulator circuit as shown in figure 9-3 or refer to
figure DCT9-1 on GOTT DCT-6000-05 module to produce the modulated delta signal. At
the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave
frequency. Next at the CLK input port (CLK I/P), input a 5 V amplitude and 256 kHz TTL
signal.
6. Connect the modulated delta signal (ADM O/P) in figure DCT9 -1 to the input
port (ADM I/P) of the adaptive delta demodulator in figure DCT10-1. At the CLK input
port (CLK I/P) of the adaptive delta demodulator, input a 5 V amplitude and 25 6 kHz
TTL signal. Then by using oscilloscope, observe on the output signal waveforms of TP1, TP2,
TP3, TP5, TP6 and Audio O/P. Finally, record the measured results in table 10-2.
7. According to the input signals in table 10-2, repeat step 6 and record the
Table 10-1 Measured results of ADM demodulator with 64 kHz CLK signal.
Input Signals of ADM

Modulator Output Signal Waveforms
TP1 TP2
TP3 TP5
500 Hz TP6
1V
Audio O/P
(continue)

TP1 TP2
TP3 TP5
1 kHz
TP6
1V
Audio O/P

TP1 TP2
TP3 TP5
500 Hz
TP6
1V
Audio O/P
(continue)

TP1 TP2
TP3 TP5
1 kHz
TP6
1V
Audio O/P
1. If the sampling frequency is being increased or decreased, explain the affect of the
demodulator at the output port.
2. Refer to figure 10-3, explain the functions of the integrator.
3. Refer to figure 10-4, explain how the circuit achieve auto gain control.
Chapter 11
ASK Modulator
1. To understand the operation theory of the amplitude shift keying (ASK) modulation.
2. To understand the signal waveform of the ASK modulation.
3. To implement the ASK modulator by using MC 1496.
4. To understand the methods of testing and adjusting the ASK modulation circuit.
In the wireless digital communication, it is not easy to transmit the digital data directly.
This is because it needs to pass through the modulator and modulate the carrier signal in order
to send the signal effectively. One of the easiest ways is to use the different data stream to
change the amplitude of carrier, this kind of modulation is called amplitude modulation, and
we cal l i t as am pl i t ude shi ft ke yi n g ( AS K) m odul at i on i n digi t al communication.
Figure 11-1 is the basic circuit diagram of ASK modulator. Let the input data be 5 V,
when the signal pass through the buffer, the switch S 1 will switch to point A, at this time the
ASK output waveform is fl. When the input data is 0 V, when the signal pass through the
buffer, the switch S I will switch to point B, at this time the ASK output waveform is DC 0 V.
The above-mentioned is the basic theory of ASK modulation.
ASK modulation signal can be expressed as
In equation (11-1), the values of amplitude A i have M types of possible change, the
ωcand ϕ0 denote the cutoff frequency and phase, respectively. If we choose M =2 , the X ASK(t)
signal will transmit the binary signal, therefore, the values of A are A1 = 0 and A2 = A , A is
the arbitrary constant so we can obtain the binary ASK modulated signal waveform as
shown in figure 11-2. When input logic is 1, then the signal is transmitted out; when the input
logic is 0, then no signal is transmitted, so this also called on-off keying (OOK), this type of
method is used in the past time.
In this chapter, we utilize 2206 IC waveform generator and MC1496 multiplier to produce
the modulated ASK signal. First of all lets introduce the characteristics of 2206 IC. 2206 IC
is a waveform generator, which is similar to 8038 IC. Figure 11-3 is the circuit diagram
of the ASK modulator by using 2206 IC. In figure 11-3, resistors R2, R5 comprise a
voltage divided circuit. The main function of the voltage divided circuit is to let the
negative voltage waveform of the 2206 IC operates normally. The oscillation
frequency of 2206 IC is determined by resistor R I and the resistor located at pin 8. Its
oscillation frequencies are f l =1/2𝜋R 1 C, f 2 = l/2𝜋RC where R is the resistor at pin 8. If
R = ∞, then frequency f 2 equal to zero. There is an internal comparator in 2206 IC.
Assume that when the input is 5 V, the output frequency is f 1 , and when the input is 0 V,
the output frequency is f 2 . We can utilize the TTL signal at pin 9 to control the output
frequency to be f l or f 2 . This type of structure is similar to the structure in figure 11 -
1. Therefore, by using the characteristic of this structure, we can achieve ASK modulation
easily.
Figure 11-1 Basic circuit diagram of ASK modulator.

Figure 11-2 ASK modulation signal waveform.
Figure 11-3 Circuit diagram of ASK modulator by using 2206 IC.

Figure 11-4 The basic block diagram of ASK modulator.
Figure 11-4 is the basic block diagram of ASK modulator, which the balanced modulator
can meet the objectives of amplitude modulation, and the bandpass filter will remove the
high frequency signal to make the ASK signal waveform perfectly. We use the MC1496 to
implement the balanced modulator in this experiment. Figure 11-5 is the internal circuit
diagram of MC1496, where D 1 , R 1 , R 3 , Q 7 and Q 8 comprise a current source, it
provides DC bias current to Q 5 and Q 6 . The Q 5 and Q 6 comprise a differential
amplifier, which is used to drive the Q 1 , Q 2 , Q 3 and Q4 to become double differential
amplifiers. The data signal is inputted between pin 1 and pin 4. The carrier signal is
inputted between pin 8 and pin 10. The gain of balanced modulator is inputted between pin
2 and pin 3, which is controlled by the resistor between pin 2 and pin 3. The range of bias
current of the amplifier is determined by the resistor connected at the pin 5.
Figure 11-3 Internet circuit diagram of MC1496.
Figure 11-6 is the circuit diagram of ASK modulation, which the MC 1496 comprises a
balanced modulator. The carrier signal and data signal are single-ended input. The carrier
signal is inputted at pin 10 and the data signal is inputted at pin 1. R 13 and R 14 determine
the gain and the bias current of this circuit, respectively. If we adjust VR 1 or the data
signal amplitude, it can prevent the ASK modulation signal from distortion. Slightly
adjust VR 2 will avoid the asymmetric of the signal waveform. The pin 12 of balanced
modulator will send the output signal to uA741. The C 3, R 17 , R 18 and R 19 comprise a
bandpass filter to remove the high frequency signal, so that the ASK signal waveform will
become more perfect.

Figure 11-6 Circuitdiagram of ASK modulator by using MC1496.
Experiment 1: XR 2206 ASK modulator
1. Refer to figure 11 -3, R, = 1 kΩ or refer to figure DCT 11- 1 on GOTT DCT-6000-

06 module. Let J2 be short circuit and J3 be open circuit.
2. Let the two terminal of I/P be short circuit and JP1 be open circuit, i.e. at the data
signal input terminal (Data I/P), input 0 V DC voltage. By using oscilloscope,
observe on the output signal waveform of ASK signal (ASK O/P), then record the
3. Let the two terminal of I/P be open circuit and JP1 be short circuit, i.e. at the data
signal input terminal (Data I/P), input 5V DC voltage. By using oscilloscope,
observe on the output signal waveform of ASK signal (ASK O/P), then record the
4. At the data signal input terminal (Data I/P), input 5V amplitude, 100 Hz TTL
signal. By using oscilloscope, observe on the output signal waveform of ASK signal
(ASK O/P), then record the measured results in table 11-1.
5. According to the input signal in table 11-1, repeat step 4 and record the measured
6. Refer to figure 11 -3, R I = 5100 or refer to figure DCT 11-1 on GOTT DCT-6000-
06 module. Let J2 be open circuit and J3 be short circuit.
7. According to the input signal in table 11-2, repeat step 2 to step 4 and record the
Experiment 2: MC 1496 ASK modulator
1. Refer to figure 11-6 or refer to figure DCT11-2 on GOTT DCT-6000-06 module.
2. At the data signal input terminal (Data I/P), input 5 V amplitude, 500 Hz TTL signal. Then at the
carrier signal input terminal (Carrier I/P), input 400 mV amplitude and 20 kHz sine wave
frequency.
3. By using oscilloscope, observe on the output signal waveform of the modulated ASK signal
(ASK O/P ). Adjust VR 1 until the signal does not occur distortion. Then adjust VR 2 to avoid
the asymmetry of the signal. Finally record the output signal waveform of the balanced
modulator (TP1) and the ASK O/P in table 11-3.
4. According to the input signal in table 11-3, repeat step 2 to step 3 and record the measured
5. At the data signal input terminal (Data I/P), input 5V amplitude, 1 kHz TTL signal. Then
at the carrier signal input terminal (Carrier I/P), input 400 mV amplitude and 20 kH z sine
wave frequency.
6. Follow the adjustment in step 3, then record the output signal wavefor m of the balanced
results in table 11 -4.
8. At the data signal input terminal (Data I/P), input 5 V amplitude, 1 kHz TTL signal. Then at
the carrier signal input terminal (Carrier I/P), input 400 mV amplitude and 100 kHz sine
wave frequency.
9. Follow the adjustment in step 3, then record the output signal waveform of the balanced
Table 11-1 Measured results of ASK modulator by using 2206 IC.
Input Signal
0 V (I/P SC , J1 OC) 5V (J1 SC , I/P OC)
J2 SC
J3 OC
100 Hz 200 Hz
Input Signal
J2 SC
J3 OC
Table 11-2 Measured results of ASK modulator by using 2206 IC.
Input Signal
0 V (I/P SC , J1 OC) 5V (J1 SC , I/P OC)
J2 OC
J3 SC
100 Hz 200 Hz
Input Signal
J2 OC
J3 SC
Table 11-3 Measured results of ASK output signal waveforms by varying the data signal frequency. (VC =
v
400 m . fc = 20 kHz)
Input Signal
Data I/P TP1
Vp = 5 V
fData = 500 Hz
ASK O/P
Table 11-3 Measured results of ASK output signal waveforms by varying the data signal frequency.
v
(continue) (VC = 400m . fc = 20 kHz)
Input Signal
Data I/P TP1
Vp = 5 V
fData = 1 kHz
ASK O/P
Table 11-4 Measured results of ASK output signal waveforms by varying the carrier signal frequency.
v
(VC = 400 m . fData = 1 kHz)
Carrier Signal
Frequencies Carrier I/P TP1
20 kHz
ASK O/P
v
(continue) (VC = 400 m . fData = 1 kHz)
Carrier Signal
50 kHz
ASK O/P
(fC= 100 kHz . fData = 1 kHz)
Carrier Signal
400 mV
ASK O/P
Tab1le 11-5 Measured results of ASK output signal waveforms by varying the carrier signal frequency.
(continue) (fC= 100 kHz . fData = 1 kHz)
Carrier Signal
1V
ASK O/P
1. In figure 11-6, what are the functions of µA741, C3, R17, R18 and R19?
2. In figure 11-6, what are the purposes of VR1and VR2 ?
3. In figure 11-6, what are the purposes of R13 and R14 ?

Chapter 12
ASK Demodulator
1. To understand the operation theory of ASK demodulation.
2. To understand the operation theory of ASK asynchronous detector.
3. To understand the operation theory of ASK synchronous detector.
4. To understand the methods of testing and adjusting the ASK demodulation circuit.
In chapter 11, we have mentioned that we need a modulator to modulate the data to a
high carrier frequency, so that the signal can be transmitted effectively. Therefore, for receiver,
we must convert the digital signal back to the modulating signal. Figure 12-1 shows the
theoretical diagram of ASK demodulation. There are two methods to design the ASK
demodulator, which are asynchronous detector and synchronous detector. We will discuss
these two types of ASK demodulator in this chapter.

1. Asynchronous ASK Detector.
Figure 12-2 is the block diagram of asynchronous ASK detector. This structure is a typical
asynchronous ASK detector. When the ASK signal pass through the rectifier, we can obtain the
positive half wave signal. After that the signal will pass through a low-pass filter and obtain an
envelop detection. Then get rid of the DC signal, the digital signal will be recurred.
Figure 12-3 is the circuit diagram of asynchronous ASK detector, which R 1 , R 2 and
µA741 comprise an inverting amplifier to amplify the input signal. Then D 1 is the
rectifying diode to make the modulation signal passes through D 1 half wave rectifier. R 3
and C 1 comprise a low-pass filter. µA741, VR 1 , D 2 , R 4 and C 2 comprise a comparator,
therefore, the output terminal can demodulate the digital demodulated signal.
Figure 12-2 Block diagram of asynchronous ASK detector.
Figure 12-3 Circuit diagram of ASK asynchronous detector.

2. Synchronous ASK Detector
We have mentioned before that we can use synchronous detector to design the ASK
demodulation. This experiment utilizes the structure of square-law detector and the block
diagram is shown in figure 12-4. Let XASK(t) be the ASK modulated signal, which is
In equation (12-1), the values of amplitude A i have M types of possible change, the ω c
and ϕ 0 denote the cutoff frequency and phase constant, respectively. When we input the ASK
modulated signal to the two input terminals of balance modulator, then the output signal of
balanced modulator can be expressed as

Figure 12-5 Internal circuit diagram of MC1496 balanced modulator.
Figure 12-6 Circuit diagram of ASK synchronous detector.

where k represents the gain of balanced modulator. The first term of equation (12-2) is
the data signal amplitude and the second term is the 2nd harmonic of the modulated signal.
From the output signal xout(t)if the first data signal amplitude receives the demodulated ASK
signal, this means that the data signal can be recovered correctly.
In this chapter, we utilize MC1496 balanced modulator to design the square-law
detector as shown in figure 12-5. Figure 12-5 is the internal circuit diagram of MC1496
balanced modulator (Readers may refer to the circuit diagram in chapter 11).
Figure 12-6 is the circuit diagram of synchronous ASK detector. In figure 12-6, Q1 , C1 ,
C 2 , R2 , R3 and R 4 comprise an emitter follower. VR 1 controls the input ranges of modulated
ASK signal and the output signal of MC1496 (pin 12) is shown in equation (12-2). The C9, C11
and R13 comprise a low-pass filter, which the objective is to remove the 2 nd harmonic of
modulated ASK signal as shown in the second term in equation (12-2). The first term in the
equation (12-2) is the data signal amplitude part, which can be recovered by using the
comparator and voltage limiter comprised by µA741, VR2, D1 and D2.

Experiment 1: Asynchronous ASK detector (XR 2206)
1. Use the ASK modulator in chapter 11 with R, = 1 M (as shown in figure 11-3) or refer to
figure DCT 11-1 on GOTT DCT-6000-06 module to produce the amplitude modulated signal as
the modulated ASK signal input. Let J2 be short circuit and J3 be open circuit.
2. At the data signal input terminal (Data I/P) in figure DCT11-1, input 5V amplitude and 100
Hz TTL signal.
3. Connect the ASK signal output terminal (ASK O/P) in figure DCT11 -1 to the signal input
terminal of the asynchronous ASK detector (ASK I/P) in figure DCT 12-1.
4. Adjust the variable resistor VR 1 in figure DCT12-1 to obtain the optimum reference level
of the comparator. By using oscilloscope, observe on the output signal waveforms of the
negative feedback amplifier (TP1), demodulated signal output port (TP2), comparator
reference level (TP3) and the digital signal output port (Data O/P). Finally, record the
6. Use the ASK modulator in chapter 11 with R, = 510 Ω (as shown in figure 11 -3) or refer to
figure DCT 11-1 on GOTT DCT-6000-06 module to produce the amplitude modulated
signal as the modulated ASK signal input. Let J2 be open circuit and J3 be short circuit.
Experiment 2: Asynchronous ASK detector (MC 1496)
1. Use the ASK modulator in chapter 11 (as shown in figure 11 -6) or refer to figure DCT11-2
on GOTT DCT-6000-06 module to produce the amplitude modulated signal as the modulated
ASK signal input.
2. At the data signal input terminal (Data I/P) in figure DCT11-2, input 5 V amplitude and 100 Hz
TTL signal. At the carrier signal input terminal (Carrie r I/P), input 400 mV amplitude and 20
kHz sine wave frequency.
3. Adjust VR 1 of ASK modulator in figure DCT11-2 and observe on the modulated ASK signal
before the signal occurs distortion, then slightly adjust VR 2 to avoid the asymmetry of the
signal to obtain the optimum output waveform of modulated ASK signal (ASK O/P).
4. Connect the ASK signal output terminal (ASK O/P) in figure DCT11-2 to the signal input terminal
of the asynchronous ASK detector (ASK I/P) in figure DCT 12- 1.
5. Adjust the variable resistor VR 1 in figure DCT12-1 to obtain the optimum reference level
of the comparator. By using oscilloscope, observe on the output signal waveforms of the
negative feedback amplifier (TP1), demodulated signal output port (TP2), comparator
reference level (TP3) and the digital signal output port (Data O/P). Finally, record the measured
7. At the data signal input terminal (Data I/P) in figure DCT11-2, input 5V amplitude and 100
Hz TTL signal. At the carrier signal input terminal (Carrier I/P), input 400 mV amplitude
and 100 kHz sine wave frequency.
Experiment 3: Synchronous ASK detector
1. Use the ASK modulator in chapter 11 (as shown in figure 11 -6) or refer to figure DCT 11-2 on
GOTT DCT-6000-06 module to produce the amplitude modulated signal as the modulated ASK
signal input.
2. At the data signal input terminal (Data I/P) in figure DCT11-2, input 5V amplitude and 1 kHz
TTL signal. At the carrier signal input terminal (Carrier I/P), input 400 mV amplitude and
100 kHz sine wave frequency.
3. Adjust VR1 of ASK modulator in figure DCT11-2 and observe on the modulated ASK
signal before the signal occurs distortion, then slightly adjust VR 2 to avoid the asymmetry
of the signal to obtain the optimum output waveform of modulated ASK signal (ASK O/P).
4. Connect the ASK signal output terminal (ASK O/P) in figure DCT11 -2 to the signal input
terminal of the asynchronous ASK detector (ASK I/P) in figure DCT 12-2.
5. By using oscilloscope and switching to DC channel, then adjust VR 2 of figure DCT12-2 to

obtain the optimum comparator reference voltage. Then observe on the output signal
waveforms of the emitter follower (TP1), balanced modulator (TP2), comparator (TP3) and data
signal output port (Data O/P). Finally, record the measured results in table 12-5. If the signal
output waveform occurs distortion, then slightly adjust VR 1 .
7. At the data signal input terminal (Data I/P) in figure DCT11-2, input 5 V amplitude and 1
kHz TTL signal. At the carrier signal input terminal (Carrier I/P), input 400 mV amplitude and 40
kHz sine wave frequency.
Table 12-1 Measured results of ASK demodulator by using asynchronous detector. (2206 IC, J2
SC, J3 OC)
Data Signal Data I/P ASK O/P

Frequencies
Vp = 5 V TP1 TP2
fData = 100 Hz
TP3 Data O/P

Table 12-1 Measured results of ASK demodulator by using asynchronous detector. (continue)
(2206 IC, J2 SC, J3 OC)

Frequencies
Vp = 5 V TP1 TP2
fData = 500 Hz
TP3 Data O/P

Table 12-2 Measured results of ASK demodulator by using asynchronous detector. (2206 IC, J2
OC, J3 SC)

Frequencies
TP1 TP2
Vp = 5 V
fData = 100 Hz
TP3 Data O/P

(2206 IC, J2 OC, J3 SC)

Frequencies
TP1 TP2
Vp = 5 V
fData = 500 Hz
TP3 Data O/P

Table 12-3 Measured results of ASK demodulator by using asynchronous detector. (MC 1496,
Vc = 400mV, fc = 20 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 100 Hz
TP3 Data O/P

Table 12-3 Measured results of ASK demodulator by using asynchronous detector.(continue)
(MC 1496, Vc = 400mV, fc = 20 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 500 Hz
TP3 Data O/P

Vc = 400mV, fc = 100 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 100 Hz
TP3 Data O/P

(MC 1496, Vc = 400mV, fc = 100 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 500 Hz
TP3 Data O/P

Vc = 400mV, fc = 100 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 1kHz
TP3 Data O/P

(MC 1496, Vc = 400mV, fc = 100 kHz)

Frequencies
TP1 TP2
Vp = 5 V
fData = 5 kHz
TP3 Data O/P

Vc = 400mV, fdata = 1 kHz)

Frequencies
TP1 TP2
40 kHz
TP3 Data O/P

(MC 1496, Vc = 400mV, fdata = 1 kHz)

Frequencies
TP1 TP2
70 kHz
TP3 Data O/P

1. In figure 12-3, if we neglect the µA741 op-amp and connect the ASK modulator to the
diode detector, then what are the results?
2. What are the purposes of the comparators in figure 12-3 and figure 12-6?
3. In figure 12-6, what are the objectives of R13, C9 and C11?
4. In figure 12-6, what are the objectives of D1 and Dz?

Chapter 13
FSK Modulator
1. To understand the operation theory of FSK modulator.
2. To understand the FSK modulation by using the theory of mathematical.
3. To design and implement the FSK modulator by using VCO.
In digital signal transmission, the repeater is used to recover the data signal, this will enhance the
immunity to noise. So the coding technique can be used to detect, correct and encrypt the
signal. During long haul transmission, the high frequency part of the digital signal
will easily attenuate and cause distortion. Therefore, the signal has to be modulated before
transmission, and one of the methods is the frequency-shift keying (FSK) modulation. FSK
technique is to modulate the data signal to two different frequencies to achieve effective
transmission. At the receiver, the data signal will be recovered based on the two different
frequencies of the received signal.

The relation of FSK signal and data signal is shown in figure 13-1. When the data
signal is 5V, after the signal pass through the buffer, the switch S1 will OFF, then the
frequency of FSK signal is f l . When the data signal is 0 V, after the signal pass through
the buffer, the switch S2 will OFF, the frequency of FSK signal is f 2 . Normally, the
difference between frequencies f 1 and f 2 has to be as large as possible. This is
because the corelation of both signals is low, therefore, the effect of transmitting and
receiving will be better. However, the required bandwidth must be increased. Figure 13-2 is
the signal waveforms of FSK modulation.
Figure 13-1 Structure diagram of FSK modulator.

Figure 13-2 Relation diagram between data signal and FSK signal.
In this section, we utilize the theory of mathematic to solve the FSK modulation as
shon in equation (13-1).The expression are as follow.The technique of FSK is widely
used in commercial and industrial wire transmission and wireless transmission. In the
experiments, we will discuss how to produce FSK signal. In certain applications, the
FSK signal is fixed. For example, for wireless transmission, the mark signal is 2124 Hzand
space signal is 2975 Hz. For wire transmission such as telephone, the frequencies are as follow
Space 1370 Hz
Mark 870 Hz
or
Space 2225 Hz
Mark 2025 Hz
From the above mentioned, we notice that the frequency gap of FSK is 500 Hz.
In FSK modulator, we use data signal (square wave) as the signal source. The
output signal frequency of modulator is based on the square wave levels of the data signal. In
this chapter, the frequencies of the carriers are 870 Hz and 1370 Hz. These two frequencies can
be produced by using a voltage controlled oscillator, (VCO). The output signal frequencies
are varied by the difference levels of the input pulse to produce two different frequencies. Each
output signal frequency corresponds to an input voltage level (i.e. "0" or "1").
In this chapter, we utilize 2206 IC waveform generator and LM 566 voltage controlled
oscillator to produce the modulated FSK signal. First of all lets introduce the characteristics of
2206 IC. 2206 IC is a waveformgenerator, which is similar to 8038 IC. Figure 13-3 is the
circuit diagram of the FSK modulator by using 2206 IC. In figure 13 -3, resistors
R 3 , R 4 comprise a voltage divided circuit. The main function of the voltage divided circuit
is to let the negative voltage waveform of the 2206 IC operates normally. The
oscillation frequency of 2206 IC is determined by resistors R1 and R5. Its oscillation
frequencies are f 1 =1/2𝜋R 1 C, f 2 =1/2𝜋R 5 C. There is an internal comparator in 2206 IC.
Assume that when the input is 5 V, the output frequency is and when the input is 0 V,
the output frequency is f 2 . We can utilize the TTL signal at pin 9 to control the output
frequency to be fl or f 7 . This type of structure is similar to the structure in figure 13 -1.
Therefore, by using the characteristic of this structure, we can achieve FSK modulation
easily.
Figure 13-3 Circuit diagram of FSK modulator by using 2206 IC.
Next, we use LM566 voltage control oscillator to implement the FSK modulator. First
of all, we will discuss the varactor diode. Varactor diode or tuning diode is mainly used for
changing the capacitance value of oscillator. The objective is to let the output frequency of
oscillator can be adjusted or tunable, therefore varactor diode dominates the tunable range of
the whole voltage controlled oscillator.
Varactor diode is a diode, which its capacitance can be varied by adding a reverse bias to
pn junction. When reverse bias increases, the depletion region become wide, this will cause
the capacitance value decreases; nevertheless when reverse bias decreases, the depletion region will
be reduced, this will cause the capacitance value increases. Varactordiode also can be varied from
the amplitude of AC signal.
Figure 13-4 is the capacitance analog diagram of varactor diode. When a varactor diode without
bias, the concentration will be differed from minor carriers at pn junction. Then these carriers will
diffuse and become depletion region. The p type depletion region carries electron positive ions,
then the n type depletion region carries negative ions. We can use parallel plate capacitor to
obtain the expression as shown as follow:
where
ɛ=11.8ɛ0 (dielectric constant of Silicon)
ɛo = 8.85 x10-12
A: the cross section area of capacitor.
d: the width of depletion region.
When reverse bias increases, the width of depletion region d will increase but the
cross section area A remains, therefore the capacitance value would be reduced. On
the other hand, the capacitance value will increase when reverse bias decreases.
Figure 13-4 Capacitance analog diagram of varactor diode.

Figure 13-5 Equivalent circuit diagram varactor diode.
Varactor diode can be equivalent to a capacitor series a resistor as shown in figure

13-5. From figure 13-5, C j is the junction capacitor of semiconductor, which only
exits in pn junction. R S is the sum of bulk resistance and contact resistance of
semiconductor material, which is related to the quality of varactor diode (generally below a
few ohm).
Tuning ratio, TR is the ratio of capacitance value under two different biases for varactor
diode. The expression is shown as follow:
Where V cc is the power supply voltage input at pin 8 of LM566. V in is the input voltage of
LM566 at pin 5.
If Vcc i s fix ed, t hen wit h proper R 1 0 , C 5 and V i n , t he output signal frequencies
(f 0 ) of LM566 will be 1072 Hz and 1272 Hz. The conditions for using LM566 VCO are as
follow
Figure 13-6 is the circuit diagram of FSK modulator. The operation theory is to convert the
voltage level of data signal (TTL levels) to appropriate voltage level. This voltage will
input to the input terminal of LM566 VCO. Then, the VCO will produce two frequencies with
respect to the input voltage levels (870Hz and 1370Hz). The Q 1, Q2 , R1,R2, R3, VR1 and VR2
comprise a voltage converter. In the circuit, Q1 will operate as NOT gate. When the input signal
of the base of Q1 is high, then Q1 will switch on. At this moment, the output signal of the
collector will be low (around 0.2 V), so Q2 will switch off. When input signal of the base of
Q1 is low (0 V), Q 1will switch off. At this moment, the output signal of collector of Q1 is high(5
V), so, Q 2 will switches on. When Q 2 switch off, the input voltage of VCO is
The VCO output signal frequency is f l . When Q 2 switches on, the input voltage of VCO is
(assume the resistance of Q 2 is only a few ohm)
At this moment, the output signal frequency of VCO is f 2 . So, we just need to adjust VR 1
and VR 2 , then the output signal frequencies of VCO will become f l and f 2 which are
1370 Hz and 870 Hz, respectively. In figure 13-6, the two µA741, R5, R6, R7, R8, R9, R10,
C3, C4, C5 and C6 comprise a 4th order low-pass filter. The objective is to remove the
unwanted signal from the LM566 VCO output (TP2), so that we can obtain the
sinusoidal waveform signal.
Figure 13-6 Circuit diagram of FSK modulator.

Experiment 1: XR 2206 FSK modulator
1. Refer to figure 13-3 with R, = 1 kΩ and R5 = 10 kΩ or refer to figure DCT13-1 on

GOTT DCT-6000-07 module. Let J2 and J4 be short circuit, J3 and J5 be open circuit.
2. From figure DCT13-1, let the two terminal of I/P be short circuit and JP1 be open circuit, i.e. at
the data signal input terminal (Data I/P), input 0V DC voltage. By using oscilloscope, observe on
the output signal waveform of FSK signal (FSK O/P), then re cord the measured results in table
13-1.
3. From figure DCT13-1, let the two terminal of I/P be open circuit and JP1 be short circuit, i.e.
at the data signal input terminal (Data I/P), input 5V DC voltage. By using oscilloscope, observe
on the output signal waveform of FSK signal (FSK O/P), then record the measured results in
table 13-1.
4. At the data signal input terminal (Data I/P), input 5 V amplitude, 100 Hz TTL signal. By using
oscilloscope, observe on the output signal waveform of FSK signal (FSK O/P), th en record the
5. According to the input signal in table 13-1, repeat step 4 and record the measured results in
table 13-1.
6. Refer to figure 13-3 with R 1 = 7.5kΩ and R 5 = 15 kΩ or refer to figure DCT13-1
on GOTT DCT-6000-07 module. Let J2 and J4 be open circuit, J3 and J5 be short
circuit.
Experiment 2: LM566 FSK modulator
1. Refer to the circuit diagram in figure 13-6 or figure DCT13-2 on GOTT DCT-6000-07
module.
2. From figure DCT13-2, let the two terminal of I/P be short circuit and JP1 be open circuit, i.e. at
the data signal input terminal (Data I/P), input 0V DC voltage. By using oscilloscope, observe on
the output signal waveform of the VCO output port (TP2) of LM 566. Slightly adjust VR 2 so that
the frequency of TP2 is 1370 Hz. Again observe on the output signal waveforms of the charge
and discharge test point (TP1), second order low-pass filter (TP3) and FSK signal output port
(FSK O/P). Finally, record the measured results in table 13 -3.
3. From figure DCT13-2, let the two terminal of I/P be open circuit and JP1 be short circuit, i.e. at
the data signal input terminal (Data I/P), input 5 V DC voltage. By using osc illoscope, observe on
the output signal waveform of the VCO output port (TP2) of LM 566. Slightly adjust VR2 so that
the frequency of TP2 is 870 Hz. Again observe on TP1, TP3 and FSK O/P. Finally, record the
4. At the data signal input terminal (Data I/P), input 5V amplitude and 200 Hz TTL signal. By
using oscilloscope, observe on the output signal waveforms of Data I/P, TPI, TP2, TP3, and FSK
O/P. Finally, record the measured results in table 13-4.
5. According to the input signal in table 13-4, repeat step 4 and record the measured results
in table 13-4.
Table 13-1 Measured results of FSK modulator by using 2206 IC.
Input Signal
0V 5V
J2 , J4
SC
J3 , J5
OC
Input Signal TTL Signal with Vp = 5V , f =

TTL Signal with Vp = 5V , f = 200Hz
100Hz
J2 , J4
SC
J3 , J5
OC
Table 13-2 Measured results of FSK modulator by using 2206 IC.
Input Signal
0V 5V
J3 , J5
SC
J2 , J4
OC
Input Signal TTL Signal with Vp = 5V , f =

TTL Signal with Vp = 5V , f = 200Hz
100Hz
J3 , J5
SC
J2 , J4
OC
Table 13-3 Measured results of FSK modulator by using LM566.
Input Signal
TP1 TP2
0V TP3 FSK O/P

Table 13-3 Measured results of FSK modulator by using LM566. (continue)
Input Signal
TP1 TP2
5V TP3 FSK O/P

Table 13-4 Measured results of FSK modulator by using LM566.
Input Signal
TP1 TP2
TP3 FSK O/P
TTL Signal
with Vp = 5V
f = 200Hz
FSK O/P
Table 13-4 Measured results of FSK modulator by using LM566. (continue)
Input Signal
TP1 TP2
TP3 FSK O/P
TTL Signal
with Vp = 5V
f = 100Hz
FSK O/P
1. In figure 13-6, what are the functions of Q1, Q2 and LM566?
2. In figure 13-6, what are the functions of variable resistors VR1 and VR2?
3. In figure 13-6, if the input signal is larger than the FSK frequency, will this circuit operate
properly? (i.e. compare the 200 Hz and 900 Hz input signals in table 13-3)

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CHAPTER 8

1. To understand the theory of delta demodulation.

2. To understand the signal waveforms of delta demodulation.

3. Design and implementation of delta demodulator.

4. Measurement and adjustment of delta demodulator.

8-2 Curriculum Theory

1. The Basic Theory of Delta Demodulation

yq (t) = Δ(t) + Δ(t – Ts) + Δ(t-2Ts) + Δ(t – 3Ts)+……. (8-1)

Δ(t) : The diversity signal, i.e. the magnitude of step value.

yD(t)=Lp {yq (t)} = x(t) (8-2)

UNIPOLAR LOW- ANALOG

Figure 8-1 Block diagram of delta demodulation.

2. Implementation of Delta Demodulator

Figure 8-3 is the circuit diagram of delta demodulator, which is modified

Figure 8-3 Circuit diagram of delta demodulator.

Experiment 1: Delta demodulator

1. Try to sketch the block diagram of delta demodulation.

1. To understand the operation theory of adaptive delta modulation (ADM).

2. To understand the signal waveforms of ADM modulation.

3. Design and implementation of ADM modulator.

4. Measurement and adjustment of ADM modulator.

9-2 : Curriculum Theory

1. The Operation Theory of ADM Modulation

2. The Implementation of ADM Modulator

Figure 9-2 Basic circuit of ADM modulator

Experiment 1: Adaptive Delta Modulator

INPUT SIGNAL OUTPUT SIGNAL WAVEFORMS

INPUT SIGNAL OUTPUT SIGNAL WAVEFORMS

INPUT SIGNAL OUTPUT SIGNAL WAVEFORMS

INPUT SIGNAL OUTPUT SIGNAL WAVEFORMS

3. Refer to figure 9-3, explain the functions of the integrator.

1. To understand the operation theory of adaptive delta demodulation.

2. To understand the signal waveforms of ADM demodulation.

3. Design and implementation of ADM demodulator.

4. Measurement and adjustment of ADM demodulator.

10-2 Curriculum Theory

1. The Operation Theory of ADM Demodulation

ADM Sampling Quantization Level Integrator Audio

Figure 10-1 Block diagram of ADM demodulator

2. The Implementation of ADM Demodulator

signal of the flip-flop will be

similar to the original signal at the integrator.

Figure 10-2 Basic circuit diagram of CVSD demodulator.

switch is controlled by the pin A and pin B.

Figure 10-4(a) is the controlled circuit of Δ(t) value. In figure 10 -4(a), UI is

When A:B = 01, the gain is

When A:B = 10, the gain is

When A:B = 11, the gain is

Figure 10-4(a) Circuit diagram of auto gain controller.

Experiment 1: Adaptive Delta Demodulator

1. To implement a adaptive delta modulator circuit as shown in figure 9 -3 or refer to

2. To implement a adaptive delta demodulator circuit as shown in figure 10-3 or refer to

Input Signals of ADM

Input Signals of ADM

Input Signals of ADM

Input Signals of ADM

2. Refer to figure 10-3, explain the functions of the integrator.

2. To understand the signal waveform of the ASK modulation.

3. To implement the ASK modulator by using MC 1496.

11-2 : Curriculum Theory

method is used in the past time.

negative voltage waveform of the 2206 IC operates normally. The oscillation

R = ∞, then frequency f 2 equal to zero. There is an internal comparator in 2206 IC.

frequency to be f l or f 2 . This type of structure is similar to the structure in figure 11 -