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FM Global 7-7R
Property Loss Prevention Data Sheets 17-12R
January 2003
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Table of Contents
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7-7R REFERENCE DOCUMENT
List of Figures
Fig. 1. Process gas distribution arrangements ............................................................................................. 4
Fig. 2. Wet bench free burn test. ................................................................................................................. 13
Fig. 3. Flow diagram of semiconductor fabrication. ..................................................................................... 17
Fig. 4. Semiconductor fabrication facility systems diagram. ........................................................................ 18
Fig. 5. Clean bay service aisle. .................................................................................................................... 22
Fig. 6. Tool service corridor. ......................................................................................................................... 23
Fig. 7. Various arrangements of a wet bench and associated fume exhaust ductwork. ............................ 24
List of Tables
Table 1.
Gases Used in Fabrication ............................................................................................................. 5
Table 2.
Silane Mixtures ................................................................................................................................. 6
Table 3.
Flammable and Combustible Liquids Used in Fabrication .............................................................. 8
Table 4.
Process Reactions ........................................................................................................................... 9
Table 5.
Vacuum Applications Used in Fabrication ...................................................................................... 10
Table 6.
Material Nomenclature and Use .................................................................................................... 14
Table 7.
Common Nonflammable Semiconductor Process Liquids ........................................................... 26
Table 8.
Possible Water Damage Sources ................................................................................................. 27
Table 9.
Selected airborne particulate cleanroom classes for cleanrooms and cleanzones
defined by ISO 14644-1 ................................................................................................................. 32
Table 10. Comparison between different Cleanroom Class Standards ....................................................... 32
1.0 SCOPE
This reference data sheet describes the process flow and processing tools used to fabricate semiconductors.
Included is an overview of the requirements of other applicable codes used by the industry at the national
and international levels. Basic terminology used by the industry is provided along with a bibliography of
reference material.
PROCESS
HAZARD
F — flammable
P — pyrophoric
T — toxic (T)-toxic byproducts
C — corrosive
I — inert
O — oxidizer
2.1.1.1 Silane
Silane, which is discussed in detail under Section 2.6, more so than other gases used in semiconductor manu-
facturing, can lead to severe exposures. It is a stable gas but is pyrophoric, that is, under certain condi-
tions, it can spontaneously ignite.
The trend today is to use higher concentrations of silane. In addition, silane is being used as a carrier gas
for arsine and phosphine. In the event of a leak, the pyrophoric silane reaction would likely consume the
poisonous arsine and phosphine. The process properties of silane mixtures can be found in Table 2.
2.1.1.2 Dichlorosilane
Dichlorosilane (DCS) is a pyrophoric, toxic, corrosive and colorless gas. Its boiling point is 47°F (8.3°C).
The minimum autoignition temperature is 111°F (44°C).
DCS is used for a variety of chemical vapor deposition reactions. It is used to form epitaxial layers as well
as silicon dioxide, silicon nitride, and polysilicon layers.
DCS tends to slowly decompose during storage. This is only a problem in the presence of heat and/or cata-
lysts such as amines or Lewis acids. Decomposition products are silane, monochlorosilane, trichlorosilane
and silicon tetrachloride.
Due to the corrosive nature of DCS, there is concern regarding its effect on carbon steel cylinders and valves.
Therefore, no more than a 12-month shelf life is recommended.
Minimum ignition energy (MIE) is 0.0154 mJ (second to hydrogen which is the lowest measured MIE).
Combustion produces amorphous silica, water, hydrogen chloride gas, and chlorine.
Due to its low vapor pressure (9 psi [0.6 bar]) and concern about proper distribution flow, there is a preference
in the industry to locate process cylinders of DCS close to the process tool to minimize the length of distri-
bution pipe. However, this results in process DCS cylinders being located in service chases and subfabs
which, in turn, results in an unnecessary exposure to the cleanroom, process tools and related support
equipment.
Some facilities have overcome the low vapor pressure distribution flow issue by insulating and heat tracing
the distribution piping. This allows them to locate process DCS cylinders in properly arranged process gas
distribution rooms which do not expose the cleanroom, process tools and related support equipment.
2.1.1.3 Trichlorosilane
Another chlorinated silane gas is trichlorosilane (TCS) which is used to produce polycrystalline silicon and
to form silicon epitaxial layers. With a boiling point of 89°F (32°C) and a flash point of 7°F (–14°C), TCS is
normally found in liquid form.
reaction source for chlorine trifluoride because it is normally readily available in the surroundings. Expo-
sure to chlorine trifluoride in the presence of a relative humidity of 50% has been shown to cause signifi-
cant corrosion in a short period of time to materials.
Since chlorine trifluoride decomposes instantaneously when exposed to atmospheric conditions (moist air),
the compound in its original form cannot be monitored or detected. The presence of chlorine trifluoride must
be sensed through one of its by-products.
Electrochemical detectors or paper tapes are two methods being successfully used to detect chlorine trifluo-
ride through its by-products. Hydrogen fluoride (HF) is the major by-product of chlorine trifluoride reactions
with moist air, however, detectors based on hydrogen fluoride do not have the capability to sense very low con-
centrations of HF (less than 0.1 ppm). For this reason, detectors calibrated for HF should only be used to
detect high quantity chlorine trifluoride leaks. In critical areas where life safety is required, detectors calibrated
for chlorine dioxide provide the most accurate indication of chlorine trifluoride.
Detection based on HF, HCL, chlorine or fluorine are not recommended as they will not provide accurate
detection at TLV or sub-TLV values of chlorine trifluoride.
In air, chlorine trifluoride reacts rapidly with oxygen and water to form highly toxic and corrosive products,
such as hydrogen fluoride, hydrogen chloride, fluorine, chlorine and chlorine dioxide.
2.1.1.5 Hydrogen
Hydrogen gas is widely used and is the primary carrier for the dopant gases such as silane, phosphine, ars-
ine, diborane, etc. It can be found in both cylinder and cryogenic form. Even though the flammable and explo-
sive properties of hydrogen are well documented, there have been numerous adverse incidents involving
this gas. These incidents generally involve some kind of leak and ignition of the gas by many different sources.
The storage of flammable/combustible photoresist, developer and rinse within the fabrication area creates
an unnecessary exposure to the cleanroom and process tools. If storage of these liquids inside the clean-
room is absolutely necessary, such storage should be arranged in accordance with Section 2.2.5 of the Data
Sheet 7-7/17-12.
The developing, rinsing, and etching portions of the fabrication process are typically performed in plastic
work stations called wet benches (Figs. 17 and 18 in Data Sheet 7-7/17-12). Process liquids (both flam-
mable and nonflammable) are often heated by using hot plates, electric immersion heaters, liquid heat trans-
fer systems or steam heated bench inserts; more modern wet benches may use in-line, infrared heaters
which are safer.
Various studies and loss experience have shown that if the fume exhaust ductwork does not collapse dur-
ing a fire, the fume exhaust system will effectively remove smoke and heat. However, if the ductwork col-
lapses, smoke contamination of the cleanroom is usually widespread. Once products of combustion are
released from a collapsed duct, the cleanroom recirculating air system will pick up these products, and dis-
tribute them throughout the cleanroom in seconds. The need to keep the fume exhaust ductwork intact is criti-
cal. (See Section 2.4. FM Approved Duct Systems.)
for dielectric and dissolved gas in oil analysis. Isolation transformers experience both high temperatures and
high voltages so testing to detect gassing is critical. The transformer tank withstand strength is unknown. Iso-
lation transformers with a 208 V primary are electrically protected by 240 V circuit breakers similar to what
is used in the home. These breakers may have interruption capability as low as 10,000 amps. Fault cur-
rents higher than this may occur and breakers of larger interrupting capability will be required. Current limi-
tation is not provided on the primary. Ground fault protection is not feasible on the secondary because the
transformer neutral is connected to the HVDC.
2.1.6.3 Ion Implanters — National Electric Code (NEC) Requirements for Transformers
Oil insulated transformers installed indoors must be installed in accordance with the provisions of the NEC.
The following is quoted directly from NFPA 70-1996, National Electrical Code, Article 450 Transformers and
Transformer Vaults:
Article 450-26. Oil-insulated Transformers Installed Indoors. ‘‘Oil-insulated transformers installed indoors shall
be installed in a vault constructed as specified in Part C of this article.’’ There are several exceptions to this
rule. Exception 1 and 2 may be applicable.
‘‘Exception No. 1: Where the total capacity does not exceed 112.5 kVA, the vault specified in Part C of this
article shall be permitted to be constructed of reinforced concrete not less than 4 in. (102 mm) thick.’’
‘‘Exception No. 2: Where the nominal voltage does not exceed 600, a vault shall not be required if suitable
arrangements are made to prevent a transformer oil fire from igniting other materials, and the total capac-
ity in one location does not exceed 10 kVA in a section of the building classified as combustible, or 75 kVA
where the surrounding structure is classified as fire-resistant construction.’’
The phrase ‘‘total capacity’’ in the above refers to adding the kVA of all of the transformers in the section
of a building. If one had 4 transformers each rated 30 kVA, the ‘‘total capacity’’ would be 120 kVA. A vault
in accordance with Article 450, Part C. Transformer Vaults of the NEC would therefore be required.
At the May, 1998 NFPA meeting an exception to NFPA 70, National Electric Code, Article 450 ‘‘Transformers
and Transformer Vaults’’ was granted. This exception was submitted by the implanter manufacturers and
reads as follows:
‘‘Section 450-26, Exception No.4: A transformer that is an integral part of charged particle accelerating equip-
ment having a total rating not exceeding 75 kVA shall be permitted to be installed without a vault in a build-
ing or room of noncombustible or fire-resistant construction, provided suitable arrangements are made to
prevent a transformer oil fire from spreading to other combustible material.’’
This exception effectively allows oil filled ion implanter transformers up to 75 kVA rating to be allowed in a
cleanroom. By this exception, multiple implanters containing several hundred gallons of mineral oil each could
be located in the same room.
Changes to the exception may still result as it is currently being challenged.
(11.34 kg) for one minute without permanent deformation. The valve shall withstand a static force
of 100 lb (45.36 kg) for one minute applied normal to its longitudinal axis at the outermost extrem-
ity of the body. When specified, the venting port, on the outward side of the valve head set, shall
be protected to prevent entry of dust, moisture, and insects before and after the valve has actu-
ated; or a weather-cap-type indicator shall be provided, which will remain attached to the valve
and provide positive indication to an observer that the valve has operated. Venting and sealing
characteristics shall be as follows:
7.6 Tanks
7.6.1 The tank shall be of sufficient strength to withstand a pressure of 7 psig without perma-
nent distortion; and 15 psig without rupturing or affecting cabinet security as described in ANSI
C57.12.28-1988. A 1-inch NPT upper plug (or cap) for filling and pressure testing shall be pro-
vided in the low voltage compartment. A 1-inch NPT drain plug (or cap) for transformers rated
75-500 kVA and 1-inch NPT drain valve with built-in sampling device for transformers rated 750-
2500 kVA shall be provided in the low-voltage compartment. Suitable means for indicating the cor-
rect liquid level at 25°C shall be provided.
2.1.7 Diffusion
The high process temperature (1652°F–2372°F [900°C– 1300°C]) and use of process gases such as
phosphine, arsine, diborane, boron trichloride in a hydrogen carrier makes diffusion one of the most hazard-
ous processes in the manufacture of semiconductor devices. A vertical furnace used in the diffusion pro-
cess is shown in Figure 24 (see Data Sheet 7-7/17-12). Numerous adverse incidents have occurred and
generally business interruption was considerable since diffusion is the workhorse of the doping process.
These incidents included ignition of unreacted pyrophoric and/or flammable gases, ignition of combustible
vacuum pump oil residue and backstreaming of vacuum pump oil. A foreline trap or antibackstreaming device
should be installed between the vacuum pump and quartz tube in all diffusion furnaces where backstream-
ing is thought to be possible. This device is an optically dense, wool type filter barrier reinforced with cop-
per or stainless steel mesh. The filter will cause the oil to condense and drop back into the vacuum pump.
Fire suppression tests were conducted on wet benches placed in a mockup cleanroom facility constructed at
FM Global Research. In this facility, typical cleanroom ventilation and wet bench exhaust systems were
installed, so that typical air velocities and flow rates could be maintained in both the room and wet bench.
All fire suppression tests were conducted with the room ventilation system and wet bench exhaust system in
full operation. Three different fire suppression systems were tested: fine water spray (FWS), carbon diox-
ide (CO2), and FM-200. These suppression systems were tested with fires of different sizes placed at the
bench working surface and subsurface areas. Fire tests were also conducted with FWS in unventilated
spaces. Results of these tests were successful and formed the basis for design and installation protection cri-
teria offered for each of these systems in this data sheet.
FM Global Research does not limit vertical runs of duct to any particular length. FM Global Research limits
the height of the riser to the actual height that was tested. While most manufacturers have chosen to test
15 ft (4.6 m), several manufacturers have successfully tested risers longer than 15 ft (4.6 m) as shown in the
Approval Guide.
Compatibility of the duct system for the end use application is determined by the manufacturer of the duct sys-
tem; however, further investigation is underway into the methods used to determine the compatibility of duct
systems to the end use application. This is necessary because of the many variables and the lack of
consistent pass/fail criteria used in industry today.
While there have been no failures documented by FM Global for Approved ducts used and installed as
described in this data sheet, failures of FM Approved ducts have been reported when the duct system was
used to handle corrosive liquids or when condensate was allowed to accumulate in the duct system; fail-
ures have also been reported for duct systems installed with improperly prepared joints. In both these con-
ditions, the duct systems were being utilized outside their intended use or were not installed according to
the manufacturers’ recommendations.
Accidental releases followed by self ignition of the gas will generate a pressure rise inside the enclosure
and a localized fire that can be kept confined to the cabinet of origin by installing automatic sprinkler protection
inside the gas cabinet per section 2.2.12, Process Gas Cabinets in Data Sheet 7-7/17-12.
Gas cylinders containing silane are required by code (Uniform Fire Code and others) to be equipped with
a restrictive flow orifice (RFO) in the CGA fitting. The RFO is intended to limit the flow of gas in the event of
a failure of the pressure regulator. Current code requirements are for RFO’s with a diameter of 0.010 in.
(0.25 mm) or less.
The work conducted by FM Global Research has provided new insights on the behavior of silane and on
the RFO effects on the accidental discharge of a line. Based on the results of this work and, on the current
trend in the industry for better usage of silane, the use of RFOs with diameters of 0.020 in. (0.50 mm) is
likely in the near future.
Notes:
1. Optional step, almost all facilities purchase wafers from an outside supplier.
2. Masks may be supplied from an outside supplier.
3. Mask may be replaced with direct writing on wafers (not very common).
4. Most of the time these operations are performed at other facilities.
In addition to the production of electronic circuits, electro-optical and electro-magnetic devices are also pro-
duced. These devices are made on wafers in cleanrooms with similar processes. Photocells for convert-
ing light energy to electrical energy and sensors for measuring UV, visible, and IR electromagnetic waves
are made using the deposition, photolithography, and etching processes. Electromagnetic devices, such as
read-write heads for magnetic disc drives are also made using similar processes in cleanrooms.
Crystal production involves the growing of silicon crystals in electrically heated, argon-atmosphere vacuum
furnaces operating at a temperature above 1400°F (760°C). As with all crystal growing, a seed crystal is
required to set the process in motion. When the growing process is complete, the silicon ingot is brought to
room temperature and the seed is removed from the crystal. Years ago the diameter of the ingot was only
1/2 in. (13 mm). Six in. (150 mm) and 8 in. (200 mm) ingots are common today and 12 in. (300 mm) ver-
sions are in the development stages.
In the cut and grind operation, the ends of the polysilicon crystal are removed and the uneven exterior is
ground to achieve uniformity. The silicon ingot is then sliced into wafers. This can be done using either
multiwire saws that make numerous cuts at once, or with a diamond edge circular saw. These slice the ingot
into 14 to 30 mil (0.36 to 0.76 mm) wafers. (This is about the thickness of a business card.) About 28 wafers
are cut from each inch of the ingot.
After slicing, the wafers are lapped to remove the saw marks. The wafers are mounted to the equipment
which features an abrasive slurry on a revolving disc. An acid etch process performed in plastic wet benches
follows to remove the lap marks.
Wafers are then polished with a diamond paste to a mirror-like finish. Finally, the wafers are either given a
thin surface layer of silicon dioxide in an oxidation furnace (metal oxide semiconductor [MOS] process) or sili-
con in a epitaxial reactor (bipolar process). At this point, the wafers are ready for building the circuits on
the silicon substrate. Most chip manufacturers purchase wafers from an outside supplier, but some facili-
ties make a small portion of wafers needed for processing.
Gallium arsenide crystal is more brittle and it is more difficult to grow a single crystal than silicon; so 2 in.
(50 mm), 3 in. (75 mm), and 4 in. (100 mm) wafers are typically used. Gallium arsenide circuits are some-
times grown on germanium wafers due to the lower cost of germanium.
Mask production involves transferring a large circuit drawing to a glass plate called a mask. The mask con-
tains hundreds of exact reproductions of the original art work and is used later to recreate the pattern on
the wafer surface. Each mask contains the pattern for a single layer of the circuit, so many masks are used
to fabricate the entire integrated circuit or chip. The mask surface may be an emulsion, chrome, iron oxide
or silicon monoxide. Most masks are fabricated from chrome on glass. Two different techniques used to pro-
duce masks are known as reticle and electron beam technology.
The circuit design process starts with a determination of the functioning of the circuit. A logic diagram of the
circuit is developed and then translated to a schematic diagram which shows the location of the various com-
ponents. The circuit components are then translated to their relative final dimensions, as they will be formed
in and on the wafer surface. A sophisticated computer-aided design (CAD) system then draws a composite
picture of the circuit surface showing all of the sublayer patterns.
The reticle is a miniaturized reproduction of one layer of the circuit. The actual size of the pattern on the
reticle is normally ten times the final size (10 X) of the pattern on the wafer. A reticle is an emulsion or chrome
photo plate that is selectively exposed to light in a pattern generator. The computer tape from the digitiz-
ing operation instructs the shutter system to open and close, exposing the reticle in the exact pattern of the
original drawing.
The pattern on the reticle is transferred to the mask in the step and a repeat operation. The reticle is posi-
tioned over one corner of the photoresist coated mask blank and a light source transfers the pattern on the
reticle into the photoresist. After the first pattern is transferred, the machine ‘‘steps’’ the reticle to the next posi-
tion and repeats the pattern in the next location. This process continues until the entire mask surface is filled
with the reticle pattern.
Electron beam technology is used to make masks which produce more advanced circuits. An electron beam
writer is similar to a scanning electron microscope. The coated mask is placed in a vacuum chamber and
an electron beam directed at it. The pattern information stored on the tape at the digitizing operation is used
to direct the electron beam to the correct locations to expose the photoresist. The pattern is written onto
the mask without a reticle.
The fabrication or main part of the process involves repeated steps of photoresist, masking, etching, doping,
and deposition. These processes are typically performed in cleanrooms. Photoresist and its developer are
the largest volume solvents within the fabrication area. Negative photoresist is a photosensitive polymer sus-
pended in a flammable organic solvent base such as xylene or toluene. It is used to coat the wafer in prepa-
ration for transferring the pattern of the circuit from the mask to the wafer. The wafers are coated by
dispensing a small quantity of photoresist on the wafer and rapidly rotating on a ‘‘spinner’’ which spreads a
thin uniform layer. Photoresist materials are classified as either negative or positive resists, depending on
whether the solubility in the developer decreases (negative) or increases (positive) upon exposure to a UV
light source. Since photoresist is sensitive to light, it is shipped, stored and dispensed to the areas in brown
glass or plastic bottles.
Photoresist adjuncts, a variety of chemical liquids and gases, are used to promote the adhesion of the photo-
resist coating to the wafer. Hexamethyldisilazane (HMDS) is the most widely used chemical for adhesion
and is spun onto the wafer surface prior to photoresist application.
After the wafers are coated with photoresist, they are ‘‘soft baked’’ to evaporate a portion of the solvents in
the photoresist. Methods used to soft bake include hot plates and the following different type ovens: con-
vection, vacuum, moving belt IR, microwave and conduction belt. After the baking has been concluded, the
actual photomask process takes place.
Photomasking is a process of alignment and exposure. The different types of equipment used for this pro-
cess can vary in size, overall appearance, method of operation and equipment cost. This equipment includes
contact aligners, projection aligners, and wafer steppers. The function is the same in that the wafer is placed
onto this machine and a specific patterned ‘‘mask plate’’ is placed over the wafer. The wafer is then aligned
with the mask plate, and then exposed through the action of the shutter of the machine opening to allow ultra-
violet light to hit the unmasked portion of the wafer.
After the wafer has been aligned and exposed, the next step is developing. In developing a wafer, a machine
similar to a ‘‘spinner’’ is used. The developing is done by chemicals which are sprayed down onto the wafer.
This spray washes away the nonexposed resist (areas where the light was not allowed to pass through the
mask plate) while the exposed or ‘‘polymerized’’ resist remains. The preferred developing chemical for nega-
tive photoresist is xylene. A Stoddard solvent may also be used in certain cases. Positive photoresist is devel-
oped in an alkaline solution, such as potassium hydroxide or sodium hydroxide.
Other flammable solvents are also used in the wafer fabrication process. Butyl acetate and isopropyl alco-
hol will be used as washes for wafers after they have been developed with negative resist. D.I. water is more
commonly used with positive photoresist as a post develop wash.
Etching removes layers of silicon dioxide, metals and polysilicon as well as resists, according to desired
patterns delineated by the resist. The two major categories of etching are wet and dry chemical. Wet etch-
ing is predominantly used and involves solutions containing the etchants (usually an acid mixture) at the
desired strengths, which react with the materials to be removed. Plastic wet benches and plastic fume exhaust
ductwork are typically used in wet etching operations (Figures 17 and 18 of Data Sheet 7-7/17-12). Dry etch-
ing involves the use of reactive gases (hydrogen chloride, ammonia, etc.) under vacuum in a highly ener-
gized chamber, which also removes the desired layers not protected by resist.
To form the junctions where current will flow, a controlled number of impurities or dopants must be intro-
duced into a selected region of the wafer either by diffusion or ion implantation. Diffusion is a high tempera-
ture (1652°F to 2372°F [900°C to 1300°C]) process in which certain chemicals (dopants) are introduced into
the surface layer of the semiconductor material to change its electrical characteristics. Diffusion is the most
established method of applying dopant material. Ion implantation is a technique for doping impurity atoms into
an underlying substrate by accelerating the selected dopant ion towards the silicon target through an elec-
trical field. Ion implantation is often preferred over standard diffusion methods because it is more precise,
faster and less expensive. Annealing usually is required following ion implantation because of the struc-
tural damage caused by bombardment of the substrate by the accelerated ions.
The need for annealing after ion implantation led to the development of a technology called Rapid Thermal
Processing (RTP). This process, which takes place in seconds, eliminated the need for a minutes-long
process in a tube furnace, which had undesirable side effects of migration of dopant atoms within the wafer.
Also, every time a wafer is heated near diffusion temperatures and then cooled down, crystal dislocation
forms, which can result in circuit failures. In the single wafer RTP tool, radiation heating (usually from tung-
sten halogen lamps) is very rapid and the body of the wafer never comes up to temperature. Annealing can
take place without undesirable side effects. The trend to small feature sizes on wafers has also lead to thin-
ner layers. Thermally grown gate oxide layers now may be less than 100 Angstroms thick. RTO ( Rapid Ther-
mal Oxidation) tools are similar to the RTP annealing tools but have an oxygen atmosphere in the chamber
rather than an inert gas. RTP technology is now used in various oxide, nitride and silicon layer processes.
Deposition is the process of placing additional layers onto the wafer surface, either by epitaxial or chemical
vapor deposition (CVD). Chemical vapor deposition is the process of forming a thin film on a substrate by
the chemical reaction of various gases. CVD is usually promoted by heating the substrate, either at atmo-
spheric pressure, or low pressure (LPCVD). Epitaxy is the process of depositing a crystalline layer having the
same structure as the substrate. Epitaxy represents a special form of chemical vapor deposition. Often,
epitaxial layers are grown with intentionally added impurities such as boron or phosphorus. These change
the electrical conductivity of the crystalline silicon. Some of the more common process reactions can be found
in Table 6 of Data Sheet 7-7/17-12.
The photoresist, masking, etching, doping and deposition processes are repeated many times until the com-
plete circuit is produced.
After the final diffusion step, the devices which have been fabricated into the silicon wafer must be con-
nected together to perform circuit functions. This process is known as metalization. Metalization provides a
means of wiring or interconnecting the uppermost layers of integrated circuits by depositing complex patterns
of conductive material, which route electrical energy within the circuits. To do this, a conductive metal is either
sputtered or evaporated over the front of the wafer. A photoresist pattern is then aligned over the metal and
some of it is etched away, leaving the desired metal coverage. The most common metals used for metal-
ization are: aluminum, nickel, chromium, gold, copper, silver, titanium, tungsten and platinum.
The final step in wafer form of integrated circuit manufacturing is testing. During the electrical test, (e.g.,
‘‘die sort,’’ ‘‘wafer sort,’’ ‘‘wafer probe’’), each circuit or die is tested for its ability to perform the operations
for which it was designed. As each die or chip is tested, a computer records certain information about it. If a
die is not acceptable, that is, if it fails any one or more of the tests, a small droplet of ink is automatically
placed on the die so that when the wafer is separated into individual die the bad or ‘‘inked’’ die can be
discarded.
The air flow velocity in the cleanroom ranges from 40 to 100 ft/min (0.20 to 0.51 m/sec). Typical air flow vol-
umes for new cleanrooms, whether recirculated at work stations, modules, or large global air systems, range
from about 20 to 50 cfm/ft2 (0.57 to 1.4 m3/min) of cleanroom. This assumes that 60 percent of the clean-
room is a service corridor with less stringent requirements.
The method of returning the air from the cleanroom to the recirculation fans is accomplished by sidewall
vents (Figs. 2 and 3 of Data Sheet 7-7/17-12), a perforated raised floor (Fig. 4 of Data Sheet 7-7/17-12),
or a perforated raised floor opening into a basement plenum (Fig. 5 of Data Sheet 7-7/17-12).
Sidewall return refers to the use of openings in the walls of the work area as the path for air return. A perfo-
rated raised floor is from 1 to 4 ft (0.3 to 1.2 m) above the structural floor and forms a plenum underneath
the walking level for air return. Finally, perforations in the structural floor allows air flow directly to the base-
ment which is used as an air plenum.
The air supplied to the cleanroom is usually a mixture of recirculated air and make-up air which compen-
sates for leakage and exhaust losses. Since the recirculated air is cleaner and closer to the temperature and
humidity requirements, a high ratio (80 to 95 percent) of recirculated-to-make-up air is provided.
The concept of laminar air flow is used in nearly all semiconductor cleanrooms. Laminar flow occurs when
air is made to flow in unidirectional layers when air flow velocities are maintained above 70 ft/min
(0.36 m/sec). As the air flows from the supply side (usually the ceiling) to the return side (either a perfo-
rated floor or sidewall vent), particulate matter is ‘‘washed’’ away in a shower of air.
The laminar flow cleanroom requires an air flow rate between 70 to 110 ft/min (0.36 to 0.56 m/sec) The aver-
age Class 100 room will operate at 90 ft/min (0.46 m/sec). If this room has a 9-ft high (2.7 m) ceiling, ten
air changes per minute or 600 per hour would occur.
The cleanroom is typically kept under a positive pressure in the range of about 0.15 in. W.G. (water gauge)
(0.04 kPa). This is done because if there is any air leakage, or if a door or other passage is opened, the
exchange of air will be from the inside to the outside. If outside air were to rush in, it would bring millions of
airborne contaminates with it.
In a vertical laminar flow (VLF) work station or hood (Fig. 7 and Figs. 1 through 4 of Data Sheet 7-7/17-12),
the air enters from above and moves vertically downward over the work area. These stations are used in recir-
culating applications, or where fumes are generated, and must be removed and exhausted. The use of a
VLF work station can reduce the size of the central air system and simultaneously provide a source of high
velocity, filtered air to the work area.
In the past, as more critical particulate control became necessary, the VLF hood approach had several draw-
backs. But this problem was solved by dividing the fabrication area into separate tunnels or bays. Today,
HEPA filters built into the ceilings serve the same purpose.
Fig. 7. Various arrangements of a wet bench and associated fume exhaust ductwork.
High Efficiency Particular Air (HEPA) filters are built into an extended surface configuration by folding filter
media into pleats and housing it in a frame. The media is a matte of glass fibers held together with binder
resins which filter over 99 percent of the particles attempting to pass through it. The combustibility of the HEPA
and ULPA (ultrahigh particulate air) filter modules varies depending on the media, binder resins, and frame
materials.
The pressure drop through a HEPA filter is typically 0.5 in. W.G. After extended use, depending upon the clean-
liness of the air passing through the filter and the amount of prefiltration used, the pressure drop will increase
to 1 in. W.G. and beyond and must be replaced. In the event of a cleanroom fire, if the HEPA filters are
exposed to fire products of combustion, the filters might experience an unacceptable pressure drop and need
to be replaced.
3.3.3 Reprocessors
Reprocessors are on-site distillation systems which enable wafer fabrication facilities to recycle various liquid
chemicals. Sulfuric and hydrofluoric acid are the main acids recycled due to their ultra high purity require-
ments, large consumption volumes, high cost and disposal challenge. Isopropyl alcohol is also being recycled
for these reasons.
The reprocessors consist of self-contained distillation systems which concentrate and purify the used liquid
before returning it to the distribution system.
Mini-environment enclosures will most always create shielded areas which are not adequately protected by
cleanroom sprinkler systems. The protection guidelines developed by FM Global for specific tools and equip-
ment address the need to provide internal protection to mitigate the shielding problem when a mini-
environment enclosure is provided around that tool.
easily removable memory boards. Losses of $15,000 were a daily occurrence in many cities; some of the larg-
est losses reached in excess of $500,000.
Typically, these codes have separate chapters or articles that specifically govern the semiconductor industry.
Examples: in the UBC a special occupancy class H-6 has been designated for the semiconductor indus-
try; in the UFC, Article 51 and in the BOCA Fire Code, Chapter 15 address the semiconductor industry
specifically.
The scope statements of these model codes illustrate the difference between them and FM Global stan-
dards. The codes are designed to provide minimum standards primarily focused on safeguarding the life and
health of people while FM Global provides property damage loss prevention and control engineering.
A fire incident which resulted in no loss of life or injuries might be acceptable in a semiconductor fabricat-
ing facility from a code standpoint. However, that same incident, which might only have opened two auto-
matic sprinkler heads, could be a 20 or 30 million-dollar loss and totally unacceptable from a property
conservation viewpoint.
A brief look at the code requirements versus FM Global standards for the semiconductor industry illustrates
the following differences.
1. It is only since the 1994 UFC that a 0.010 in. (0.254 mm) RFO is required. FM Global has recom-
mended the RFO, automated cylinder valves, and high ventilation airflows since 1990.
2. Fire codes require automatic sprinklers in combustible ducts 10 in. (0.25 m) diameter and larger with an
exception for 12 ft (3.6 m) of ductwork below the ceiling. FM Global recommends (1) using ducts not need-
ing sprinkler protection; (2) not using ducts of certain materials such as PVC or polypropylene and sprin-
kler protection in all combustible ducts.
3. Smoke/contaminant control systems are not addressed as required in the model codes but are recom-
mended for all semiconductor fabricating areas by FM Global.
4. Automatic sprinkler protection for the horizontal surface of a wet bench plus within 2 ft (0.6 m) of the duct
connection to the bench is the requirement of the UFC. FM Global recommends protection for the surface
and all interior compartments with a detector-activated suppression system to limit the loss to far less than
would be expected in a wet bench fire controlled by sprinkler protection alone.
To overcome the interim period until the standards are approved, CEN has decided to publish an European
Prestandard ENV 1631 Cleanroom Technology — Design construction and operation of cleanrooms and
clean airdevices, which will be automatically withdrawn once the ISO standards 14644-4 and -5 are approved
and published.
Table 9. Selected airborne particulate cleanroom classes for cleanrooms and cleanzones defined by ISO 14644-1
Maximum concentration limits (particles/m3 of air) for particles equal to and larger than the considered
sizes (in nanometers) shown below (concentration limits are calculated in accordance with formula 1)
ISO Classification Number (N) 100 nm 200 nm 300 nm 500 nm 1000 nm 5000 nm
ISO Class 1 10 2
ISO Class 2 100 24 10 4
ISO Class 3 1000 237 102 35 8
ISO Class 4 10000 2370 1020 352 83
ISO Class 5 100000 23700 10200 3520 832 29
ISO Class 6 1000000 237000 102000 35200 8320 293
ISO Class 7 352000 83200 2930
ISO Class 8 3520000 832000 29300
ISO Class 9 35200000 8320000 293000
Deionized Water—Water which has had all charged particles removed. Commonly called ‘‘D.I. water,’’ it is
used throughout the entire manufacturing process.
Deposition—The depositing or laying down of various chemicals on wafers, generally done in a high
temperature furnace or evaporator.
Developer—Chemical used to remove areas defined in the masking and exposure step of wafer fabrication.
DIE—See Chip.
Diffusion—The fab process whereby high temperature furnaces are used to drive dopant material into the
wafer.
DIP (Dual In-line Package)—A rectangular circuit package, with leads coming out of the long sides and
bent down to fit onto a socket.
Dopant—Chemical ‘‘impurities’’ used to regulate the current flow in integrated circuit junctions. Usually put
on the wafer via furnaces, implants, or CVD systems and later diffused further into the wafer by heat.
Dry Etch—Generally used in place of the acid bathing technique to produce more uniform pattern definition,
particularly with smaller geometries, as is necessary for VLSI processing.
Emergency Shut Off Valve (ESOV)—A valve located in the gas piping train, usually close to the cylinder
CGA fitting, which can be closed either automatically or manually in response to a gas emergency. For
example, automatic closure might result from a signal from the gas monitoring system; manual closure can be
done from the gas cabinet EMO button.
EPI—(i.e. epitaxy)—A special process for growing additional layers of silicon on wafers. Usually either silane
or silicon tetrachloride is used at a high temperature in a reactor.
Evaporation—The vaporizing of a material such as aluminum or gold and subsequent depositing of the
vapor on the wafers.
Expose—In masking after proper alignment of mask to wafer, light is allowed to activate or polymerize the
photoresist on the wafer much like exposing film in a camera.
FAB—Fabrication i.e., wafer fabrication area is called FAB or ‘‘Wafer fab.’’
FET (Field-Effect Transistor)—A unipolar transistor consisting of a source, gate and drain, whose action
depends on the flow of majority carriers past the gate from source to drain.
Fume Scrubber—Equipment used to clean the fumes which evolve during the wafer fabrication process. Usu-
ally, the exhaust hood, furnace exhaust, etc. in the wafer fabrication process are vented to a fume scrubber.
The scrubber is required by the environmental authorities.
Furnace—Generally refers to high temperature cylinders used for depositions and diffusions in wafer fab.
Crystal growing machines are also referred to as furnaces.
Glassification—Process used to place an environmentally safe protective coating on the completed semi-
conductor. This hard surface is the final process before the individual chips are cut from the silicon wafers and
tested for operational capabilities.
Hard Bake—Generally, in masking, the baking of wafers at about 150°C (302°F) to remove moisture and
provide for better adhesion of the photoresist after develop and prior to etch.
HPM—Hazardous Production Material—A solid, liquid or gas that has a degree of hazard ranking in health,
flammability or reactivity of 3 or 4 as ranked by Uniform Fire Code Standard 79-3 and which is used directly
in research, laboratory or production processes which have, as their end product, materials which are not
hazardous.
HEPA Filter—High Efficiency Particulate Air Filter capable of filtering out 99.97 percent of particles greater
than 0.3 microns in diameter.
Integrated Circuit (IC)—An array of transistors and other components on a piece of semiconductor material.
Ion Implantation—A process of introducing charged dopant ions into the semiconductor. These ions, usu-
ally boron or phosphorus, are accelerated and driven into the surface of the semiconductor wafer.
Junction—The interface at which the conductivity type of a circuit material changes from P-type to N-type
or vice versa.
Jungle—Generally, the entire collection of tubes, lines, bubblers, injectors, etc. found at the back end of
a diffusion or deposition system. Also called a source cabinet.
Laminar Flow Hoods—The hoods used in cleanrooms where it is important to maintain laminar airflow
characteristics throughout a given space.
Lapping—Process of removing the saw marks on the raw wafers once they are sliced from the polysilicon
ingot.
LPCVD—Low Pressure Chemical Vapor Deposition (Furnace).
Manufacturing Electron Beam Exposure System (MEBES)—An electron beam lithography machine used
to make masks. The circuit design is programmed into the MEBES machine. The MEBES reduces the cir-
cuit pattern size to that of a chip and transfers this design onto the master mask. This design is duplicated
many times to form a grid on the master mask. This mask provides the basic pattern which is exposed onto
the silicon wafer.
Mask—A glass plate covered with an array of patterns used on the photo-masking process. Each pattern con-
sists of opaque and clear areas that respectively prevent or allow light to pass. The mask surface may be
emulsion, chrome, iron oxide, silicon, or a number or other materials.
Masking—The fab process whereby each layer of the process is photographically transposed onto the wafer.
MBE—Molecular Beam Epitaxy. An evaporation rather than a CVD process. An electron beam is directed
into the center of the target material, which it heats to the liquid state. In this state, atoms evaporated out
of the material, exit the cell through an opening, and deposit on the wafers. MBE has found production use
in the fabrication of special microwave devices and for compound semiconductors such as gallium arsenide.
Micron—Equal to one millionth of a meter. Used in measuring thickness of material or line width at various
steps of processing.
Microprocessors—A single semiconductor device which carries out the processing tasks in a digital system.
Its development made the microcomputer possible. A microprocessor incorporates both the arithmetic logic
unit and the control unit—components previously requiring separate dedicated devices.
Mil—Equal to 0.001 in. (0.03 mm). Used in measuring thickness and width at various steps of processing.
Mini-environment—An environment that maintains wafer cleanliness by storing, transporting, and loading or
unloading wafers in small, clean enclosures.
MOCVD—Metal Organic Chemical Vapor Deposition, one of the latest options for CVD of compound mate-
rials. A Group III halide (gallium) is formed in the hot zone and the gallium arsenide compound is depos-
ited in the cold zone. In the metallorganic process for gallium arsenide, trimethylgallium is metered into the
reaction chamber along with arsine to form gallium arsenide.
MOS—Metal Oxide Semiconductor.
MOSFET—Metal Oxide Semiconductor Field Effect Transistor.
Nitride—(Si3N4) Short for silicon nitride, used to form an insulation layer on a circuit.
Optoelectronics—The technology which mixes solid state electronics and optics.
Organometallic Compounds—Organic compounds in which metal atoms have replaced one or more hydro-
gen atoms. The hazards vary, but most of the materials are flammable liquids or solids. Most are very reac-
tive and some will react with air or moisture at room temperature. Examples of some organometallic
compounds include trimethylaluminum, diethylzinc, and trimethylgallium.
Oxidation—The process which combines oxygen and heat with a silicon wafer in a furnace to produce a
layer of silicon dioxide (‘‘oxide’’). Also done in a CVD process using silane.
Oxide—Silicon dioxide. Grown on a wafer, oxide is used as a deterrent to dopant penetration in deposition
and diffusion processes. Also used as part of the structure of the circuit or as a final protective layer (glass).
Package—The finished integrated circuit unit which consists of the chip fastened to a frame inside a ceramic
or plastic case whose metal leads can be inserted into printed circuit boards. Can also refer to the case only.
Passivation—Usually a silicon dioxide or silicon nitride layer put over an existing layer of the wafer to protect
against moisture, contamination and abrasion.
Pass-through—An enclosure installed in a wall with a door on each side that allows chemicals, production
materials, equipment and parts to be transferred from one side of the wall to the other.
Pattern Generator—Optical or E-Beam tool used to make the mask plates or reticles.
PECVD—Plasma Enhanced Chemical Vapor Deposition.
Pellicle—A protective film covering on a frame adhered to a mask plate which keeps contaminants off the
mask surface.
Photoresist—A light-sensitive, frequently flammable liquid which is sprayed on the wafer, exposed and devel-
oped to make the circuit image during the wafer fabrication process. Similar to film in an ordinary camera
in its sensitivity to light.
Plasma—A high energy gas made up of ionized particles.
Plasma Etcher—A machine in which a high energy RF field excites the gas molecules in the chamber to
a high level causing a reaction in which unprotected sections of an oxide layer are removed.
Plasma Etching—An etching process which accomplishes results similar to the chemical etch mechanism
reaction using an etching gas instead of a wet chemical.
Polishing—The process whereby a mirror-like finish is put on raw wafers after slicing.
Poly—Polycrystalline silicon. Usually grown in layers epitaxially to form part of the circuit structure. Also the
raw material for the melt for crystal growth.
Projection/Promixity—Masking exposure methods in which the wafer and mask plate have no contact,
thus lengthening the mask usage due to less contamination of the mask plate.
Puller—Furnace for growing silicon crystals. Refers to the process of pulling the crystal out of the molten
silicon.
Pyrophoric—A substance which ignites spontaneously in air below 130°F (54°C).
RCA Clean—A multiple-step process to clean wafers before oxidation; named after RCA, the company that
developed the procedure. Chemicals used include mixtures of water, hydrogen peroxide and ammonium
hydroxide (step 1) or hydrochloric acid (step 2).
Reactive Ion Etching (RIE)—An etching process that combines plasma and ion beam removal of the sur-
face layer. The etchant gas enters the reaction chamber and is ionized. The individual molecules acceler-
ate to the wafer surface. At the surface, the top layer removal is achieved by the physical and chemical
removal of the material.
Reticle—A miniature reproduction of one layer of a circuit drawing on an emulsion or chrome covered glass
plate. Typically 5 x or 10 x in size it will be reduced and reproduced many times on a mask blank.
RTO (Rapid Thermal Oxidation)—An RTP technology used to grow very thin (usually less than 100
Angstorms) MOS gate oxide layers.
RTP (Rapid Thermal Processing)—A process usually using high intensity tungsten halogen lamps to heat
and cool a wafer in seconds.
Seed—In crystal growing a piece of single-crystal structured silicon which upon contact with the melt (molten
poly-silicon) starts a crystal or ingot to be grown which has same single-crystal structure as that of the seed.
SEM—Scanning Electron Microscope. Used in examining portions of circuit by allowing the viewer to see
an image as much as 15,000 times its actual size.
Semiconductor—An element such as silicon or germanium intermediate in electrical conductivity between
the conductors and the insulators.
Slicing—The cutting of a silicon crystal in a saw in order to make wafers on which ICs will be made.
Soft Baking—A heating process used to evaporate a portion of the solvents in resist. The term ‘‘soft’’
describes the still soft resist after baking. The solvents are evaporated to achieve two results: to avoid reten-
tion of the solvent in the resist film and to increase the surface adhesion of the resist to the wafer.
Spin—The operation and development in a spinner machine where photoresist or developer is applied to
a wafer and rotated at high speed so that a uniform film coating results.
Sputter—Method of depositing various types of thin metal films on wafers by ion bombardment of a target.
Standard Mechanical Interface (SMIF)—A system that allows the mating of portable clean wafer boxes
(called pods) to the clean microenvironment loading stations of process tools.
Step & Repeat—In making mask plates a step-and-repeat camera (‘‘stepper’’) is used to transform the pat-
tern image of the reticle onto the surface of the plate. In some fab processing, a stepper is used to project
the reticle’s image directly onto the resist spun wafer and does not employ a mask plate (also called DSW for
Direct-Step-On-The-Wafer).
Strip—In fab, refers to the stripping of the photoresist after etch usually in a wet chemical bath or in a plasma
chamber.
Substrate—The silicon wafer.
Tape Automatic Bonding (TAB)—Chip-to-package connection process in which the package leads are
formed on a flexible tape and all the lead fingers are bonded to the chip in one action.
Tetraethylorthosilicate (TEOS)—A chemical source for the deposition of silicon dioxide. A combustible liquid
(flash point 125°F [52°C]) replacement for silane.
Tool—Any device, storage container, work station, or process machine used in a cleanroom.
Torr—In vacuum systems the remaining pressure inside the chamber after pumpdown is a measure of
atmospheric pressure expressed in Torr (Torr = 1/760 of atmospheric pressure).
Transition Piece—That portion of a work station exhaust plenum attached to the rear of a work station.
This portion of the plenum is connected to the fume exhaust branch duct.
ULPA Filter—Ultrahigh-Efficiency Particulate Air Filter, capable of filtering out 99.999 percent of particles
greater than 0.3 microns in diameter.
VLF—Vertical Laminar Flow.
VLSI (Very Large Scale Integration)—A chip manufacturing process which enables a high density of
transistors and circuits typically 100,000 to 1,000,000 devices per chip.
Wafer—The silicon disc sliced from a crystal on which integrated circuits are manufactured. Also called a
substrate or starting material.
Wafer Box—A plastic box with a hinged opening top used to hold carriers with wafers during non-processing
times.
Wafer Fab—The area in which circuits are manufactured, usually consisting of masking, diffusion, deposition,
and other operations which will transform a polished wafer into hundreds of chips.
Wafer Sort—The step after wafer fabrication during which the electrical parameters of integrated circuits
are tested for functionality. Probes contact the pads of the circuit to conduct the test leading to the name
‘‘prober’’ for the equipment that performs electrical tests on each die site of completed wafers.
Wire Bonding—An assembly step in which thin gold or aluminum wires are attached between the die bonding
pads and the lead connections in the package.
Yield—The amount of good products compared to the total possible good products, i.e., on a wafer which
has 100 possible chips and 65 are found to be good, then the yield = 65 percent. Or if a ‘‘run’’ of wafers has
50 wafers to start and 41 wafers are finished, the run has a yield of 82 percent.
6.0 BIBLIOGRAPHY
The following codes, standards and publications provide additional information:
BOCA National Fire Prevention Code, 1993, Chapter 15: Hazardous Production Material Facilities
National Fire Protection Association (NFPA)
• Standard No. 45-1986 Edition: Fire Protection for Laboratories Using Chemicals
• Standard No. 90A-1985 Edition: Installation of Air Conditioning and Ventilation Systems
• Standard No. 91-1983 Edition: Blower and Exhaust Systems for Dust, Stock and Vapor Removal or
Conveying
• Standard No. 318-1998: Protection of Cleanrooms
Pletsch, William, Integrated Circuits—Making the Miracle Chip, California: Pletsch & Associates, 1985
Semiconductor Equipment and Materials International, SEMI S2-93, Safety Guidelines for Semiconductor
Manufacturing Equipment.
Uniform Fire Code, 1997
• Article 51—Semiconductor Fabrication Facilities
• Article 74—Compressed Gases
• Article 80—Hazardous Materials
Van Zant, Peter. Microchip Fabrication: A Practical Guide to Semiconductor Processing, Third Edition, New
York: McGraw-Hill Publishing Company, 1997