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Ultraprecision, Low Noise, 2.048 V/2.

500 V/
3.00 V/5.00 V XFET® Voltage References
ADR420/ADR421/ADR423/ADR425
FEATURES PIN CONFIGURATION
Low noise (0.1 Hz to 10 Hz) TP 1 ADR420/ 8 TP
ADR420: 1.75 μV p-p VIN 2 ADR421/ 7 NIC
ADR423/
ADR421: 1.75 μV p-p NIC 3 ADR425 6VOUT
ADR423: 2.0 μV p-p TOP VIEW
GND 4 (Not to Scale) 5 TRIM
ADR425: 3.4 μV p-p

02432-001
Low temperature coefficient: 3 ppm/°C NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
Long-term stability: 50 ppm/1000 hours
Figure 1. 8-Lead SOIC, 8-Lead MSOP
Load regulation: 70 ppm/mA
Line regulation: 35 ppm/V GENERAL DESCRIPTION
Low hysteresis: 40 ppm typical The ADR42x are a series of ultraprecision, second generation
Wide operating range eXtra implanted junction FET (XFET) voltage references
ADR420: 4 V to 18 V featuring low noise, high accuracy, and excellent long-term
ADR421: 4.5 V to 18 V stability in SOIC and MSOP footprints.
ADR423: 5 V to 18 V
Patented temperature drift curvature correction technique and
ADR425: 7 V to 18 V
XFET technology minimize nonlinearity of the voltage change
Quiescent current: 0.5 mA maximum
with temperature. The XFET architecture offers superior
High output current: 10 mA
accuracy and thermal hysteresis to the band gap references. It
Wide temperature range: −40°C to +125°C
also operates at lower power and lower supply headroom than
APPLICATIONS the buried Zener references.
Precision data acquisition systems The superb noise and the stable and accurate characteristics
High resolution converters of the ADR42x make them ideal for precision conversion
Battery-powered instrumentation applications such as optical networks and medical equipment.
Portable medical instruments The ADR42x trim terminal can also be used to adjust the out-
Industrial process control systems put voltage over a ±0.5% range without compromising any
Precision instruments other performance. The ADR42x series voltage references
Optical network control circuits offer two electrical grades and are specified over the extended
industrial temperature range of −40°C to +125°C. Devices have
8-lead SOIC or 30% smaller, 8-lead MSOP packages.
ADR42x PRODUCTS
Table 1.
Initial Accuracy
Model Output Voltage, VOUT (V) mV % Temperature Coefficient (ppm/°C)
ADR420 2.048 1, 3 0.05, 0.15 3, 10
ADR421 2.50 1, 3 0.04, 0.12 3, 10
ADR423 3.00 1.5, 4 0.04, 0.13 3, 10
ADR425 5.00 2, 6 0.04, 0.12 3, 10

Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2001–2007 Analog Devices, Inc. All rights reserved.
ADR420/ADR421/ADR423/ADR425

TABLE OF CONTENTS
Features .............................................................................................. 1 Basic Voltage Reference Connections ..................................... 16
Applications....................................................................................... 1 Noise Performance..................................................................... 16
Pin Configuration............................................................................. 1 Turn-On Time ............................................................................ 16
General Description ......................................................................... 1 Applications..................................................................................... 17
ADR42x Products............................................................................. 1 Output Adjustment .................................................................... 17
Revision History ............................................................................... 2 Reference for Converters in Optical Network Control
Specifications..................................................................................... 3 Circuits......................................................................................... 17

ADR420 Electrical Specifications............................................... 3 A Negative Precision Reference Without Precision Resistors


....................................................................................................... 17
ADR421 Electrical Specifications............................................... 4
High Voltage Floating Current Source .................................... 18
ADR423 Electrical Specifications............................................... 5
Kelvin Connections.................................................................... 18
ADR425 Electrical Specifications............................................... 6
Dual-Polarity References........................................................... 18
Absolute Maximum Ratings............................................................ 7
Programmable Current Source ................................................ 19
Thermal Resistance ...................................................................... 7
Programmable DAC Reference Voltage .................................. 19
ESD Caution.................................................................................. 7
Precision Voltage Reference for Data Converters.................. 20
Pin Configurations and Function Descriptions ........................... 8
Precision Boosted Output Regulator ....................................... 20
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 21
Terminology .................................................................................... 15
Ordering Guide .......................................................................... 22
Theory of Operation ...................................................................... 16
Device Power Dissipation Considerations.............................. 16

REVISION HISTORY
6/07—Rev. G to Rev. H 1/03—Rev. B to Rev. C
Changes to Table 2............................................................................ 3 Changed Mini_SOIC to MSOP ........................................Universal
Changes to Table 3............................................................................ 4 Changes to Ordering Guide .............................................................4
Changes to Table 4............................................................................ 5 Corrections to Y-axis labels in TPCs 21 and 24 ............................9
Changes to Table 5............................................................................ 6 Enhancement to Figure 13 ............................................................ 15
Updated Outline Dimensions ....................................................... 21 Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 22
3/02—Rev. A to Rev. B
6/05—Rev. F to Rev. G Edits to Ordering Guide ...................................................................4
Changes to Table 1............................................................................ 1 Deletion of Precision Voltage Regulator section........................ 15
Changes to Ordering Guide .......................................................... 22 Addition of Precision Boosted Output Regulator section ....... 15
Addition of Figure 13..................................................................... 15
2/05—Rev. E to Rev. F
Updated Format..................................................................Universal 10/01—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 21 Addition of ADR423 and ADR425 to
Changes to Ordering Guide .......................................................... 22 ADR420/ADR421...............................................................Universal

7/04—Rev. D to Rev. E 5/01—Revision 0: Initial Version


Changes to Ordering Guide ............................................................ 5

3/04—Rev. C to Rev. D
Changes to Table I ............................................................................ 1
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 16

Rev. H | Page 2 of 24
ADR420/ADR421/ADR423/ADR425

SPECIFICATIONS
ADR420 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.045 2.048 2.051 V
B Grade 2.047 2.048 2.049 V
INITIAL ACCURACY VOUTERR
A Grade −3 +3 mV
−0.15 +0.15 %
B Grade −1 +1 mV
−0.05 +0.05 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V, 10 35 ppm/V
−40°C < TA < +125°C
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA, 70 ppm/mA
−40°C < TA < +125°C
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 60 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA

Rev. H | Page 3 of 24
ADR420/ADR421/ADR423/ADR425
ADR421 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.

Table 3.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.497 2.500 2.503 V
B Grade 2.499 2.500 2.501 V
INITIAL ACCURACY VOUTERR
A Grade −3 +3 mV
−0.12 +0.12 %
B Grade −1 +1 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V, 10 35 ppm/V
−40°C < TA < +125°C
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA, 70 ppm/mA
−40°C < TA < +125°C
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 80 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA

Rev. H | Page 4 of 24
ADR420/ADR421/ADR423/ADR425
ADR423 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.

Table 4.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.996 3.000 3.004 V
B Grade 2.9985 3.000 3.0015 V
INITIAL ACCURACY VOUTERR
A Grade −4 +4 mV
−0.13 +0.13 %
B Grade −1.5 +1.5 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V, 10 35 ppm/V
−40°C < TA < +125°C
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA, 70 ppm/mA
−40°C < TA < +125°C
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 2 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 90 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA

Rev. H | Page 5 of 24
ADR420/ADR421/ADR423/ADR425
ADR425 ELECTRICAL SPECIFICATIONS
VIN = 7.0 V to 15.0 V, TA = 25°C, unless otherwise noted.

Table 5.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 4.994 5.000 5.006 V
B Grade 4.998 5.000 5.002 V
INITIAL ACCURACY VOUTERR
A Grade −6 +6 mV
−0.12 +0.12 %
B Grade −2 +2 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VO 2 V
LINE REGULATION ∆VO/∆VIN VIN = 7 V to 18 V, 10 35 ppm/V
−40°C < TA < +125°C
LOAD REGULATION ∆VO/∆IL IL = 0 mA to 10 mA, 70 ppm/mA
−40°C < TA < +125°C
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 3.4 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 110 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VO 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA

Rev. H | Page 6 of 24
ADR420/ADR421/ADR423/ADR425

ABSOLUTE MAXIMUM RATINGS


These ratings apply at 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 6. θJA is specified for the worst-case conditions, that is, θJA is
Parameter Rating specified for devices soldered in the circuit board for surface-
mount packages.
Supply Voltage 18 V
Output Short-Circuit Duration to GND Indefinite Table 7.
Storage Temperature Range −65°C to +150°C Package Type θJA Unit
Operating Temperature Range −40°C to +125°C 8-Lead MSOP (RM) 190 °C/W
Junction Temperature Range −65°C to +150°C 8-Lead SOIC (R) 130 °C/W
Lead Temperature (Soldering, 60 sec) 300°C

ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. H | Page 7 of 24
ADR420/ADR421/ADR423/ADR425

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TP 1 ADR420/ 8 TP

VIN 2 ADR421/ 7 NIC


ADR423/
NIC 3 ADR425 VOUT
6
TOP VIEW
GND 4 (Not to Scale) 5 TRIM

02432-002
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)

Figure 2. 8-Lead SOIC, 8-Lead MSOP Pin Configuration

Table 8. Pin Function Descriptions


Pin No. Mnemonic Description
1, 8 TP Test Pin. There are actual connections in TP pins, but they are reserved for factory testing purposes. Users should not
connect anything to TP pins; otherwise, the device may not function properly.
2 VIN Input Voltage.
3, 7 NIC No Internal Connect. NICs have no internal connections.
4 GND Ground Pin = 0 V.
5 TRIM Trim Terminal. It can be used to adjust the output voltage over a ±0.5% range without affecting the temperature
coefficient.
6 VOUT Output Voltage.

Rev. H | Page 8 of 24
ADR420/ADR421/ADR423/ADR425

TYPICAL PERFORMANCE CHARACTERISTICS


2.0495 5.0025

2.0493 5.0023

2.0491 5.0021

2.0489 5.0019

2.0487 5.0017
VOUT (V)

VOUT (V)
2.0485 5.0015

2.0483 5.0013

2.0481 5.0011

2.0479 5.0009

02432-004

02432-007
2.0477 5.0007

2.0475 5.0005
–40 –10 20 50 80 110 125 –40 –10 20 50 80 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. ADR420 Typical Output Voltage vs. Temperature Figure 6. ADR425 Typical Output Voltage vs. Temperature

2.5015 0.55

2.5013
0.50
2.5011
SUPPLY CURRENT (mA) +125°C
2.5009
0.45
2.5007
VOUT (V)

+25°C
2.5005 0.40

2.5003
–40°C
0.35
2.5001

2.4999
0.30
02432-005

02432-008
2.4997

2.4995 0.25
–40 –10 20 50 80 110 125 4 6 8 10 12 14 15
TEMPERATURE (°C) INPUT VOLTAGE (V)

Figure 4. ADR421 Typical Output Voltage vs. Temperature Figure 7. ADR420 Supply Current vs. Input Voltage

3.0010 0.55

3.0008
0.50
3.0006
SUPPLY CURRENT (mA)

3.0004
0.45
3.0002 +125°C
VOUT (V)

3.0000 0.40

2.9998
+25°C
0.35
2.9996

2.9994 –40°C
0.30
02432-006

02432-009

2.9992

2.9990 0.25
–40 –10 20 50 80 110 125 4 6 8 10 12 14 15
TEMPERATURE (°C) INPUT VOLTAGE (V)

Figure 5. ADR423 Typical Output Voltage vs. Temperature Figure 8. ADR421 Supply Current vs. Input Voltage

Rev. G | Page 9 of 24
ADR420/ADR421/ADR423/ADR425
0.55 70
IL = 0mA TO 5mA
60
0.50

LOAD REGULATION (ppm/mA)


+125°C
50
SUPPLY CURRENT (mA)

0.45
VIN = 5V
40
0.40
+25°C 30

0.35 VIN = 6.5V


20
–40°C

0.30
10

02432-010

02432-013
0.25 0
4 6 8 10 12 14 15 –40 –10 20 50 80 110 125
INPUT VOLTAGE (V) TEMPERATURE (°C)

Figure 9. ADR423 Supply Current vs. Input Voltage Figure 12. ADR421 Load Regulation vs. Temperature

0.55 70
IL = 0mA TO 10mA
60
0.50

+125°C LOAD REGULATION (ppm/mA) 50


SUPPLY CURRENT (mA)

0.45 VIN = 7V

40
0.40
+25°C 30
VIN = 15V
0.35
20
–40°C
0.30
10

02432-014
02432-011

0.25 0
6 8 10 12 14 15 –40 –10 20 50 80 110 125
INPUT VOLTAGE (V) TEMPERATURE (°C)

Figure 10. ADR425 Supply Current vs. Input Voltage Figure 13. ADR423 Load Regulation vs. Temperature

70 35
VIN = 15V
IL = 0mA TO 5mA IL = 0mA TO 10mA
60 30
LOAD REGULATION (ppm/mA)

LOAD REGULATION (ppm/mA)

50 25

40 20
VIN = 4.5V
VIN = 6V
30 15

20 10

10 5
02432-012

02432-015

0 0
–40 –10 20 50 80 110 125 –40 –10 20 50 80 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. ADR420 Load Regulation vs. Temperature Figure 14. ADR425 Load Regulation vs. Temperature

Rev. H | Page 10 of 24
ADR420/ADR421/ADR423/ADR425
6 14
VIN = 4.5V TO 15V VIN = 7.5V TO 15V
12
5
LINE REGULATION (ppm/V)

LINE REGULATION (ppm/V)


10
4

8
3
6

2
4

1
2

02432-016

02432-019
0 0
–40 –10 20 50 80 110 125 –40 –10 20 50 80 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 15. ADR420 Line Regulation vs. Temperature Figure 18. ADR425 Line Regulation vs. Temperature

6 2.5
VIN = 5V TO 15V

5
2.0

DIFFERENTIAL VOLTAGE (V)


–40°C
LINE REGULATION (ppm/V)

4
+25°C
1.5

3 +85°C

1.0
2

0.5
1
02432-017

02432-020
0 0
–40 –10 20 50 80 110 125 0 1 2 3 4 5
TEMPERATURE (°C) LOAD CURRENT (mA)

Figure 16. ADR421 Line Regulation vs. Temperature Figure 19. ADR420 Minimum Input/Output Voltage
Differential vs. Load Current

9 2.5
VIN = 5V TO 15V
8

2.0
7
DIFFERENTIAL VOLTAGE (V)

–40°C
LINE REGULATION (ppm/V)

6
+25°C
1.5
5
+125°C
4
1.0
3

2
0.5

1
02432-018

02432-021

0 0
–40 –10 20 50 80 110 0 1 2 3 4 5
TEMPERATURE (°C) LOAD CURRENT (mA)

Figure 17. ADR423 Line Regulation vs. Temperature Figure 20. ADR421 Minimum Input/Output Voltage
Differential vs. Load Current

Rev. H | Page 11 of 24
ADR420/ADR421/ADR423/ADR425
2.5

2.0
DIFFERENTIAL VOLTAGE (V)

–40°C

+25°C
1.5

1µV/DIV
+125°C

1.0

0.5

02432-025
02432-022
0
0 1 2 3 4 5 TIME (1s/DIV)
LOAD CURRENT (mA)

Figure 21. ADR423 Minimum Input/Output Voltage Figure 24. ADR421 Typical Noise Voltage 0.1 Hz to 10 Hz
Differential vs. Load Current

2.5

2.0
DIFFERENTIAL VOLTAGE (V)

–40°C

+25°C
1.5
50µV/DIV

+125°C

1.0

0.5

02432-026
02432-023

0
0 1 2 3 4 5 TIME (1s/DIV)
LOAD CURRENT (mA)

Figure 22. ADR425 Minimum Input/Output Voltage Figure 25. Typical Noise Voltage 10 Hz to 10 kHz
Differential vs. Load Current

30 1k
TEMPERATURE SAMPLE SIZE – 160
+25°C –40°C
+125°C +25°C
25
VOLTAGE NOISE DENSITY (nV/ Hz)
NUMBER OF PARTS

20
ADR425
ADR423
15 100

10 ADR421
ADR420

5
02432-027
02432-024

0 10
10 100 1k 10k
MORE
0
10
20
30
40
50
60
70
80
90

110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10

100

120
130

FREQUENCY (Hz)
DEVIATION (ppm)

Figure 23. ADR421 Typical Hysteresis Figure 26. Voltage Noise Density vs. Frequency

Rev. H | Page 12 of 24
ADR420/ADR421/ADR423/ADR425

CBYPASS = 0µF CL = 100nF 1mA LOAD


LINE INTERRUPTION
VOUT
1V/DIV

VIN
500mV/DIV

LOAD OFF

VOUT 500mV/DIV 2V/DIV


LOAD ON

02432-031
02432-028
TIME (100µs/DIV) TIME (100µs/DIV)

Figure 27. ADR421 Line Transient Response, no CBYPASS Figure 30. ADR421 Load Transient Response, CL = 100 nF

CIN = 0.01µF
CBYPASS = 0.1µF NO LOAD
LINE INTERRUPTION
VOUT

VIN 2V/DIV
500mV/DIV

VIN

VOUT 500mV/DIV

2V/DIV

02432-032
02432-029

TIME (100µs/DIV) TIME (4µs/DIV)

Figure 28. ADR421 Line Transient Response, CBYPASS = 0.1 μF Figure 31. ADR421 Turn-Off Response

CIN = 0.01µF
CL = 0µF 1mA LOAD NO LOAD

VOUT 2V/DIV
1V/DIV

VOUT

LOAD OFF
2V/DIV

2V/DIV

LOAD ON VIN
02432-033
02432-030

TIME (100µs/DIV) TIME (4µs/DIV)

Figure 29. ADR421 Load Transient Response, no CL Figure 32. ADR421 Turn-On Response

Rev. H | Page 13 of 24
ADR420/ADR421/ADR423/ADR425
CL = 0.01µF 50
NO INPUT CAP
45
VOUT
40
2V/DIV

OUTPUT IMPEDANCE (Ω)


35

30
VIN ADR425
25
ADR423
20

15 ADR421

2V/DIV 10

02432-034

02432-037
5
ADR420
0
TIME (4µs/DIV) 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 33. ADR421 Turn-Off Response Figure 36. Output Impedance vs. Frequency

CL = 0.01µF 0
NO INPUT CAP
–10
2V/DIV
–20

VOUT RIPPLE REJECTION (dB) –30

–40

–50
2V/DIV
–60

–70

VIN –80
02432-035

02432-038
–90

–100
TIME (4µs/DIV) 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 34. ADR421 Turn-On Response Figure 37. Ripple Rejection vs. Frequency

CBYPASS = 0.1µF
RL = 500Ω
CL = 0

VOUT 5V/DIV

VIN 2V/DIV
02432-036

TIME (100µs/DIV)

Figure 35. ADR421 Turn-On/Turn-Off Response

Rev. H | Page 14 of 24
ADR420/ADR421/ADR423/ADR425

TERMINOLOGY
Temperature Coefficient Thermal Hysteresis
The change of output voltage over the operating temperature The change of output voltage after the device is cycled through
range is normalized by the output voltage at 25°C, and temperatures from +25°C to −40°C to +125°C and back to
expressed in ppm/°C as +25°C. This is a typical value from a sample of parts put
VOUT (T2 ) − VOUT (T1 ) through such a cycle.
TCVOUT ( ppm / °C ) = × 10 6
VOUT ( 25°C ) × (T2 − T1 ) VOUT _ HYS = VOUT ( 25°C ) − VOUT _ TC
VOUT ( 25°C ) − VOUT _ TC
where: VOUT _ HYS ( ppm) = × 10 6
VOUT (25°C) = VOUT at 25°C. VOUT ( 25°C )
VOUT (T1) = VOUT at Temperature 1.
where:
VOUT (T2) = VOUT at Temperature 2.
VOUT (25°C) = VOUT at 25°C.
Line Regulation VOUT_TC = VOUT at 25 °C after temperature cycle at +25°C to
The change in output voltage due to a specified change in input −40°C to +125°C and back to +25°C.
voltage. It includes the effects of self-heating. Line regulation is
Input Capacitor
expressed in either percent per volt, parts per million per volt,
Input capacitors are not required on the ADR42x. There is
or microvolts per volt change in input voltage.
no limit for the value of the capacitor used on the input, but a
Load Regulation 1 μF to 10 μF capacitor on the input improves transient response
The change in output voltage due to a specified change in load in applications where the supply suddenly changes. An addi-
current. It includes the effects of self-heating. Load regulation is tional 0.1 μF capacitor in parallel also helps to reduce noise
expressed in either microvolts per milliampere, parts per from the supply.
million per milliampere, or ohms of dc output resistance.
Output Capacitor
Long-Term Stability The ADR42x do not need output capacitors for stability under
Typical shift of output voltage at 25°C on a sample of parts any load condition. An output capacitor, typically 0.1 μF, filters
subjected to operation life test of 1000 hours at 125°C. out any low level noise voltage and does not affect the operation
ΔVOUT = VOUT (t 0 ) − VOUT (t 1 ) of the part. On the other hand, the load transient response can
be improved with an additional 1 μF to 10 μF output capacitor
VOUT (t 0 ) − VOUT (t 1 )
ΔVOUT ( ppm) = × 10 6 in parallel. A capacitor here acts as a source of stored energy for
VOUT (t 0 ) sudden increase in load current. The only parameter that
where: degrades by adding an output capacitor is the turn-on time,
VOUT (t0) = VOUT at 25°C at Time 0. which depends on the size of the selected capacitor.
VOUT (t1) = VOUT at 25°C after 1000 hours operation at 125°C.

Rev. H | Page 15 of 24
ADR420/ADR421/ADR423/ADR425

THEORY OF OPERATION
The ADR42x series of references uses a reference generation DEVICE POWER DISSIPATION CONSIDERATIONS
technique known as XFET (eXtra implanted junction FET). The ADR42x family of references is guaranteed to deliver load
This technique yields a reference with low supply current, good currents to 10 mA with an input voltage that ranges from 4.5 V
thermal hysteresis, and exceptionally low noise. The core of the to 18 V. When these devices are used in applications at higher
XFET reference consists of two junction field-effect transistors currents, the following equation should be used to account for
(JFET), one having an extra channel implant to raise its pinch- the temperature effects due to power dissipation increases:
off voltage. By running the two JFETs at the same drain current,
the difference in pinch-off voltage can be amplified and used to TJ = PD × θJA + TA (2)
form a highly stable voltage reference. where:
The intrinsic reference voltage is about 0.5 V with a negative TJ and TA are the junction temperature and the ambient
temperature coefficient of about −120 ppm/°C. This slope is temperature, respectively.
essentially constant to the dielectric constant of silicon and can PD is the device power dissipation.
be closely compensated by adding a correction term generated θJA is the device package thermal resistance.
in the same fashion as the proportional-to-temperature (PTAT) BASIC VOLTAGE REFERENCE CONNECTIONS
term used to compensate band gap references. The primary
Voltage references, in general, require a bypass capacitor
advantage over a band gap reference is that the intrinsic tem-
connected from VOUT to GND. The circuit in Figure 39
perature coefficient is approximately 30 times lower (therefore
illustrates the basic configuration for the ADR42x family of
requiring less correction). This results in much lower noise
references. Other than a 0.1 μF capacitor at the output to help
because most of the noise of a band gap reference comes from
improve noise suppression, a large output capacitor at the
the temperature compensation circuitry.
output is not required for circuit stability.
Figure 38 shows the basic topology of the ADR42x series. The
temperature correction term is provided by a current source
TP 1 ADR420/ 8 TP

VIN 2
ADR421/ 7 NIC
with a value designed to be proportional to absolute tempera- + ADR423/
10µF 0.1µF OUTPUT
ture. The general equation is NIC 3 ADR425 6
TOP VIEW 0.1µF
4 (Not to Scale) 5 TRIM
VOUT = G × (ΔVP − R1 × IPTAT) (1)

02432-040
NIC = NO INTERNAL CONNECTION
where: TP = TEST PIN (DO NOT CONNECT)
G is the gain of the reciprocal of the divider ratio. Figure 39. Basic Voltage Reference Configuration
ΔVP is the difference in pinch-off voltage between the two JFETs.
IPTAT is the positive temperature coefficient correction current. NOISE PERFORMANCE
The noise generated by ADR42x references is typically less
Each ADR42x device is created by on-chip adjustment of R2
than 2 μV p-p over the 0.1 Hz to 10 Hz band for the ADR420,
and R3 to achieve the specified reference output.
ADR421, and ADR423. Figure 24 shows the 0.1 Hz to 10 Hz
VIN
I1 I1 noise of the ADR421, which is only 1.75 μV p-p. The noise
IPTAT ADR420/ADR421/ measurement is made with a band-pass filter made of a 2-pole
ADR423/ADR425
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
VOUT
low-pass filter with a corner frequency at 10 Hz.
R2
* TURN-ON TIME
ΔVP At power-up (cold start), the time required for the output
R1 R3
voltage to reach its final value within a specified error band
is defined as the turn-on settling time. Two components typi-
02432-039

*EXTRA CHANNEL IMPLANT cally associated with this are the time for the active circuits to
VOUT = G(ΔVP – R1 × IPTAT) GND
settle and the time for the thermal gradients on the chip to
Figure 38. Simplified Schematic
stabilize. Figure 31 to Figure 35 show the turn-on settling time
for the ADR421.

Rev. H | Page 16 of 24
ADR420/ADR421/ADR423/ADR425

APPLICATIONS
OUTPUT ADJUSTMENT SOURCE FIBER
GIMBAL + SENSOR
The ADR42x trim terminal can be used to adjust the output DESTINATION
LASER BEAM FIBER
voltage over a ±0.5% range. This feature allows the system
designer to trim system errors out by setting the reference to ACTIVATOR
ACTIVATOR MEMS MIRROR RIGHT
a voltage other than the nominal. This is also helpful if the LEFT

part is used in a system at temperature to trim out any error.


Adjustment of the output has a negligible effect on the AMPL PREAMP AMPL
temperature performance of the device. To avoid degrading
temperature coefficients, both the trimming potentiometer ADR421
and the two resistors need to be low temperature coefficient CONTROL
ELECTRONICS ADR421
types, preferably <100 ppm/°C. DAC ADC DAC ADR421
INPUT

02432-042
2
DSP
VIN VOUT 6 OUTPUT
VOUT = ±0.5% Figure 41. All Optical Router Network
ADR420/
ADR421/ A NEGATIVE PRECISION REFERENCE
ADR423/
ADR425 R1 WITHOUT PRECISION RESISTORS
470kΩ RP
TRIM 5
GND 10kΩ In many current-output CMOS DAC applications where
4 R2 10kΩ (ADR420)
15kΩ (ADR421) the output signal voltage must be of the same polarity as the
02432-041

reference voltage, a current-switching DAC is often recon-


Figure 40. Output Trim Adjustment figured into a voltage-switching DAC with a 1.25 V reference,
an op amp, a pair of resistors, and an additional operational
REFERENCE FOR CONVERTERS IN OPTICAL
amplifier at the output to reinvert the signal. A negative voltage
NETWORK CONTROL CIRCUITS
reference should be used because an additional operational
In the high capacity, all optical router network of Figure 41, amplifier is not required for either reinversion (current-switching
arrays of micromirrors direct and route optical signals from mode) or amplification (voltage-switching mode) of the DAC
fiber to fiber, without first converting them to electrical form, output voltage. In general, any positive voltage reference can be
which reduces the communication speed. The tiny micro- converted into a negative voltage reference using an operational
mechanical mirrors are positioned so that each is illuminated amplifier and a pair of matched resistors in an inverting
by a single wavelength that carries unique information and configuration. The disadvantage to this approach is that the
can be passed to any desired input and output fiber. The mirrors largest single source of error in the circuit is the relative
are tilted by the dual-axis actuators controlled by precision matching of the resistors used.
analog-to-digital converters (ADCs) and digital-to-analog
A negative reference can easily be generated by adding a
converters (DACs) within the system. Due to the microscopic
precision op amp and configuring as shown in Figure 42. VOUT
movement of the mirrors, not only is the precision of the
is at virtual ground and, therefore, the negative reference can be
converters important, but the noise associated with these
taken directly from the output of the op amp. The op amp must
controlling converters is extremely critical, because total noise
be dual-supply, low offset and have rail-to-rail capability if
within the system can be multiplied by the numbers of
negative supply voltage is close to the reference output.
converters used. Consequently, the exceptional low noise of the
+VDD
ADR42x is necessary to maintain the stability of the control
loop for this application.
2
VIN
ADR420/
ADR421/
ADR423/
ADR425
6 VOUT
GND
4

A1 –VREF

A1 = OP777, OP193
02432-043

–VDD

Figure 42. Negative Reference

Rev. H | Page 17 of 24
ADR420/ADR421/ADR423/ADR425
VIN
HIGH VOLTAGE FLOATING CURRENT SOURCE
The circuit in Figure 43 can be used to generate a floating 2
RLW
current source with minimal self-heating. This particular ADR420/ VOUT
ADR421/ VIN SENSE
configuration can operate on high supply voltages determined ADR423/
ADR425 RLW
by the breakdown voltage of the N-channel JFET. A1
VOUT
VOUT 6 FORCE
+VS
GND
RL
SST111 4

02432-045
VISHAY A1 = OP191

2 Figure 44. Advantage of Kelvin Connection


VIN
ADR420/ DUAL-POLARITY REFERENCES
ADR421/
ADR423/ Dual-polarity references can easily be made with an op amp and
ADR425
a pair of resistors. In order not to defeat the accuracy obtained
VOUT 6
OP09 2N3904 by the ADR42x, it is imperative to match the resistance toler-
GND ance and the temperature coefficient of all components.
4 VIN
RL
2.10kΩ 1µF 0.1µF 2
VIN VOUT 6 +5V
02432-044

R1 R2
–VS 10kΩ
U1 10kΩ
Figure 43. High Voltage Floating Current Source ADR425 +10V

KELVIN CONNECTIONS GND TRIM 5 V+


4 U2
–5V
In many portable instrumentation applications where PC board OP1177
V–

02432-046
cost and area are important considerations, circuit intercon- R3
nects are often narrow. These narrow lines can cause large 5kΩ
–10V
voltage drops if the voltage reference is required to provide load Figure 45. +5 V and −5 V Reference Using ADR425
currents to various functions. In fact, a circuit’s interconnects
can exhibit a typical line resistance of 0.45 mΩ/square (1 oz. Cu,
+2.5V
for example). Force and sense connections, also referred to as
Kelvin connections, offer a convenient method of eliminating +10V
2
the effects of voltage drops in circuit wires. Load currents flow-
VIN VOUT 6
ing through wiring resistance produce an error (VERROR = R × IL)
U1
at the load. However, the Kelvin connection in Figure 44 ADR425 R1
5.6kΩ
overcomes the problem by including the wiring resistance
GND TRIM 5
within the forcing loop of the op amp. Because the op amp 4
R2
senses the load voltage, op amp loop control forces the output to 5.6kΩ V+
U2
compensate for the wiring error and to produce the correct OP1177
voltage at the load. V–
–2.5V
02432-047

–10V

Figure 46. +2.5 V and −2.5 V Reference Using ADR425

Rev. H | Page 18 of 24
ADR420/ADR421/ADR423/ADR425
PROGRAMMABLE CURRENT SOURCE PROGRAMMABLE DAC REFERENCE VOLTAGE
Together with a digital potentiometer and a Howland current With a multichannel DAC, such as the quad, 12-bit voltage
pump, the ADR425 forms the reference source for a program- output AD7398, one of its internal DACs, and an ADR42x
mable current as voltage reference can be used as a common programmable
VREFx for the rest of the DACs. The circuit configuration is
⎛ R2 A + R2 B ⎞
⎜ ⎟ shown in Figure 48. The relationship of VREFx to VREF depends
⎝ R1 ⎠
IL = × VW (3) on the digital code and the ratio of R1 and R, and is given by
R2 B
⎛ R2 ⎞
and VREF × ⎜1 + ⎟
VREF x = ⎝ R1 ⎠
(5)
D ⎛ D R2 ⎞
VW = × V REF (4) ⎜1 + N × ⎟
2N ⎝ 2 R1 ⎠
where: where:
D is the decimal equivalent of the input code. D is the decimal equivalent of input code.
N is the number of bits. N is the number of bits.
C1 VREF is the applied external reference.
10pF
VREFx is the reference voltage for DACs A to D.
VDD R1' R2'
50kΩ 1kΩ
2
Table 9. VREFx vs. R1 and R2
VDD
VIN TRIM 5 R1, R2 Digital Code VREF
U1 AD5232 V+ R1 = R2 0000 0000 0000 2 VREF
U2
ADR425 DIGITAL POT C2
A2
R1 = R2 1000 0000 0000 1.3 VREF
VDD 10pF OP2177
VOUT 6
GND A V– R2B R1 = R2 1111 1111 1111 VREF
4 10Ω
U2 V+ R1 = 3R2 0000 0000 0000 4 VREF
VSS
B W A1
OP2177 R1 R2A
R1 = 3R2 1000 0000 0000 1.6 VREF
V– 50kΩ 1kΩ R1 = 3R2 1111 1111 1111 VREF
VSS VL LOAD
02432-048

IL
Figure 47. Programmable Current Source R2
R1 ±0.1%
VREF A
R1' and R2' must be equal to R1 and R2A + R2B, respectively.
B
VOUTA ±0.1%

Theoretically, R2B can be made as small as needed to achieve


B DACA VREF

the current needed within A2 output current driving capability. VIN


ADR425
In the example shown in Figure 47, OP2177 is able to deliver VREF B
VOUTB
a maximum of 10 mA. Because the current pump uses both VOB = VREF x (DB)
DACB
positive and negative feedback, capacitors C1 and C2 are needed
to ensure that negative feedback prevails and, therefore, avoiding
oscillation. This circuit also allows bidirectional current flow if VREF C VOUTC
VOC = VREF x (DC)
the inputs VA and VB of the digital potentiometer are supplied
B
DACC
with the dual-polarity references as previously shown.
VREF D VOUTD
VOD = VREF x (DD)
DACD
02432-049

AD7398

Figure 48. Programmable DAC Reference

Rev. H | Page 19 of 24
ADR420/ADR421/ADR423/ADR425
PRECISION VOLTAGE REFERENCE FOR DATA PRECISION BOOSTED OUTPUT REGULATOR
CONVERTERS A precision voltage output with boosted current capability
The ADR42x family has a number of features that make it ideal can be realized with the circuit shown in Figure 50. In this
for use with ADCs and DACs. The exceptionally low noise, circuit, U2 forces VOUT to be equal to VREF by regulating the turn
tight temperature coefficient, and high accuracy characteristics on of N1. Therefore, the load current is furnished by VIN. In
make the ADR42x ideal for low noise applications such as this configuration, a 50 mA load is achievable at VIN of 5 V.
cellular base station applications. Moderate heat is generated on the MOSFET, and higher current
AD7701 is an example of an ADC that is well suited for the can be achieved by replacing the larger device. In addition, for
ADR42x. The ADR421 is used as the precision reference for a heavy capacitive load with step input, a buffer may be added
the converter in Figure 49. The AD7701 is a 16-bit ADC with at the output to enhance the transient response.
N1
on-chip digital filtering intended for measuring wide dynamic
range and low frequency signals, such as those representing VIN VOUT
RL
chemical, physical, or biological processes. It contains a charge- 5V 25Ω
2 U1
balancing (Σ-Δ) ADC, calibration microcontroller with on-chip VIN 2N7002
static RAM, clock oscillator, and serial communications port. VOUT 6 + V+
ADR421 U2
+5V 5
ANALOG TRIM
AD8601
SUPPLY 0.1µF 10µF GND – V–

02432-051
AD7701
4
AVDD DVDD
SLEEP 0.1µF Figure 50. Precision Boosted Output Regulator
VIN
MODE
VOUT VREF

0.1µF ADR420/ DRDY DATA READY


ADR421/ CS READ (TRANSMIT)
ADR423/
SCLK SERIAL CLOCK
ADR425
SDATA SERIAL CLOCK
GND
CLKIN
RANGES BP/UP
SELECT CLKOUT
CALIBRATE CAL SC1
ANALOG SC2
INPUT AIN
ANALOG DGND
GROUND AGND
0.1µF
0.1µF
DVSS
AVSS
–5V
ANALOG
SUPPLY 0.1µF 10µF
02432-050

Figure 49. Voltage Reference for 16-Bit ADC AD7701

Rev. H | Page 20 of 24
ADR420/ADR421/ADR423/ADR425

OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)


BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)

0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-A A


CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]


Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

3.20
3.00
2.80

8 5 5.15
3.20
4.90
3.00
4.65
2.80 1
4

PIN 1
0.65 BSC
0.95
0.85 1.10 MAX
0.75
0.80
0.15 0.38 8° 0.60
0.23
0.00 0.22 0° 0.40
0.08
COPLANARITY SEATING
0.10 PLANE

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 52. 8-Lead Mini Small Outline Package [MSOP]


(RM-8)
Dimensions shown in millimeters

Rev. H | Page 21 of 24
ADR420/ADR421/ADR423/ADR425
ORDERING GUIDE
Output Initial Temperature
Voltage, Accuracy Coefficient Temperature Package Package
Model VOUT (V) mV % (ppm/°C) Range Description Option Branding
ADR420AR 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420AR-REEL7 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420ARZ 1 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420ARZ-REEL71 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420ARM 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 R4A
ADR420ARM-REEL7 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 R4A
ADR420ARMZ1 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 L0C
ADR420ARMZ-REEL71 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 L0C
ADR420BR 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420BR-REEL7 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420BRZ1 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420BRZ-REEL71 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421AR 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421AR-REEL7 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARZ1 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARZ-REEL71 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARM 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R5A
ADR421ARM-REEL7 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R5A
ADR421ARMZ1 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R06
ADR421ARMZ-REEL71 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R06
ADR421BR 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BR-REEL7 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BRZ1 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BRZ-REEL71 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423AR 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423AR-REEL7 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARZ1 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARZ-REEL71 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARM 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R6A
ADR423ARM-REEL7 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R6A
ADR423BR 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423BR-REEL7 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARMZ1 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R0U
ADR423ARMZ-REEL71 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R0U
ADR423BRZ1 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423BRZ-REEL71 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425AR 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425AR-REEL7 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARZ1 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARZ-REEL71 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARM 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A
ADR425ARM-REEL7 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A
ADR425ARMZ1 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A#
ADR425ARMZ-REEL71 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A#
ADR425BR 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BR-REEL7 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BRZ1 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BRZ-REEL71 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
1
Z = RoHS Compliant Part. # denotes RoHS-compliant product may be top or bottom marked.

Rev. H | Page 22 of 24
ADR420/ADR421/ADR423/ADR425

NOTES

Rev. H | Page 23 of 24
ADR420/ADR421/ADR423/ADR425

NOTES

©2001–2007 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
C02432-0-6/07(H)

Rev. H | Page 24 of 24

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