library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity one_four_demux is
port(i : in BIT;
sel : in BIT_VECTOR(1 downto 0);
y : out BIT_VECTOR(3 downto 0));
end one_four_demux;

architecture one_four_demux_arch of one_four_demux is

begin
process(i,sel)
begin
case sel is
when "00" => y(0) <= i;
when "01" => y(1) <= i;
when "10" => y(2) <= i;
when others => y(3) <= i;
end case;
end process;
end one_four_demux_arch;

-----------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity four_one_mux is
port(i : in BIT_VECTOR(3 downto 0);
sel : in BIT_VECTOR(1 downto 0);
y : out bit);
end four_one_mux;

architecture four_one_mux_arch of four_one_mux is

begin
process(i,sel)
begin
case sel is
when "00" => y <= i(0);
when "01" => y <= i(1);
when "10" => y <= i(2);
when others => y <= i(3);
end case;
end process;
end four_one_mux_arch;

------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity two_one_mux is
port(i : in BIT_VECTOR(1 downto 0);
sel : in bit;
y : out bit);
end two_one_mux;

architecture two_one_mux_arch of two_one_mux is

 begin
process(i,sel)
begin
case sel is
when '0' => y <= i(0);
when others => y <= i(1);
end case;
end process;
end two_one_mux_arch;

-----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity four_one_mux_struct is
port( a,b,c,d : in bit;
sel1,sel0 : in bit;
y_out : out bit);
end four_one_mux_struct;

architecture four_one_mux_struct_arch of four_one_mux_struct is

signal s1,s2:bit;

component two_one_mux is
port(i : in BIT_VECTOR(1 downto 0);
sel : in bit;
y : out bit);
end component;

begin

mux1 : two_one_mux port map(i(0)=>a, i(1)=>b, sel=>sel0, y=>s1);

mux2 : two_one_mux port map(i(0)=>c, i(1)=>d, sel=>sel0, y=>s2);
mux3 : two_one_mux port map(i(0)=>s1, i(1)=>s2, sel=>sel1,
y=>y_out);

end four_one_mux_struct_arch;

-------
entity and_gate is
port (a, b : in bit;
c: out bit);
end and_gate;
architecture arch_and of and_gate is
begin
process(a,b)
begin
if (a ='1' and b = '1') then
c<= '1';
else
c<= '0';
end if;
end process;
end arch_and;
---
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate1 is
port (a, b : in std_logic;
c: out std_logic);
end and_gate1;
architecture arch_and of and_gate1 is
begin
process(a,b)
begin
if (a ='1' and b = '1') then
c<= '1';
else
c<= '0';
end if;
end process;
end arch_and1;

--------
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate1 is
port (a : in std_logic_vector(1 downto 0);
c: out std_logic);
end and_gate1;
architecture arch_and of and_gate1 is
begin
process(a)
begin
if (a="11" ) then
c<= '1';
else
c<= '0';
end if;
end process;
end arch_and1;