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OPA830

SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

Low-Power, Single-Supply, Wideband


Operational Amplifier
FEATURES DESCRIPTION
D HIGH BANDWIDTH: The OPA830 is a low-power, single-supply, wideband,
250MHz (G = +1) voltage-feedback amplifier designed to operate on a single
110MHz (G = +2) +3V or +5V supply. Operation on ±5V or +10V supplies is also
D LOW SUPPLY CURRENT: 3.9mA (VS = +5V) supported. The input range extends below the negative
D FLEXIBLE SUPPLY RANGE: supply and to within 1.7V of the positive supply. Using
complementary common-emitter outputs provides an output
±1.4V to ±5.5V Dual Supply
swing to within 25mV of either supply while driving 150Ω. High
+2.8V to +11V Single Supply
output drive current (±80mA) and low differential gain and
D INPUT RANGE INCLUDES GROUND ON phase errors also make them ideal for single-supply
SINGLE SUPPLY consumer video products.
D 4.88V OUTPUT SWING ON +5V SUPPLY Low distortion operation is ensured by the high gain
D HIGH SLEW RATE: 550V/µs bandwidth product (110MHz) and slew rate (550V/µs), making
D LOW INPUT VOLTAGE NOISE: 9.2nV/√Hz the OPA830 an ideal input buffer stage to 3V and 5V CMOS
D Pb-FREE SOT23 PACKAGE ADCs. Unlike other low-power, single-supply amplifiers,
distortion performance improves as the signal swing is
decreased. A low 9.2nV/√Hz input voltage noise supports
APPLICATIONS wide dynamic range operation.
D SINGLE-SUPPLY ANALOG-TO-DIGITAL The OPA830 is available in an industry-standard SO-8
CONVERTER (ADC) INPUT BUFFERS
package. The OPA830 is also available in an ultra-small
D SINGLE-SUPPLY VIDEO LINE DRIVERS SOT23-5 package. For fixed-gain line driver applications,
D CCD IMAGING CHANNELS consider the OPA832.
D LOW-POWER ULTRASOUND
D PLL INTEGRATORS RELATED PRODUCTS
D PORTABLE CONSUMER ELECTRONICS
DESCRIPTION SINGLES DUALS TRIPLES QUADS
+3V Rail-to-Rail — OPA2830 — OPA4830
Rail-to-Rail Fixed Gain OPA832 OPA2832 OPA3832 —
2.26kΩ +3V General-Purpose
OPA690 OPA2690 OPA3690 —
(1800V/µs slew rate)
374Ω
Low-Noise,
VIN 100Ω THS1040 OPA820 OPA2822 — OPA4820
High DC Precision
OPA830 10−Bit
40MSPS
22pF

562Ω 750Ω

DC-Coupled, +3V ADC Driver

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
 

            Copyright  2004−2008, Texas Instruments Incorporated
                  
   !       !   

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

This integrated circuit can be damaged by ESD. Texas


ABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits be
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12VDC handled with appropriate precautions. Failure to observe
Internal Power Dissipation . . . . . . . . . . . . . . See Thermal Analysis proper handling and installation procedures can cause damage.
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2.5V
ESD damage can range from subtle performance degradation to
Input Voltage Range (Single Supply) . . . . . . . −0.5V to +VS + 0.3V complete device failure. Precision integrated circuits may be more
Storage Temperature Range: D, DBV . . . . . . . . . −65°C to +125°C susceptible to damage because very small parametric changes could
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C cause the device not to meet its published specifications.
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V
Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1500V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.

PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD TEMPERATURE
DESIGNATOR MARKING NUMBER MEDIA, QUANTITY
RANGE
OPA830 SO-8 Surface-Mount D −40°C to +85°C OPA830 OPA830ID Rails, 100
″ ″ ″ ″ ″ OPA830IDR Tape and Reel, 2500
OPA830 SOT23-5 DBV −40°C to +85°C A72 OPA830IDBVT Tape and Reel, 250
″ ″ ″ ″ ″ OPA830IDBVR Tape and Reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.

PIN CONFIGURATIONS

Output 1 5 +VS

−VS 2

NC 1 8 NC
Noninverting Input 3 4 Inverting Input
Inverting Input 2 7 +VS
SOT23−5
Noninverting Input 3 6 Output
5

−VS 4 5 NC

SO−8
NC = No Connection
A72
1

Pin Orientation/Package Marking

2

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

ELECTRICAL CHARACTERISTICS: VS = ±5V


Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).
OPA830ID, IDBV
TYP MIN/MAX OVER TEMPERATURE
TEST
0°C to −40°C to MIN/ LEVEL
PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX (3)
AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth G = +1, VO ≤ 0.2VPP 310 MHz typ C
G = +2, VO ≤ 0.2VPP 120 70 68 65 MHz min B
G = +5, VO ≤ 0.2VPP 25 18 16 15 MHz min B
G = +10, VO ≤ 0.2VPP 11 8 7 6 MHz min B
Gain-Bandwidth Product G ≥ +10 110 85 82 80 MHz min B
Peaking at a Gain of +1 VO ≤ 0.2VPP 6 dB typ C
Slew Rate G = +2, 2V Step 600 280 270 260 V/µs min B
Rise Time 0.5V Step 3.3 5.8 5.85 5.9 ns max B
Fall Time 0.5V Step 3.5 5.9 5.95 6.0 ns max B
Settling Time to 0.1% G = +2, 1V Step 42 63 65 66 ns max B
Harmonic Distortion VO = 2VPP, f = 5MHz
2nd-Harmonic RL = 150Ω −67 −59 −57 −56 dBc max B
RL ≥ 500Ω −71 −62 −61 −60 dBc max B
3rd-Harmonic RL = 150Ω −60 −50 −49 −48 dBc max B
RL ≥ 500Ω −77 −65 −62 −59 dBc max B
Input Voltage Noise f > 1MHz 9.5 10.5 11.0 11.5 nV/√Hz max B
Input Current Noise f > 1MHz 3.7 4.7 5.2 5.7 pA/√Hz max B
NTSC Differential Gain 0.07 % typ C
NTSC Differential Phase 0.17 ° typ C
DC PERFORMANCE(4) RL = 150Ω
Open-Loop Voltage Gain 74 66 65 64 dB min A
Input Offset Voltage ±1.5 ±7 ±8.1 ±8.6 mV max A
Average Offset Voltage Drift — ±25 ±25 µV/°C max B
Input Bias Current VCM = 0V +5 +10 +12 +13 µA max A
Input Bias Current Drift ±12 ±12 nA/°C max B
Input Offset Current VCM = 0V ±0.1 ±1 ±1.2 ±1.4 µA max A
Input Offset Current Drift — ±5 ±5 nA/°C max B
INPUT
Negative Input Voltage(5) −5.5 −5.4 −5.3 −5.2 V max A
Positive Input Voltage(5) 3.2 3.1 3.0 2.9 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 76 74 72 dB min A
Input Impedance
Differential Mode 10 2.1 kΩ  pF typ C
Common-Mode 400 1.2 kΩ  pF typ C
OUTPUT
Output Voltage Swing G = +2, RL = 1kΩ to GND ±4.88 ±4.86 ±4.85 ±4.84 V min A
G = +2, RL = 150Ω to GND ±4.64 ±4.60 ±4.58 ±4.56 V min A
Current Output, Sinking and Sourcing ±85 ±65 ±60 ±55 mA min A
Short-Circuit Current Output Shorted to Ground 150 mA typ C
Closed-Loop Output Impedance G = +2, f ≤ 100kHz 0.06 Ω typ C
POWER SUPPLY
Minimum Operating Voltage ±1.4 V typ C
Maximum Operating Voltage ±5.5 ±5.5 ±5.5 V max A
Maximum Quiescent Current VS = ±5V 4.25 4.7 5.3 5.9 mA max A
Minimum Quiescent Current VS = ±5V 4.25 4.0 3.6 3.3 mA min A
Power-Supply Rejection Ratio (+PSRR) Input-Referred 66 61 60 59 dB min A
THERMAL CHARACTERISTICS
Specification: ID, IDBV −40 to +85 °C typ C
Thermal Resistance, qJA
D SO-8 125 °C/W typ C
DBV SOT23-5 150 °C/W typ C
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical
value only for information.
(4) Current is considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

ELECTRICAL CHARACTERISTICS: VS = +5V


Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
OPA830ID, IDBV
TYP MIN/MAX OVER TEMPERATURE
TEST
0°C to −40°C to MIN/ LEVEL
PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX (3)

AC PERFORMANCE (see Figure 1)


Small-Signal Bandwidth G = +1, VO ≤ 0.2VPP 250 MHz typ C
G = +2, VO ≤ 0.2VPP 110 72 70 68 MHz min B
G = +5, VO ≤ 0.2VPP 24 17 16 15 MHz min B
G = +10, VO ≤ 0.2VPP 11 8 7 6 MHz min B
Gain-Bandwidth Product G ≥ +10 110 84 80 79 MHz min B
Peaking at a Gain of +1 VO ≤ 0.2VPP 5 dB typ C
Slew Rate G = +2, 2V Step 550 280 270 260 V/µs min B
Rise Time 0.5V Step 3.3 5.7 5.8 5.9 ns max B
Fall Time 0.5V Step 3.3 5.7 5.8 5.9 ns max B
Settling Time to 0.1% G = +2, 1V Step 43 64 66 67 ns max B
Harmonic Distortion VO = 2VPP, f = 5MHz
2nd-Harmonic RL = 150Ω −62 −55 −54 −53 dBc max B
RL ≥ 500Ω −64 −58 −57 −56 dBc max B
3rd-Harmonic RL = 150Ω −58 −50 −49 −48 dBc max B
RL ≥ 500Ω −84 −66 −63 −60 dBc max B
Input Voltage Noise f > 1MHz 9.2 10.2 10.7 11.2 nV/√Hz max B
Input Current Noise f > 1MHz 3.5 4.5 5.0 5.5 pA/√Hz max B
NTSC Differential Gain 0.08 % typ C
NTSC Differential Phase 0.09 ° typ C
DC PERFORMANCE(4) RL = 150Ω
Open-Loop Voltage Gain 72 66 65 64 dB min A
Input Offset Voltage ±0.5 ±5.0 ±6.0 ±6.5 mV max A
Average Offset Voltage Drift — ±20 ±20 µV/°C max B
Input Bias Current VCM = 2.5V +5 +10 +12 +13 µA max A
Input Bias Current Drift ±12 ±12 nA/°C max B
Input Offset Current VCM = 2.5V ±0.1 ±0.8 ±1 ±1.2 µA max A
Input Offset Current Drift — ±5 ±5 nA/°C max B
INPUT
Least Positive Input Voltage(5) −0.5 −0.4 −0.3 −0.2 V max A
Most Positive Input Voltage(5) 3.2 3.1 3.0 2.9 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 76 74 72 dB min A
Input Impedance
Differential-Mode 10 2.1 kΩ  pF typ C
Common-Mode 4001.2 kΩ  pF typ C
OUTPUT
Least Positive Output Voltage G = +5, RL = 1kΩ to 2.5V 0.09 0.11 0.12 0.13 V max A
G = +5, RL = 150Ω to 2.5V 0.21 0.24 0.25 0.26 V max A
Most Positive Output Voltage G = +5, RL = 1kΩ to 2.5V 4.91 4.89 4.88 4.87 V min A
G = +5, RL = 150Ω to 2.5V 4.78 4.75 4.73 4.72 V min A
Current Output, Sourcing and Sinking ±80 ±60 ±55 ±52 mA min A
Short-Circuit Output Current Output Shorted to Either Supply 140 mA typ C
Closed-Loop Output Impedance G = +2, f ≤ 100kHz 0.06 Ω typ C
POWER SUPPLY
Minimum Operating Voltage +2.8 V typ C
Maximum Operating Voltage +11 +11 +11 V max A
Maximum Quiescent Current VS = +5V 3.9 4.1 4.8 5.5 mA max A
Minimum Quiescent Current VS = +5V 3.9 3.7 3.4 3.1 mA min A
Power-Supply Rejection Ratio (PSRR) Input-Referred 66 61 60 59 dB min A
THERMAL CHARACTERISTICS
Specification: ID, IDBV −40 to +85 °C typ C
Thermal Resistance, qJA
D SO-8 125 °C/W typ C
DBV SOT23-5 150 °C/W typ C
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4) Current considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

ELECTRICAL CHARACTERISTICS: VS = +3V


Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).
OPA830ID, IDBV
MIN/MAX OVER
TYP TEMPERATURE
TEST
0°C to MIN/ LEVEL
PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) UNITS MAX (3)
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth G = +2, VO ≤ 0.2VPP 100 72 68 MHz min B
G = +5, VO ≤ 0.2VPP 22 17 16 MHz min B
G = +10, VO ≤ 0.2VPP 10 8 7 MHz min B
Gain-Bandwidth Product G ≥ +10 100 80 76 MHz min B
Slew Rate 1V Step 225 140 110 V/µs min B
Rise Time 0.5V Step 3.3 5.5 5.6 ns max B
Fall Time 0.5V Step 3.3 5.5 5.6 ns max B
Settling Time to 0.1% 1V Step 45 72 87 ns max B
Harmonic Distortion VO = 1VPP, f = 5MHz
2nd-Harmonic RL = 150Ω −67 −61 −59 dBc max B
RL ≥ 500Ω −67 −61 −59 dBc max B
3rd-Harmonic RL = 150Ω −66 −59 −58 dBc max B
RL ≥ 500Ω −77 −59 −58 dBc max B
Input Voltage Noise f > 1MHz 9.2 10.2 10.7 nV/√Hz max B
Input Current Noise f > 1MHz 3.5 4.5 5.0 pA/√Hz max B
DC PERFORMANCE(4)
Open-Loop Voltage Gain 72 66 65 dB min A
Input Offset Voltage ±1.5 ±7 ±8.1 mV max A
Average Offset Voltage Drift — ±25 µV/°C max B
Input Bias Current VCM = 1.0V +5 +10 +12 µA max A
Input Bias Current Drift ±12 nA/°C max B
Input Offset Current VCM = 1.0V ±0.1 ±1 ±1.2 µA max A
Input Offset Current Drift — ±5 nA/°C max B
INPUT
Least Positive Input Voltage(5) −0.45 −0.4 −0.27 V max A
Most Positive Input Voltage(5) 1.2 1.1 1.0 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 75 73 dB min A
Input Impedance
Differential-Mode 10 2.1 kΩ  pF typ C
Common-Mode 4001.2 kΩ  pF typ C
OUTPUT
Least Positive Output Voltage G = +5, RL = 1kΩ to 1.5V 0.08 0.11 0.125 V max A
G = +5, RL = 150Ω to 1.5V 0.17 0.39 0.40 V max A
Most Positive Output Voltage G = +5, RL = 1kΩ to 1.5V 2.91 2.88 2.85 V min A
G = +5, RL = 150Ω to 1.5V 2.82 2.74 2.70 V min A
Current Output, Sourcing 30 20 18 mA min A
Current Output, Sinking 30 20 18 mA min A
Short-Circuit Output Current Output Shorted to Either Supply 45 mA typ C
Closed-Loop Output Impedance See Figure 2, f < 100kHz 0.06 Ω typ C
POWER SUPPLY
Minimum Operating Voltage +2.8 V min B
Maximum Operating Voltage +11 +11 V max A
Maximum Quiescent Current VS = +3V 3.7 4.0 4.7 mA max A
Minimum Quiescent Current VS = +3V 3.7 3.3 3.1 mA min A
Power-Supply Rejection Ratio (PSRR) Input-Referred 64 60 58 dB min A
THERMAL CHARACTERISTICS
Specification: ID, IDBV −40 to +85 °C typ C
Thermal Resistance, qJA
D SO-8 125 °C/W typ C
DBV SOT23-5 150 °C/W typ C
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4) Current considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

5

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = ±5V


At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).

NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE


6 3
G = +1 G = −2
3 RF = 0Ω 0
G = −1
Normalized Gain (dB)

Normalized Gain (dB)


0
G = +2 −3
−3
G = +5 −6
−6 G = −5
−9
−9 G = −10
G = +10 −12
−12
VO = 0.2VPP
−15 VO = 0.2VPP
−15 RL = 150Ω
RL = 150Ω
See Figure 3
−18 −18
1 10 100 600 1 10 100 400
Frequency (MHz) Frequency (MHz)

NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE


9 3
VO = 2VPP
6 0
VO = 1VPP
3 −3
VO = 0.5VPP
Gain (dB)

Gain (dB)

0 −6
VO = 1VPP
−3 −9
VO = 4VPP
−6 −12
G = +2V/V VO = 2VPP VO = 4VPP
−9 RL = 150Ω −15 G = −1V/V
See Figure 3 VO = 0.5VPP RL = 150Ω
−12 −18
10 100 500 10 100 400
Frequency (MHz) Frequency (MHz)

NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE


0.4 2.0 0.4 2.0
Large−Signal Output Voltage (500mV/div)

Large−Signal Output Voltage (500mV/div)


Small−Signal Output Voltage (100mV/div)

Small−Signal Output Voltage (100mV/div)

G = +2V/V G = −1V/V
0.3 See Figure 3 Large−Signal ± 1V 1.5 0.3 1.5
Right Scale
0.2 1.0 0.2 1.0

0.1 0.5 0.1 0.5


Small−Signal ± 100mV
0 0 0 Small−Signal ± 100mV 0
Left Scale
Left Scale
−0.1 −0.5 −0.1 −0.5

−0.2 −1.0 −0.2 −1.0


Large−Signal ± 1V
−0.3 −1.5 −0.3 Right Scale −1.5

−0.4 −2.0 −0.4 −2.0


Time (10ns/div) Time (10ns/div)

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = ±5V (continued)


At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).

HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE


−50 −40
f = 5MHz −45 VO = 2VPP
−55 VO = 2VPP RL = 500Ω
−50

Harmonic Distortion (dBc)


Harmonic Distortion (dBc)

G = +2V/V G = +2V/V
−60 See Figure 3 −55 See Figure 3
Input Limited for VCM = 0V
3rd−Harmonic −60
−65
−65
2nd−Harmonic
−70 −70
2nd−Harmonic
−75 −75
−80
−80 3rd−Harmonic
−85
−85 −90
100 1000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Resistance (Ω ) Supply Voltage (±VS)

HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY


−55 −50
f = 5MHz VO = 2VPP 3rd−Harmonic
−55
−60 RL = 500Ω G = +2V/V RL = 150Ω
G = +2V/V −60 See Figure 3
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

−65 See Figure 3 −65


2nd−Harmonic
−70 −70
RL = 500Ω
−75
−75
2nd−Harmonic −80
−80 2nd−Harmonic
−85
3rd−Harmonic RL = 150Ω
−85 −90 3rd−Harmonic
−95 RL = 500Ω
−90
−100
−95 −105
0.1 1 10 0.1 1 10
Output Voltage Swing (VPP) Frequency (MHz)

TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS SUPPLY AND OUTPUT CURRENT vs TEMPERATURE


−40 95 6.0
PI
−45 PO
3rd−Order Spurious Level (dBc)

50Ω OPA830
500Ω
20MHz 90 5.5
−50
Output Current (50mA/div)

750Ω Supply Current (4mA/div)


−55 85 5.0
750Ω Source/Sink Output Current
−60 Left Scale
10MHz
−65 80 4.5
−70
75 4.0
−75
5MHz
−80 50 Supply Current 3.5
Right Scale
−85
−90 25 3.0
−26 −20 −14 −8 −2 6 −50 −25 0 25 50 75 100 125
Single−Tone Load Power (2dBm/div) Ambient Temperature (_ C)

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = ±5V (continued)


At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).

FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD


8 120
Normalized Gain to Capacitive Load (dB)

CL = 10pF 0dB Peaking Targeted


7 110
CL = 100pF
6 100
5 90
CL = 1000pF
4 80

RS (Ω)
3 70
2 60
1 RS
50
VI

0 50Ω OPA830
CL 1kΩ(1)
VO
40
−1 750Ω
30
−2
NOTE: (1) 1kΩ is optional.
750Ω
20
−3 10
1 10 100 200 1 10 100 1k
Frequency (MHz) Capacitive Load (pF)

OUTPUT SWING vs LOAD RESISTANCE OUTPUT VOLTAGE AND CURRENT LIMITATIONS


6 6
1W Internal
5 5 Power Lim it Output
4 4 Current Lim it
3 3 RL = 500Ω
Output Voltage (V)

2 2
RL = 50Ω
1 G = +5V/V 1
VO (V)

RL = 100Ω
0 VS = ±5V 0
−1 −1
−2 −2
−3 −3
−4 −4
Output 1W Internal
−5 −5 Current Limit P ower Limit
−6 −6
10 100 1k −160 −120 −80 −40 0 40 80 120 160
Resistance (Ω ) IO (mA)

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = ±5V, Differential Configuration


At TA = 25°C, GD = +2, RF = 604Ω, and RL = 500Ω, unless otherwise noted.

+5V DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE


3

OPA830
GD = 1
0
GD = 2

Normalized Gain (dB)


−5V −3
RG 6 0 4Ω

−6
6 0 4Ω
GD = 5
VI RL

+5V 50 0 Ω
VO −9
RG G D = 10
−12
OPA830 VO = 200mVPP
RL = 500Ω
GD =
604Ω −15
−5V RG 1 10 100 200
Frequency (MHz)

DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE


9 −45
−50
6 −55
Harmonic Distortion (dBc)

3rd−Harmonic
VO = 5VPP −60
3 VO = 4VPP
−65
Gain (dB)

GD = 2
−70 f = 5MHz
0
−75
VO = 2VPP
−3 −80
VO = 1VPP −85
−6 −90
GD = 2 2nd−Harmonic
VO = 200mVPP −95
RL = 500Ω
−9 −100
1 10 100 200 100 150 200 250 300 350 400 450 500
Frequency (MHz) Resistance (Ω)

DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE


−40 −55
GD = 2 GD = 2
−60
−50 VO = 4VPP RL = 500Ω
−65
Harmonic Distortion (dBc)

RL = 500Ω f = 5MHz
Harmonic Distrtion (dBc)

3rd−Harmonic
−60 −70
3rd−Harmonic −75
−70
−80
−80
−85
2nd−Harmonic
−90 −90
−95
−100
2nd−Harmonic −100
−110 −105
0.1 1 10 100 1 10
Frequency (MHz) Output Voltage Swing (VPP)

9

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +5V


At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).

NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE


6 3
G = +1 G = −2
3 RF = 0Ω 0
G = −1
Normalized Gain (dB)

Normalized Gain (dB)


0
G = +2 −3
−3
G = +5 −6
−6 G = −5
−9
−9 G = −10
G = +10 −12
−12
VO = 0.2VPP VO = 0.2VPP
−15 RL = 150Ω −15 RL = 150Ω
See Figure 1 See Figure 9
−18 −18
1 10 100 500 1 10 100 400
Frequency (MHz) Frequency (MHz)

NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE


9 3

6 0

3 −3
VO = 1VPP VO = 0.5VPP VO = 1VPP
Gain (dB)

Gain (dB)

0 −6
VO = 0.5VPP
−3 −9

−6 −12
G = +2V/V VO = 2VPP G = −1V/V VO = 2VPP
−9 RL = 150Ω −15 RL = 150Ω
See Figure 1 See Figure 9
−12 −18
10 100 500 10 100 500
Frequency (MHz) Frequency (MHz)

NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE


2.9 4.5 2.9 4.5
Small−Signal Output Voltage (100mV/div)

Small−Signal Output Voltage (100mV/div)


Large−Signal Output Voltage (500mV/div)

Large−Signal Output Voltage (500mV/div)


G = +2V/V G = −1V/V
2.8 Large−Signal ± 1V 4.0 2.8 4.0
See Figure 1
Right Scale
2.7 3.5 2.7 3.5

2.6 3.0 2.6 3.0


Small−Signal ± 100mV
2.5 Left Scale 2.5 2.5 Small−Signal ± 100mV 2.5
Left Scale
2.4 2.0 2.4 2.0

2.3 1.5 2.3 1.5


Large−Signal ± 1V
2.2 1.0 2.2 Right Scale 1.0

2.1 0.5 2.1 0.5


Time (10ns/div) Time (10ns/div)

10

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +5V (continued)


At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).

HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY


−50 −50
G = +2V/V 3rd−Harmonic
−55
−55 VO = 2VPP R L = 150Ω
−60 See Figure 1
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)


−60 2nd−Harmonic
−65
2nd−Harmonic RL = 500Ω
−65 −70
−75 2nd−Harmonic
−70 RL = 150Ω
−80
−75 −85
f = 5MHz −90
−80
VO = 2VPP 3rd−Harmonic −95
−85 G = +2V/V 3rd−Harmonic
−100
See Figure 1 RL = 500Ω
−90 −105
100 1000 0.1 1 10
Load Resistance (Ω ) Frequency (MHz)

HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs NONINVERTING GAIN


−45 −55
f = 5MHz
−50
RL = 500Ω Input Limited −60
−55 G = +2V/V 2nd−Harmonic
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

−60 See Figure 1 −65


−65
−70 −70
−75
2nd−Harmonic −75
−80
−85 −80 f = 5MHz
3rd−Harmonic RL = 500Ω
−90
3rd−Harmonic −85 VO = 2VPP
−95
See Figure 1
−100 −90
0.1 1 10 1 10
Output Voltage Swing (VPP) Gain (V/V)

HARMONIC DISTORTION vs INVERTING GAIN TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS


−55 −45
PI
−50
3rd−Order Spurious Level (dBc)

50Ω OPA830 PO
20MHz
−60 500Ω
−55
Harmonic Distortion (dBc)

750Ω
2nd−Harmonic
−60
−65 750Ω
−65
10MHz
−70 −70
3rd−Harmonic −75
−75
−80
5MHz
f = 5MHz
−85
−80 RL = 500Ω
VO = 2VPP −90
−85 −95
1 10 −26 −24 −22 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2
Gain ( V/V ) Single−Tone Load Power (dBm)

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TYPICAL CHARACTERISTICS: VS = +5V (continued)


At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).

INPUT VOLTAGE AND CURRENT NOISE DENSITY CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
100 100
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)

Output Impedance (Ω)


10
Voltage Noise
(9.2nV/√Hz)
10 1

Current Noise 0.1


(3.5pA/√Hz)

1 0.01
10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD


130 8
Normalized Gain to Capacitive Load (dB)

CL = 10pF
120 0dB Peaking Targeted 7
110 6
CL = 100pF
100 5
CL = 1000pF
90 4
80
RS (Ω)

3
70
2
60
1 VI RS
50 VO
0 50Ω O P A830

40 CL 1kΩ(1)

−1 750Ω
30
20 −2 750Ω
NOTE: (1) 1kΩis optional.

10 −3
1 10 100 1k 1 10 100 300
Capacitive Load (pF) Frequency (MHz)

OPEN−LOOP GAIN AND PHASE VOLTAGE RANGES vs TEMPERATURE


80 0 5.0
4.5 Most Positive Output Voltage
70 −20
4.0
60 −40
Open−Loop Phase (_ )

20 log (AOL)
Open−Loop Gain (dB)

3.5
−60
Voltage Range (V)

50 Most Positive Input Voltage


3.0
40 −80 2.5
30 −100 2.0
∠(AOL) RL = 150Ω
20 −120 1.5
10 −140 1.0
0.5 Least Positive Output Voltage
0 −160
0
−10 −180
−0.5 Least Positive Input Voltage
−20 −200 −1.0
100 1k 10k 100k 1M 10M 100M 1G −50 0 50 110
Frequency (Hz) Ambient Temperature (10_ C/div)

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TYPICAL CHARACTERISTICS: VS = +5V (continued)


At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).

TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE


4 8 100 6.0
Input Bias Current (IB)

Input Bias and Offset Current (µV)


3 6 95 5.5
Quiescent Current

Supply Current (0.5mA/div)


Input Offset Voltage (mV)

Output Current (5mA/div)


2 4 90 5.0

1 2 85 4.5
10 × Input Offset Current (IOS) Output Current, Sinking
0 0 80 4.0

−1 −2 75 3.5

−2 −4 70 3.0
Input Offset Voltage (VOS) Output Current, Sourcing
−3 −6 65 2.5

−8 −8 60 2.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Ambient Temperature (_ C) Ambient Temperature (_C)

CMRR AND PSRR vs FREQUENCY OUTPUT SWING vs LOAD RESISTANCE


90 5.5
Common−Mode Rejection Ratio (dB)
Power−Supply Rejection Ratio (dB)

80 5.0
4.5
70
CMRR 4.0
Output Voltage (V)

60 3.5
G = +5V/V
50 3.0
2.5
40
2.0
30 1.5
PSRR
20 1.0
0.5
10
0
0 −0.5
1k 10k 100k 1M 10M 100M 10 100 1k
Frequency (Hz) Load Resistance (Ω )

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +5V, Differential Configuration


At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.

+5V DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE


3
1.2kΩ
2.5V
GD = 1
0
1.2kΩ 0.1µF OPA830 GD = 2

Normalized Gain (dB)


−3
R 60 4Ω
G

−6
60 4Ω R VO
GD = 5
L

VI −9
+5V
GD = 10
R
G
−12
VO = 200mVPP
1.2kΩ OPA830 RL = 500Ω
2.5V
−15
604Ω
1.2kΩ 0.1µF GD = 1 10 100 200
RG
Frequency (MHz)

DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE


9 −40
−45
6
−50
Harmonic Distortion (dBc)

VO = 3VPP 3rd−Harmonic
−55
3
VO = 2VPP
−60 VO = 4VPP
Gain (dB)

GD = 2
0 −65
f = 5MHz
−70
−3
VO = 1VPP −75

−6 −80
GD = 2 VO = 0.2VPP
−85 2nd−Harmonic
RL = 500Ω
−9 −90
1 10 100 200 100 150 200 250 300 350 400 450 500
Frequency (MHz) Resistance (Ω)

DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE


−30 −55
VO = 4VPP GD = 2
−40 GD = 2 −60 RL = 500Ω
RL = 500Ω 3rd−Harmonic f = 5MHz
−65
Harmonic Distrtion (dBc)
Harmonic Distrtion (dBc)

−50 3rd−Harmonic
−70
−60
−75
−70
2nd−Harmonic −80
−80
−85
2nd−Harmonic
−90 −90
−100 −95
−110 −100
1 10 100 1 10
Frequency (MHz) Output Voltage Swing (VPP)

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TYPICAL CHARACTERISTICS: VS = +3V


At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).

NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE


6 3

3 0
G = −1
Normalized Gain (dB)

Normalized Gain (dB)


0 −3
G = +2
G = −2
−3
G = +5 −6
−6 G = −5
−9
−9 G = −10
G = +10 −12
−12
RL = 150Ω
−15 RL = 150Ω
−15 VO = 0.2VPP
VO = 0.2VPP
See Figure 2
−18 −18
1 10 100 400 1 10 100 300
Frequency (MHz) Frequency (MHz)

NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE


9 3
VO = 0.5VPP
6 0
VO = 1VPP
3 −3
VO = 0.5VPP VO = 1VPP
Gain (dB)

Gain (dB)

0 −6
VO = 1.5VPP VO = 1.5VPP
−3 −9

−6 −12
RL = 150Ω
−9 G = +2V/V −15
RL = 150Ω
See Figure 2 G = −1V/V
−12 −18
10 100 400 10 100 300
Frequency (MHz) Frequency (MHz)

NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE


1.20 2.00 1.20 2.00
Large−Signal Output Voltage (250mV/div)

Large−Signal Output Voltage (250mV/div)


Small−Signal Output Voltage (90mV/div)

Small−Signal Output Voltage (90mV/div)

G = +2V/V G = −1V/V
1.15 Large−Signal ± 0.5V 1.75 1.15 Large−Signal ± 0.5V 1.75
See Figure 2
Right Scale Right Scale
1.10 1.50 1.10 1.50

1.05 1.25 1.05 1.25


Small−Signal ± 100mV Small−Signal ± 100mV
1.00 Left Scale 1.00 1.00 Left Scale 1.00

0.95 0.75 0.95 0.75

0.90 0.50 0.90 0.50

0.85 0.25 0.85 0.25

0.80 0 0.80 0
Time (10ns/div) Time (10ns/div)

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +3V (continued)


At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).

HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs OUTPUT VOLTAGE


−50 −40
f = 5MHz f = 5MHz
−55 VO = 1VPP RL = 500Ω Input Limited
−50
G = +2V/V

Harmonic Distortion (dBc)


G = +2V/V
Harmonic Distortion (dBc)

−60 See Figure 2 See Figure 2


−60
−65 2nd−Harmonic

−70 −70
2nd−Harmonic 3rd−Harmonic
−75 −80
−80
3rd−Harmonic −90
−85

−90 −100
100 1000 0.1 1 10
Resistance (Ω ) Output Voltage Swing (VPP )

HARMONIC DISTORTION vs FREQUENCY TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS


−55 −40
−60 VO = 1VPP −45 PI
3rd−Order Spurious Level (dBc)

OPA830 PO
G = +2V/V 50Ω
2nd−Harmonic −50
Harmonic Distortion (dBc)

500Ω
−65 See Figure 2
RL = 500Ω −55
750Ω

−70 20MHz
−60 750Ω

−75 −65
2nd−Harmonic
−80 RL = 150Ω −70

−85 3rd−Harmonic −75 10MHz


RL = 150Ω −80
−90
−85 5MHz
3rd−Harmonic
−95 −90
RL = 500Ω
−100 −95
0.1 1 10 −28 −26 −24 −22 −20 −18 −16 −14 −12 −10 −8
Frequency (MHz) Single−Tone Load Power (dBm)

RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD


190 8
Normalized Gain to Capacitive Load (dB)

0dB Peaking Targeted CL = 10pF


7
170 CL = 100pF
6
150
5
130 CL = 1000pF
4
RS (Ω)

110 3

90 2
1 VI RS
70 50Ω O P A830 VO
0 CL 1kΩ(1)
50 −1
750Ω

NOTE: (1) 1kΩ is optional.


30 −2 750Ω

10 −3
1 10 100 1k 1 10 100 200
Capacitive Load (pF) Frequency (MHz)

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +3V (continued)


At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).

OUTPUT SWING vs LOAD RESISTANCE


3.5

3.0

2.5

Output Voltage (V) 2.0


G = +5V/V
1.5

1.0

0.5

−0.5
10 100 1k
Load Resistance (Ω )

17

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS: VS = +3V, Differential Configuration


At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.

+3V DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE


3
2kΩ
1V
0
1kΩ 0.1µF OPA830 GD = 1

Normalized Gain (dB)


−3
RG 60 4Ω GD = 2
−6
60 4Ω RL VO GD = 5
VI −9
+3V
GD = 10
RG
−12
VO = 200mVPP
2kΩ
1V
OPA830 RL = 500Ω
−15
0.1µ F 604Ω 1 10 100 200
1kΩ GD =
RG
Frequency (MHz)

DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE


9 −40
−45
6
−50
Harmonic Distortion (dBc)

−55
3 3rd−Harmonic
VO = 2VPP −60 VO = 4VPP
Gain (dB)

GD = 2
0 −65
f = 5MHz
VO = 1VPP
−70
−3
VO = 200mVPP −75

−6 −80
2nd−Harmonic
−85
GD = 2
−9 −90
1 10 100 200 100 150 200 250 300 350 400 450 500
Frequency (MHz) Resistance (Ω)

DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE


−35 −75
GD = 2
−45 VO = 2VPP GD = 2
RL = 500Ω −80 RL = 500Ω
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

−55 f = 5MHz
3rd−Harmonic
−65 −85
3rd−Harmonic
−75
2nd−Harmonic
−85 −90

−95
2nd−Harmonic −95
−105

−115 −100
0.1 1 10 100 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Frequency (MHz) Output Voltage Swing (VPP)

18

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

the Electrical Characteristics are taken directly at the input


APPLICATIONS INFORMATION and output pins. For the circuit of Figure 2, the total
WIDEBAND VOLTAGE-FEEDBACK effective load on the output at high frequencies is
OPERATION 150Ω || 1500Ω. The 1.13kΩ and 2.26kΩ resistors at the
The OPA830 is a unity-gain stable, very high-speed noninverting input provide the common-mode bias
voltage-feedback op amp designed for single-supply voltage. Their parallel combination equals the DC
operation (+3V to +10V). The input stage supports input resistance at the inverting input (RF), reducing the DC
voltages below ground and to within 1.7V of the positive output offset due to input bias current.
supply. The complementary common-emitter output stage
provides an output swing to within 25mV of ground and the
positive supply. The OPA830 is compensated to provide VS = +3V
stable operation with a wide range of resistive loads.
6.8µF
Figure 1 shows the AC-coupled, gain of +2 configuration +
used for the +5V Specifications and Typical Characteristic
Curves. For test purposes, the input impedance is set to 2.26kΩ 0.1µF
50Ω with a resistor to ground. Voltage swings reported in
the Electrical Characteristics are taken directly at the input 0.1µF
+1V
and output pins. For the circuit of Figure 1, the total VIN
effective load on the output at high frequencies is
53.6Ω 1.13kΩ OPA830 VOUT
150Ω || 1500Ω. The 1.5kΩ resistors at the noninverting
input provide the common-mode bias voltage. Their RL
parallel combination equals the DC resistance at the 150Ω
inverting input (RF), reducing the DC output offset due to
input bias current. RG RF
+VS
750Ω 750Ω
3
+VS/3

VS = +5V
Figure 2. AC-Coupled, G = +2, +3V Single-Supply
6.8µF Specification and Test Circuit
+

1.50kΩ 0.1µF
Figure 3 shows the DC-coupled, gain of +2, dual
power-supply circuit configuration used as the basis of the
±5V Electrical Characteristics and Typical Characteristics.
0.1µF
2.5V For test purposes, the input impedance is set to 50Ω with
VIN
a resistor to ground and the output impedance is set to
53.6Ω 1.50kΩ OPA830 VOUT 150Ω with a series output resistor. Voltage swings
reported in the specifications are taken directly at the input
RL and output pins. For the circuit of Figure 3, the total
150Ω
effective load will be 150Ω || 1.5kΩ. Two optional
components are included in Figure 3. An additional
RG RF
750Ω 750Ω
+VS resistor (348Ω) is included in series with the noninverting
+VS/2
2 input. Combined with the 25Ω DC source resistance
looking back towards the signal generator, this gives an
input bias current cancelling resistance that matches the
Figure 1. AC-Coupled, G = +2, +5V Single-Supply 375Ω source resistance seen at the inverting input (see
Specification and Test Circuit the DC Accuracy and Offset Control section). In addition
to the usual power-supply decoupling capacitors to
Figure 2 shows the AC-coupled, gain of +2 configuration ground, a 0.01µF capacitor is included between the two
used for the +3V Specifications and Typical Characteristic power-supply pins. In practical PC board layouts, this
Curves. For test purposes, the input impedance is set to optional capacitor will typically improve the 2nd-harmonic
50Ω with a resistor to ground. Voltage swings reported in distortion performance by 3dB to 6dB.

19

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

+5V +VS
0.1µF 6.8µF
+ R2

50Ω Source R1
348Ω
VIN
VIN
VO 150Ω
OPA830 VOUT
50Ω OPA830

0.01µF RF
750Ω R3 R4

RG
750Ω
6.8µF 0.1µF
+ Figure 4. DC Level-Shifting

−5V The circuit on the front page is a good example of this type
of application. It was designed to take VIN between 0V and
Figure 3. DC-Coupled, G = +2, Bipolar Supply 0.5V and produce VOUT between 1V and 2V when using
Specification and Test Circuit a +3V supply. This means G = 2.00, and
SINGLE-SUPPLY ADC INTERFACE ∆VOUT = 1.50V − G × 0.25V = 1.00V. Plugging these
The ADC interface on the front page shows a DC-coupled, values into the above equations (with R4 = 750Ω) gives:
single-supply ADC driver circuit. Many systems are now NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The
requiring +3V supply capability of both the ADC and its resistors were changed to the nearest standard values for
driver. The OPA830 provides excellent performance in this the front page circuit.
demanding application. Its large input and output voltage
ranges and low distortion support converters such as the AC-COUPLED OUTPUT VIDEO LINE DRIVER
THS1040 shown in the figure on page 1. The input Low-power and low-cost video line drivers often buffer
level-shifting circuitry was designed so that VIN can be digital-to-analog converter (DAC) outputs with a gain of 2
between 0V and 0.5V, while delivering an output voltage into a doubly-terminated line. Those interfaces typically
of 1V to 2V for the THS1040. require a DC blocking capacitor. For a simple solution, that
interface often has used a very large value blocking
DC LEVEL-SHIFTING capacitor (220µF) to limit tilt, or SAG, across the frames.
Figure 4 shows a DC-coupled noninverting amplifier that
One approach to creating a very low high-pass pole
level-shifts the input up to accommodate the desired
location using much lower capacitor values is shown in
output voltage range. Given the desired signal gain (G),
Figure 5. This circuit gives a voltage gain of 2 at the output
and the amount VOUT needs to be shifted up (∆VOUT)
pin with a high-pass pole at 8Hz. Given the 150Ω load, a
when VIN is at the center of its range, the following
simple blocking capacitor approach would require a 133µF
equations give the resistor values that produce the desired value. The two much lower valued capacitors give this
performance. Assume that R4 is between 200Ω and
same low-pass pole using this simple SAG correction
1.5kΩ.
circuit of Figure 5.
NG = G + VOUT/VS
R1 = R4/G
R2 = R4/(NG − G)
R3 = R4/(NG −1)
where:
NG = 1 + R4/R3
VOUT = (G)VIN + (NG − G)VS
Make sure that VIN and VOUT stay within the specified
input and output voltage ranges.

20

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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

+5V

1.87kΩ
Video DAC
47µF 75Ω
OPA830 VO
78.7Ω
75Ω Load

845Ω 22µF

325Ω 528Ω

650Ω

Figure 5. Video Line Driver with SAG Correction

The input is shifted slightly positive in Figure 5 using the impedance source, such as an op amp. The resistor
voltage divider from the positive supply. This gives about values are low to reduce noise. Using both RT and RF
a 200mV input DC offset that will show up at the output pin helps minimize the impact of parasitic impedances.
as a 400mV DC offset when the DAC output is at zero
current during the sync tip portion of the video signal. This
acts to hold the output in its linear operating region. This +5V
RT
will pass on any power-supply noise to the output with a
VIN
gain of approximately −20dB, so good supply decoupling
is recommended on the power-supply pin. Figure 6 shows RC OPA830 VOUT
the frequency response for the circuit of Figure 5. This plot
shows the 8Hz low-frequency high-pass pole and a
high-end cutoff at approximately 100MHz.
RG RF

−3 Figure 7. Compensated Noninverting Amplifier


Normalized Gain (dB)

−6
The Noise Gain can be calculated as follows:
−9
RF
−12 G1 + 1 )
RG (1)
−15
RF
−18 RT ) G
G2 + 1 ) 1
−21 RC (2)
1 10 102 103 104 105 106 107 108 109
Frequency (Hz) NG + G 1 G2 (3)
Figure 6. Video Line Driver Response to Matched A unity-gain buffer can be designed by selecting
Load RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG). This
gives a noise gain of 2, so the response will be similar to
NONINVERTING AMPLIFIER WITH REDUCED the Characteristics Plots with G = +2. Decreasing RC to
PEAKING 20.0Ω will increase the noise gain to 3, which typically
Figure 7 shows a noninverting amplifier that reduces gives a flat frequency response, but with less bandwidth.
peaking at low gains. The resistor RC compensates the The circuit in Figure 1 can be redesigned to have less
OPA830 to have higher Noise Gain (NG), which reduces peaking by increasing the noise gain to 3. This is
the AC response peaking (typically 5dB at G = +1 without accomplished by adding RC = 2.55kΩ across the op amp
RC) without changing the DC gain. VIN needs to be a low inputs.

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SINGLE-SUPPLY ACTIVE FILTER passband (above the 32kHz AC-coupling corner), and a
maximum stop band attenuation of 36dB at the amplifier’s
The OPA830, while operating on a single +3V or +5V −3dB bandwidth of 30MHz.
supply, lends itself well to high-frequency active filter
designs. Again, the key additional requirement is to
establish the DC operating point of the signal near the
DESIGN-IN TOOLS
supply midpoint for highest dynamic range. Figure 8 DEMONSTRATION BOARDS
shows an example design of a 1MHz low-pass Butterworth Two printed circuit boards (PCBs) are available to assist
filter using the Sallen-Key topology. in the initial evaluation of circuit performance using the
OPA830 in its two package options. Both of these are
Both the input signal and the gain setting resistor are offered free of charge as unpopulated PCBs, delivered
AC-coupled using 0.1µF blocking capacitors (actually with a user’s guide. The summary information for these
giving bandpass response with the low-frequency pole set fixtures is shown in Table 1.
to 32kHz for the component values shown). As discussed
for Figure 1, this allows the midpoint bias formed by the
Table 1. Demonstration Fixtures by Package
two 1.87kΩ resistors to appear at both the input and output ORDERING LITERATURE
pins. The midband signal gain is set to +4 (12dB) in this PRODUCT PACKAGE NUMBER NUMBER
case. The capacitor to ground on the noninverting input is OPA830ID SO-8 DEM-OPA-SO-1A SBOU009
intentionally set larger to dominate input parasitic terms. At
a gain of +4, the OPA830 on a single supply will show OPA830IDBV SOT23-5 DEM-OPA-SOT-1A SBOU010
30MHz small- and large-signal bandwidth. The resistor
values have been slightly adjusted to account for this The demonstration fixtures can be requested at the Texas
limited bandwidth in the amplifier stage. Tests of this circuit Instruments web site (www.ti.com) through the OPA830
show a precise 1MHz, −3dB point with a maximally-flat product folder.

+5V

100pF

1.87kΩ
0.1µF 137Ω 432Ω
VI

150pF OPA830 4V I
1.87kΩ
1MHz, 2nd−Order
Butterworth Filter

1.5kΩ

500Ω

0.1µF

Figure 8. Single-Supply, High-Frequency Active Filter

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MACROMODEL AND APPLICATIONS increase both the RF and RG values, and then achieve the
SUPPORT input matching impedance with a third resistor to ground
Computer simulation of circuit performance using SPICE (see Figure 9). The total input impedance becomes the
is often a quick way to analyze the performance of the parallel combination of RG and the additional shunt
OPA830 and its circuit designs. This is particularly true for resistor.
video and RF amplifier circuits where parasitic
capacitance and inductance can play a major role on BANDWIDTH vs GAIN:
circuit performance. A SPICE model for the OPA830 is NONINVERTING OPERATION
available through the TI web page (www.ti.com). The
applications department is also available for design Voltage-feedback op amps exhibit decreasing closed-loop
assistance. These models predict typical small signal AC, bandwidth as the signal gain is increased. In theory, this
transient steps, DC performance, and noise under a wide relationship is described by the Gain Bandwidth Product
variety of operating conditions. The models include the (GBP) shown in the specifications. Ideally, dividing GBP
noise terms found in the electrical specifications of the by the noninverting signal gain (also called the Noise Gain,
data sheet. These models do not attempt to distinguish or NG) will predict the closed-loop bandwidth. In practice,
between the package types in their small-signal AC this only holds true when the phase margin approaches
performance. 90°, as it does in high-gain configurations. At low gains
(increased feedback factors), most amplifiers will exhibit a
more complex response with lower phase margin. The
OPA830 is compensated to give a slightly peaked
OPERATING SUGGESTIONS response in a noninverting gain of 2 (see Figure 3). This
OPTIMIZING RESISTOR VALUES results in a typical gain of +2 bandwidth of 110MHz, far
Since the OPA830 is a unity-gain stable, voltage-feedback exceeding that predicted by dividing the 110MHz GBP by
op amp, a wide range of resistor values may be used for 2. Increasing the gain will cause the phase margin to
the feedback and gain setting resistors. The primary limits approach 90° and the bandwidth to more closely approach
on these values are set by dynamic range (noise and the predicted value of (GBP/NG). At a gain of +10, the
distortion) and parasitic capacitance considerations. For a 11MHz bandwidth shown in the Electrical Characteristics
noninverting unity-gain follower application, the feedback agrees with that predicted using the simple formula and
connection should be made with a direct short. the typical GBP of 110MHz.
Below 200Ω, the feedback network will present additional Frequency response in a gain of +2 may be modified to
output loading which can degrade the harmonic distortion achieve exceptional flatness simply by increasing the
performance of the OPA830. Above 1kΩ, the typical noise gain to 3. One way to do this, without affecting the +2
parasitic capacitance (approximately 0.2pF) across the signal gain, is to add an 2.55kΩ resistor across the two
feedback resistor may cause unintentional band limiting in inputs, as shown in Figure 7. A similar technique may be
the amplifier response. used to reduce peaking in unity-gain (voltage follower)
applications. For example, by using a 750Ω feedback
A good rule of thumb is to target the parallel combination resistor along with a 750Ω resistor across the two op amp
of RF and RG (see Figure 3) to be less than about 400Ω. inputs, the voltage follower response will be similar to the
The combined impedance RF || RG interacts with the gain of +2 response of Figure 2. Further reducing the value
inverting input capacitance, placing an additional pole in of the resistor across the op amp inputs will further dampen
the feedback network, and thus a zero in the forward the frequency response due to increased noise gain. The
response. Assuming a 2pF total parasitic on the inverting OPA830 exhibits minimal bandwidth reduction going to
node, holding RF || RG < 400Ω will keep this pole above single-supply (+5V) operation as compared with ±5V. This
200MHz. By itself, this constraint implies that the feedback minimal reduction is because the internal bias control
resistor RF can increase to several kΩ at high gains. This circuitry retains nearly constant quiescent current as the
is acceptable as long as the pole formed by RF and any total supply voltage between the supply pins is changed.
parasitic capacitance appearing in parallel is kept out of
the frequency range of interest.
In the inverting configuration, an additional design INVERTING AMPLIFIER OPERATION
consideration must be noted. RG becomes the input All of the familiar op amp application circuits are available
resistor and therefore the load impedance to the driving with the OPA830 to the designer. See Figure 9 for a typical
source. If impedance matching is desired, RG may be set inverting configuration where the I/O impedances and
equal to the required termination value. However, at low signal gain from Figure 1 are retained in an inverting circuit
inverting gains, the resultant feedback resistor value can configuration. Inverting operation is one of the more
present a significant load to the amplifier output. For common requirements and offers several performance
example, an inverting gain of 2 with a 50Ω input matching benefits. It also allows the input to be biased at VS/2
resistor (= RG) would require a 100Ω feedback resistor, without any headroom issues. The output voltage can be
which would contribute to output loading in parallel with the independently moved to be within the output voltage range
external load. In such a case, it would be preferable to with coupling capacitors, or bias adjustment resistors.

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of −2 circuit of Figure 9 (NG = +2.87) than for the gain of


+5V +2 circuit of Figure 1.
The third important consideration in inverting amplifier
+ design is setting the bias current cancellation resistors on
0.1µF 6.8µF the noninverting input (a parallel combination of
2RT RT = 750Ω). If this resistor is set equal to the total DC
1.5kΩ resistance looking out of the inverting node, the output DC
error, due to the input bias currents, will be reduced to
150Ω
+VS (Input Offset Current) times RF. With the DC blocking
0.1µF 2RT OPA830
2 capacitor in series with RG, the DC source impedance
1.5kΩ
looking out of the inverting mode is simply RF = 750Ω for
Figure 9. To reduce the additional high-frequency noise
50Ω Source RG RF introduced by this resistor and power-supply feed-through,
0.1µF 374Ω 750Ω RT is bypassed with a capacitor.

RM OUTPUT CURRENT AND VOLTAGES


57.6Ω The OPA830 provides outstanding output voltage
capability. For the +5V supply, under no-load conditions at
+25°C, the output voltage typically swings closer than
90mV to either supply rail.
Figure 9. AC-Coupled, G = −2 Example Circuit
The minimum specified output voltage and current
specifications over temperature are set by worst-case
In the inverting configuration, three key design simulations at the cold temperature extreme. Only at cold
considerations must be noted. The first consideration is startup will the output current and voltage decrease to the
that the gain resistor (RG) becomes part of the signal numbers shown in the ensured tables. As the output
channel input impedance. If input impedance matching is transistors deliver power, their junction temperatures will
desired (which is beneficial whenever the signal is coupled increase, decreasing their VBEs (increasing the available
through a cable, twisted pair, long PC board trace, or other output voltage swing) and increasing their current gains
transmission line conductor), RG may be set equal to the (increasing the available output current). In steady-state
required termination value and RF adjusted to give the operation, the available output voltage and current will
desired gain. This is the simplest approach and results in always be greater than that shown in the over-temperature
optimum bandwidth and noise performance. specifications, since the output stage junction
However, at low inverting gains, the resulting feedback temperatures will be higher than the minimum specified
resistor value can present a significant load to the amplifier operating ambient.
output. For an inverting gain of 2, setting RG to 50Ω for To maintain maximum output stage linearity, no output
input matching eliminates the need for RM but requires a short-circuit protection is provided. This will not normally
100Ω feedback resistor. This configuration has the be a problem, since most applications include a series
interesting advantage of the noise gain becoming equal to matching resistor at the output that will limit the internal
2 for a 50Ω source impedance—the same as the power dissipation if the output side of this resistor is
noninverting circuits considered above. The amplifier shorted to ground. However, shorting the output pin
output will now see the 100Ω feedback resistor in parallel directly to the adjacent positive power-supply pin (8-pin
with the external load. In general, the feedback resistor packages) will, in most cases, destroy the amplifier. If
should be limited to the 200Ω to 1.5kΩ range. In this case, additional short-circuit protection is required, consider a
it is preferable to increase both the RF and RG values, as small series resistor in the power-supply leads. This will
shown in Figure 9, and then achieve the input matching reduce the available output voltage swing under heavy
impedance with a third resistor (RM) to ground. The total output loads.
input impedance becomes the parallel combination of RG
and RM. DRIVING CAPACITIVE LOADS
The second major consideration, touched on in the One of the most demanding and yet very common load
previous paragraph, is that the signal source impedance conditions for an op amp is capacitive loading. Often, the
becomes part of the noise gain equation and hence capacitive load is the input of an ADC—including
influences the bandwidth. For the example in Figure 9, the additional external capacitance which may be recom-
RM value combines in parallel with the external 50Ω mended to improve ADC linearity. A high-speed, high
source impedance (at high frequencies), yielding an open-loop gain amplifier like the OPA830 can be very
effective driving impedance of 50Ω || 57.6Ω = 26.8Ω. This susceptible to decreased stability and closed-loop
impedance is added in series with RG for calculating the response peaking when a capacitive load is placed directly
noise gain. The resulting noise gain is 2.87 for Figure 9, as on the output pin. When the primary considerations are
opposed to only 2 if RM could be eliminated as discussed frequency response flatness, pulse response fidelity,
above. The bandwidth will therefore be lower for the gain and/or distortion, the simplest and most effective solution

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is to isolate the capacitive load from the feedback loop by


ENI
inserting a series isolation resistor between the amplifier
output and the capacitive load.
The Typical Characteristic curves show the recommended OPA830 EO
RS
RS versus capacitive load and the resulting frequency IBN
response at the load. Parasitic capacitive loads greater
than 2pF can begin to degrade the performance of the ERS
OPA830. Long PC board traces, unmatched cables, and RF
√ 4kTRS
connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the
√ 4kTRF
recommended series resistor as close as possible to the RG I BI
output pin (see the Board Layout Guidelines section). 4kT
4kT = 1.6E − 20J
RG
at 290_K
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a gain
of +2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring Figure 10. Noise Analysis Model
relatively high values of RS to flatten the response at the The total output spot noise voltage can be computed as the
load. Increasing the noise gain will also reduce the peaking square root of the sum of all squared output noise voltage
(see Figure 7). contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 10:
DISTORTION PERFORMANCE
The OPA830 provides good distortion performance into a
150Ω load. Relative to alternative solutions, it provides
EO + Ǹǒ 2
Ǔ
E NI ) ǒI BNRSǓ ) 4kTRS NG 2 ) ǒI BIR FǓ ) 4kTRFNG
2 2

(4)
exceptional performance into lighter loads and/or
operating on a single +3V supply. Generally, until the Dividing this expression by the noise gain
fundamental signal reaches very high frequency or power (NG = (1 + RF/RG)) will give the equivalent input-referred
levels, the 2nd-harmonic will dominate the distortion with spot noise voltage at the noninverting input, as shown in
a negligible 3rd-harmonic component. Focusing then on Equation 5:

Ǹ
the 2nd-harmonic, increasing the load impedance
ǒ Ǔ
2
improves distortion directly. Remember that the total load IBIRF 4kTRF
ENI ) ǒIBNR SǓ ) 4kTRS )
2 2
includes the feedback network; in the noninverting EN + )
NG NG
configuration (see Figure 3) this is sum of RF + RG, while (5)
in the inverting configuration, only RF needs to be included Evaluating these two equations for the circuit and
in parallel with the actual load. Running differential
component values shown in Figure 1 will give a total output
suppresses the 2nd-harmonic, as shown in the differential
spot noise voltage of 19.3nV/√Hz and a total equivalent
typical characteristic curves.
input spot noise voltage of 9.65nV/√Hz. This is including
the noise added by the resistors. This total input-referred
NOISE PERFORMANCE
spot noise voltage is not much higher than the 9.2nV/√Hz
High slew rate, unity-gain stable, voltage-feedback op specification for the op amp voltage noise alone.
amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 9.2nV/√Hz input voltage
noise for the OPA830 however, is much lower than
DC ACCURACY AND OFFSET CONTROL
comparable amplifiers. The input-referred voltage noise The balanced input stage of a wideband voltage-feedback
and the two input-referred current noise terms (2.8pA/√Hz) op amp allows good output DC accuracy in a wide variety
combine to give low output noise under a wide variety of of applications. The power-supply current trim for the
operating conditions. Figure 10 shows the op amp noise OPA830 gives even tighter control than comparable
analysis model with all the noise terms included. In this products. Although the high-speed input stage does
model, all noise terms are taken to be noise voltage or require relatively high input bias current (typically 5µA out
current density terms in either nV/√Hz or pA/√Hz. of each input terminal), the close matching between them
may be used to reduce the output DC error caused by this
current. This is done by matching the DC source
resistances appearing at the two inputs. Evaluating the
configuration of Figure 3 (which has matched DC input

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resistances), using worst-case +25°C input offset voltage highest possible internal dissipation will occur if the load
and current specifications, gives a worst-case output requires current to be forced into the output at high output
offset voltage equal to: voltages or sourced from the output at low output voltages.
(NG = noninverting signal gain at DC) This puts a high current through a large internal voltage
drop in the output transistors.
±(NG × VOS(MAX)) + (RF × IOS(MAX))
= ±(2 × 7mV) × (375Ω × 1µA) BOARD LAYOUT GUIDELINES
= ±14.38mV Achieving optimum performance with a high-frequency
A fine-scale output offset null, or DC operating point amplifier like the OPA830 requires careful attention to
adjustment, is often required. Numerous techniques are board layout parasitics and external component types.
available for introducing DC offset control into an op amp Recommendations that will optimize performance include:
circuit. Most of these techniques are based on adding a DC a) Minimize parasitic capacitance to any AC ground for
current through the feedback resistor. In selecting an offset all of the signal I/O pins. Parasitic capacitance on the
trim method, one key consideration is the impact on the output and inverting input pins can cause instability: on the
desired signal path frequency response. If the signal path noninverting input, it can react with the source impedance
is intended to be noninverting, the offset control is best to cause unintentional bandlimiting. To reduce unwanted
applied as an inverting summing signal to avoid interaction capacitance, a window around the signal I/O pins should
with the signal source. If the signal path is intended to be be opened in all of the ground and power planes around
inverting, applying the offset control to the noninverting those pins. Otherwise, ground and power planes should
input may be considered. Bring the DC offsetting current be unbroken elsewhere on the board.
into the inverting input node through resistor values that
are much larger than the signal path resistors. This will b) Minimize the distance ( < 0.25”) from the power-supply
insure that the adjustment circuit has minimal effect on the pins to high-frequency 0.1µF decoupling capacitors. At the
loop gain and hence the frequency response. device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
THERMAL ANALYSIS
the pins and the decoupling capacitors. Each power-
Maximum desired junction temperature will set the supply connection should always be decoupled with one
maximum allowed internal power dissipation, as of these capacitors. An optional supply decoupling
described below. In no case should the maximum junction capacitor (0.1µF) across the two power supplies (for
temperature be allowed to exceed 150°C. bipolar operation) will improve 2nd-harmonic distortion
Operating junction temperature (TJ) is given by performance. Larger (2.2µF to 6.8µF) decoupling
TA + P D × q JA. The total internal power dissipation (P D) capacitors, effective at lower frequency, should also be
is the sum of quiescent power (P DQ ) and additional used on the main supply pins. These may be placed
power dissipated in the output stage (P DL ) to deliver load somewhat farther from the device and may be shared
power. Quiescent power is simply the specified no-load among several devices in the same area of the PC board.
supply current times the total supply voltage across the c) Careful selection and placement of external
part. PDL will depend on the required output signal and components will preserve the high-frequency perfor-
load; though, for resistive loads connected to mance. Resistors should be a very low reactance type.
mid-supply (V S/2), PDL is at a maximum when the output Surface-mount resistors work best and allow a tighter
is fixed at a voltage equal to VS/4 or 3V S/4. Under this overall layout. Metal film or carbon composition
condition, PDL = V S2 /(16 × R L ), where RL includes axially-leaded resistors can also provide good high-
feedback network loading. frequency performance. Again, keep their leads and PC
Note that it is the power in the output stage, and not into the board traces as short as possible. Never use wire-wound
load, that determines internal power dissipation. type resistors in a high-frequency application. Since the
output pin and inverting input pin are the most sensitive to
As a worst-case example, compute the maximum TJ using parasitic capacitance, always position the feedback and
an OPA830 (SOT23-5 package) in the circuit of Figure 1 series output resistor, if any, as close as possible to the
operating at the maximum specified ambient temperature output pin. Other network components, such as
of +85°C and driving a 150Ω load at mid-supply. noninverting input termination resistors, should also be
PD = 10V × 3.9mA + 52/(16 × (150Ω || 750Ω)) = 51.5mW placed close to the package. Where double-side
component mounting is allowed, place the feedback
Maximum TJ = +85°C + (0.051W × 150°C/W) = 93°C.
resistor directly under the package on the other side of the
Although this is still well below the specified maximum board between the output and inverting input pins. Even
junction temperature, system reliability considerations with a low parasitic capacitance shunting the external
may require lower ensured junction temperatures. The resistors, excessively high resistor values can create

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significant time constants that can degrade performance. e) Socketing a high-speed part is not recommended.
Good axial metal film or surface-mount resistors have The additional lead length and pin-to-pin capacitance
approximately 0.2pF in shunt with the resistor. For resistor introduced by the socket can create an extremely
values > 1.5kΩ, this parasitic capacitance can add a pole troublesome parasitic network which can make it almost
and/or zero below 500MHz that can effect circuit impossible to achieve a smooth, stable frequency
operation. Keep resistor values as low as possible response. Best results are obtained by soldering the
consistent with load driving considerations. The 750Ω OPA830 onto the board.
feedback used in the Typical Characteristics is a good
starting point for design. INPUT AND ESD PROTECTION
d) Connections to other wideband devices on the board The OPA830 is built using a very high-speed complemen-
may be made with short direct traces or through onboard tary bipolar process. The internal junction breakdown
transmission lines. For short connections, consider the voltages are relatively low for these very small geometry
trace and the input to the next device as a lumped devices. These breakdowns are reflected in the Absolute
capacitive load. Relatively wide traces (50mils to 100mils) Maximum Ratings table. All device pins are protected with
should be used, preferably with ground and power planes internal ESD protection diodes to the power supplies, as
opened up around them. Estimate the total capacitive load shown in Figure 11.
and set RS from the typical characteristic curve
Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
+VCC
OPA830 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (increasing the External Internal
unloaded phase margin). If a long trace is required, and the Pin Circuitry
6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched
− VCC
impedance transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω Figure 11. Internal ESD Protection
environment is normally not necessary onboard, and in
fact, a higher impedance environment will improve These diodes provide moderate protection to input
distortion as shown in the distortion versus load plots. With overdrive voltages above the supplies as well. The
a characteristic board trace impedance defined (based on protection diodes can typically support 30mA continuous
board material and trace dimensions), a matching series current. Where higher currents are possible (that is, in
resistor into the trace from the output of the OPA830 is systems with ±15V supply parts driving into the OPA830),
used as well as a terminating shunt resistor at the input of current-limiting series resistors should be added into the
the destination device. Remember also that the two inputs. Keep these resistor values as low as possible,
terminating impedance will be the parallel combination of since high values degrade both noise performance and
the shunt resistor and the input impedance of the frequency response.
destination device; this total effective impedance should
be set to match the trace impedance. If the 6dB attenuation
of a doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source end
only. Treat the trace as a capacitive load in this case and
set the series resistor value as shown in the typical
characteristic curve Recommended RS vs Capacitive
Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.

27
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Revision History

DATE REV PAGE SECTION DESCRIPTION

8/08 F 2 Absolute Maximum Ratings Changed Storage Temperature minimum value from −40°C to −65°C.
8/07 E 1 Features Changed 550V/ns to 550V/µs.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

28
PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA830ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 830
OPA830IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 A72
& no Sb/Br)
OPA830IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 A72
& no Sb/Br)
OPA830IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 A72
& no Sb/Br)
OPA830IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 830
OPA830IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 830
OPA830IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 830

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA830 :

• Enhanced Product: OPA830-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA830IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA830IDR SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN


ARROUND ARROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/C 04/2017

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.


5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
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