Linear Technology: Application Note 87 November 2000

Application Note 87
November 2000
Linear Technology Magazine Circuit Collection, Volume V

Data Conversion, Interface and Signal Conditioning Products
Richard Markell, Editor
INTRODUCTION
Application Note 87 is the fifth in a series that excerpts instrumentation circuits. There are also several circuits
useful circuits from Linear Technology magazine to pre- that cannot be so neatly categorized. So, without further
serve them for posterity. This application note highlights ado, I’ll let the authors describe their circuits.
data conversion, interface and signal conditioning circuits
from issue VI:1 (February 1996) through issue VIII:4 Note: Article Titles appear in this application note exactly
(November 1998). Like its predecessor, AN67, this Appli- as they originally appeared in Linear Technology maga-
cation Note includes circuits for high speed video, inter- zine. This may result in some inconsistency in the usage
face and hot swap circuits, active RC and switched capaci- of terminology.
tor filter circuitry and a variety of data conversion and
TABLE OF CONTENTS
Introduction ......................................................................................................................................................... 1
DATA CONVERTERS
The LTC®1446 and LTC1446L: World’s First Dual 12-Bit DACs in SO-8 Packages ............................................... 3
Multichannel A/D Uses a Single Antialiasing Filter................................................................................................ 4
LTC1454/54L and LTC1458/58L: Dual and Quad 12-Bit, Rail-to-Rail, Micropower DACs .................................... 5
Micropower ADC and DAC in SO-8 Give PC 12-Bit Analog Interface .................................................................... 7
The LTC1594 and LTC1598: Micropower 4- and 8-Channel 12-Bit ADCs ........................................................... 10
MUX the LTC1419 Without Software ................................................................................................................. 13
The LTC1590 Dual 12-Bit DAC is Extremely Versatile......................................................................................... 14
New 16-Bit SO-8 DAC Has 1LSB Max INL and DNL Over Industrial Temperature .............................................. 16
LTC1659, LTC1448: Smallest Rail-to-Rail 12-Bit DACs Have Lowest Power ...................................................... 18
An SMBus-Controlled 10-Bit, Current Output, 50µA Full-Scale DAC .................................................................. 19
INTERFACE CIRCUITS
Simple Resistive Surge Protection for Interface Circuits .................................................................................... 20
The LTC1343 and LTC1344 Form a Software-Selectable Multiple-Protocol Interface Port
Using a DB-25 Connector ................................................................................................................................... 22
The LT1328: a Low Cost IrDA Receiver Solution for Data Rates up to 4Mbps ................................................... 34
LTC1387 Single 5V RS232/RS485 Multiprotocol Transceiver ............................................................................ 36
A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards ......................................................... 37
Net1 and Net2 Serial Interface Chip Set Supports Test Mode............................................................................. 44
OPERATIONAL AMPLIFIERS/VIDEO AMPLIFIERS
LT1490/LT1491 Over-the-Top™ Dual and Quad Micropower Rail-to-Rail Op Amps........................................... 46
The LT1210: A 1-Ampere, 35MHz Current Feedback Amplifier........................................................................... 47
The LT1207: An Elegant Dual 60MHz, 250mA Current Feedback Amplifier ........................................................ 50
AN87-1
Application Note 87
Micropower, Dual and Quad JFET Op Amps Feature C-Load™ Capability
and PicoAmpere Input Bias Currents.................................................................................................................. 54
The LT1210: High Power Op Amp Yields Higher Voltage and Current ................................................................ 56
New Rail-to-Rail Amplifiers: Precision Performance from Micropower to High Speed ....................................... 59
LT1256 Voltage-Controlled Amplitude Limiter ................................................................................................... 61
The LT1495/LT1496: 1.5µA Rail-to-Rail Op Amps ............................................................................................. 62
Send Camera Power and Video on the Same Coax Cable ................................................................................... 64
200µA, 1.2MHz Rail-to-Rail Op Amps Have Over-The-Top Inputs ...................................................................... 65
Low Distortion Rail-to-Rail Op Amps Have 0.003% THD with 100kHz Signal .................................................... 66
The LT1167: Precision, Low Cost, Low Power Instrumentation Amplifier Requires
a Single Gain-Set Resistor .................................................................................................................................. 67
Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply ................................................ 70
LT1468: An Operational Amplifier for Fast, 16-Bit Systems ............................................................................... 71
TELECOMMUNICATIONS CIRCUITS
How to Ring a Phone with a Quad Op Amp ........................................................................................................ 73
A Low Distortion, Low Power, Single-Pair HDSL Driver Using the LT1497 ........................................................ 79
COMPARATORS
Ultralow Power Comparators Include Reference ................................................................................................ 80
A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for 3V/5V Operation ................................................ 82
INSTRUMENTATION CIRCUITS
LTC1441-Based Micropower Voltage-to-Frequency Converter ........................................................................... 86
Bridge Measures Small Capacitance in Presence of Large Strays ...................................................................... 87
Water Tank Pressure Sensing, a Fluid Solution .................................................................................................. 89
0.05µV/°C Chopped Amplifier Requires Only 5µA Supply Current ..................................................................... 92
4.5ns Dual-Comparator-Based Crystal Oscillator has 50% Duty Cycle and Complementary Outputs ................. 93
LTC1531 Isolated Comparator............................................................................................................................ 94
FILTERS
The LTC1560-1: A 1MHz/500kHz Continuous-Time, Low Noise, Elliptic Lowpass Filter .................................... 96
The LTC1067 and LTC1067-50: Universal 4th Order Low Noise, Rail-to-Rail Switched Capacitor Filters ........... 98
Universal Continuous-Time Filter Challenges Discrete Designs ........................................................................ 102
High Clock-to-Center Frequency Ratio LTC1068-200 Extends Capabilities of Switched Capacitor
Highpass Filter ................................................................................................................................................. 104
Clock-Tunable, High Accuracy, Quad 2nd Order, Analog Filter Building Blocks................................................ 106
MISCELLEANEOUS
Biased Detector Yields High Sensitivity with Ultralow Power Consumption ..................................................... 110
Zero-Bias Detector Yields High Sensitivity with Nanopower Consumption....................................................... 111
Transparent Class-D Amplifiers Featuring the LT1336 ..................................................................................... 112
Single-Supply Random Code Generator ........................................................................................................... 118
APPENDIX A: COMPONENT VENDOR CONTACTS ......................................................................... 120
INDEX ............................................................................................................................ 123
, LTC, and LT are registered trademarks of Linear Technology Corporation; Adaptive Power, Burst Mode, C-Load, FilterCAD, No RSENSE, Operational Filter, Over-The-Top, PolyPhase, PowerPath
and UltraFast are trademarks of Linear Technology Corporation. Gelcell is a trademark of Johnson Controls, Inc.; Kool Mµ is a registered trademark of Magnetics, Inc.; Pentium is a registered
trademark of Intel Corp.; VERSA-PAC is a trademark of Coiltronics, Inc.
AN87-2
Application Note 87
Data Converters
LTC1446L has an output swing of 0V to 2.5V. It can
THE LTC1446 AND LTC1446L: WORLD’S FIRST operate on a single supply with a wide range of 2.7V to
DUAL 12-BIT DACS IN SO-8 PACKAGES 5.5V. It dissipates 1.35mW (ICC typical = 450µA) at a 3V
by Hassan Malik and Jim Brubaker supply.
Dual 12-Bit Rail-to-Rail Performance in a Tiny SO-8 An Autoranging 8-Channel ADC with Shutdown
The LTC1446 and LTC1446L are dual 12-bit, single-sup- Figure 1 shows how to use an LTC1446 to make an
ply, rail-to-rail voltage output digital-to-analog convert- autoranging ADC. The microprocessor sets the reference
ers. Both of these parts include an internal reference and span and the common pin for the analog input by loading
two DACs with rail-to-rail output buffer amplifiers, packed the appropriate digital code into the LTC1446. VOUTA
in a small, space-saving 8-pin SO or PDIP package. A controls the common pin for the analog inputs to the
power-on reset initializes the outputs to zero-scale at LTC1296 and VOUTB controls the reference span by setting
power-up. the REF+ pin on the LTC1296. The LTC1296 has a shut-
down pin that goes low in shutdown mode. This will turn
The LTC1446 has an output swing of 0V to 4.095V, making off the PNP transistor supplying power to the LTC1446.
each LSB equal to 1mV. It operates from a single 4.5V to The resistor and capacitor on the LTC1446 outputs act as
5.5V supply, dissipating 3.5mW (ICC typical = 700µA). The a lowpass filter for noise.
22µF
+
5V
VCC
CS CH0
DOUT 8 ANALOG
CLK INPUT CHANNELS
LTC1296
µP
DIN CH7
COM
REF +
SSO REF –
74HC04
47k 47k
5V
0.1µF
2N3906
100Ω
CLK VOUTB
0.1µF
DIN VCC
LTC1446
CS/LD GND
100Ω
DOUT VOUTA
0.1µF
Figure 1. An Autoranging 8-Channel ADC with Shutdown
AN87-3
Application Note 87
A Wide-Swing, Bipolar-Output DAC with
Digitally Controlled Offset
Figure 2 shows how to use an LTC1446 and an LT1077 to be set by loading the appropriate digital code for DAC A,
make a wide bipolar-output-swing 12-bit DAC with an sets the offset. As this value changes, the transfer curve
offset that can be digitally programmed. VOUTA, which can for the output moves up and down, as shown in the figure.
5V
8.192
0.1µF
VOUT VOUTA = 0V
(ZERO SCALE)
CLK VOUTB 15V 4.096
4.99k
1%
VOUTA = 2.048V
DIN VCC
LTC1446
+ (MID SCALE)
µP 10k 0 DIN
LT1077 VOUT = 2 { VOUTB–VOUTA }
CS/LD GND 1%
– VOUTA = 4.096V
(FULL SCALE)
DOUT VOUTA –4.096
–15V
49.9k
1%
TO DIN OF NEXT DAC
100k –8.192
1%
Figure 2. A Wide-Swing, Bipolar Output DAC with Digitally Controlled Offset
MULTICHANNEL A/D USES

A SINGLE ANTIALIASING FILTER
by LTC Applications Staff
The circuit in Figure 3 demonstrates how the LTC1594’s The combined MUX and A/D errors result in an integral
independent analog multiplexer can simplify the design of nonlinearity error of ±3LSB (maximum) and a differential
a 12-bit data acquisition system. All four channels are nonlinearity error of ±0.75LSB (maximum). The typical
MUXed into a single 1kHz, fourth-order Sallen-Key anti- signal-to-noise plus distortion ratio is 68dB, with approxi-
aliasing filter, which is designed for single-supply opera- mately −78dB of total harmonic distortion. The LTC1594
tion. Since the LTC1594’s data converter accepts inputs is programmed through a 4-wire serial interface that
from ground to the positive supply, rail-to-rail op amps allows efficient data transfer to a wide variety of micro-
were chosen for the filter to maximize dynamic range. The processors and microcontrollers. Maximum serial clock
LT1368 dual rail-to-rail op amp is compensated for the speed is 200kHz, which corresponds to a 10.5kHz sam-
0.1µF load capacitors (C1 and C2) that help reduce the pling rate.
amplifier’s output impedance and improve supply rejec-
tion at high frequencies. The filter contributes less than The complete circuit consumes approximately 800µA
1LSB of error due to offsets and bias currents. The filter’s from a single 5V supply. For ratiometric measurements,
noise and distortion are less than −72dB for a 100Hz, the A/D’s reference can also be taken from the 5V supply.
2VP-P offset sine input. Otherwise, an external reference should be used.
AN87-4
Application Note 87
5V
0.015µF
0.1µF
7.5k 7.5k
+
1/2
5V 0.03µF
LT1368
–
C2
0.1µF
1µF
CH0 VCC
7.5k
ANALOG CH1 MUX OUT +
7.5k 1/2
INPUTS 0.015µF
CH2 DIN LT1368
C1
LTC1594 – 0.1µF
CH3 CS 0.03µF
SHA IN CLK
VREF VCC DATA IN
0.1µF COM DOUT CLOCK
GND CS DATA OUT
CHIP SELECT
Figure 3. Simple Data Acquisition System Takes Advantage of the LTC1594’s

MUX OUT/SHA IN Loop to Filter Analog Signals Prior to A/D Conversion
LTC1454/54L AND LTC1458/58L: DUAL AND QUAD 5V and 3V Single Supply and Micropower
12-BIT, RAIL-TO-RAIL, MICROPOWER DACS
by Hassan Malik and Jim Brubaker The LTC1454 and LTC1458 operate from a single 4.5V to
5.5V supply. The LTC1454 dissipates 3.5mW (ICC typical
Dual and Quad Rail-to-Rail DACs Offer = 700µA), whereas the LTC1458 dissipates 6.5mW (ICC
Flexibility and Performance typical = 1.3mA). There is an onboard reference of 2.048V
and a nominal full scale of 4.095V when using the onboard
The LTC1454 and LTC1454L are dual 12-bit, single sup- reference and a gain-of-2 configuration.
ply, rail-to-rail voltage-output digital-to-analog convert-
ers. The LTC1458 and LTC1458L are quad versions of this The LTC1454L and LTC1458L operate on a single supply
family. These DACs have an easy-to-use, SPI-compatible with a wide range of 2.7V to 5.5V. The LTC1454L dissi-
interface. A CLR pin and power-on-reset both reset the pates 1.35mW (ICC typical = 450µA), whereas the LTC1458L
DAC outputs to zero scale. DNL is guaranteed to be less dissipates 2.4mW (ICC typical = 800µA) from a 3V supply.
than 0.5LSB. Each DAC has its own rail-to-rail voltage There is a 1.22V onboard reference and a convenient full
output buffer amplifier. The onboard reference is brought scale of 2.5V when using the onboard reference and a
out to a separate pin and can be connected to the REFHI gain-of-2 configuration.
pins of the DACs. There is also a REFLO pin that can be
used to offset the DAC range. For further flexibility the Flexibility Allows a Host of Applications
×1/×2 pin for each DAC allows the user to select a gain of
either 1 or 2. The LTC1454/54L are available in 16-pin These products can be used in a wide range of applica-
PDIP and SO packages, and the LTC1458/58L are available tions, including digital calibration, industrial process con-
in 28-pin SO or SSOP packages. trol, automatic test equipment, cellular telephones and
portable, battery-powered systems.
AN87-5
Application Note 87
A 12-Bit DAC with Digitally Programmable The transfer characteristic is:
Full Scale and Offset
VOUTC = 2 × [DC × (2 × DB – DA) + DA] × REFOUT
Figure 4 shows how to use one LTC1458 to make a 12-bit
where REFOUT = The reference output
DAC with a digitally programmable full scale and offset.
DAC A and DAC B are used to control the offset and full DA = (DAC A digital code)/4096 this sets the offset
scale of DAC C. DAC A is connected in a ×1 configuration
DB = (DAC B digital code)/4096 this sets the full scale
and controls the offset of DAC C by moving REFLOC above
ground. The minimum value to which this offset can be DC = (DAC C digital code)/4096
programmed is 10mV. DAC B is connected in a ×2
configuration and controls the full scale of DAC-C by A Single-Supply, 4-Quadrant Multiplying DAC
driving REFHIC . Note that the voltage at REFHIC must be
less than or equal to VCC/2, corresponding to DAC B’s The LTC1454L can also be used for four-quadrant multi-
code ≤ 2,500 for VCC = 5V, since DAC-C is being operated plying with an offset signal ground of 1.22V. This applica-
in ×2 mode for full rail-to-rail output swing. tion is shown in Figure 5. The inputs are connected to
REFHIB or REFHIA and have a 1.22V amplitude around a
signal ground of 1.22V. The outputs will swing from 0V to
2.44V, as shown by the equation with the figure.
5V
0.1µF
LTC1458L/LTC1458
X1/X2C VCC 5V
X1/X2 B VOUT B VOUT B
VOUT VOUTC X1/X2B 0.1µF
CS/LD VOUTB CLR VCC
DIN CLR CLK CLK REFHI B VIN B: 1.22V ± 1.22V

REFHIC REFHIB
DIN DIN GND
GND GND LTC1454L
CS/LD CS/LD REFLO
REFLOC REFLOB
500Ω REFLOD REFLOA DOUT REFHI A VIN A: 1.22V ± 1.22V
REFHI D REFHIA 1.22V

X1/X2 A REF
DOUT REFOUT
VOUT A VOUT A VCC 5k
CLK N/C
N/C VOUTA
( )
VOUTD X1/X2A
VO = (VIN – VREF) GAIN
DIN – 1 +1 + V
REF
X1/X2D VCC A/B 4096 1454_4.eps
= ( VIN – 1.22 )( D
)
2.05 IN –1.05 + 1.22V
4096
Figure 4. A 12-Bit DAC with Digitally Controlled Figure 5. Single-Supply, 4-Quadrant Multiplying DAC
Zero Scale and Full Scale
AN87-6
Application Note 87
MICROPOWER ADC AND DAC IN SO-8 to transfer data to the DAC and ADC, CTS is used to receive
GIVE PC 12-BIT ANALOG INTERFACE conversion results from the LTC1298 and the signal on TX
by LTC Applications Staff selects either the LTC1446 or the LTC1298 to receive input
data. The LTC1298’s and LTC1446’s low power dissipa-
Needing to add two channels of simple, inexpensive, low
tion allows the circuit to be powered from the serial port.
powered, compact analog input/output to a PC computer,
The TX and RTS lines charge capacitor C4 through diodes
The LTC1298 ADC and LTC1446 DAC were chosen. The
D3 and D4. An LT1021-5 regulates the voltage to 5V.
LTC1298 and the LTC1446 are the first SO-8 packaged 2-
Returning the TX and RTS lines to a logic high after
channel devices of their kind. The LTC1298 draws just
sending data to the DAC or completion of an ADC conver-
340µA. A built-in auto shutdown feature further reduces
sion provides constant power to the LT1021-5.
power dissipation at reduced sampling rates (to 30µA at
1ksps). Operating on a 5V supply, the LTC1446 draws just
Using a 486-33 PC, the throughput was 3.3ksps for the
1mA (typ). Although the application shown is for PC data
LTC1298 and 2.2ksps for the LTC1446. Your mileage may
acquisition, these two converters provide the smallest,
vary.
lowest power solutions for many other analog I/O applica-
tions.
Listing 1 is C code that prompts the user to either read a
conversion result from the ADC’s CH0 or write a data word
The circuit shown in Figure 6 connects to a PC’s serial to both DAC channels.
interface using four interface lines: DTR, RTS, CTS and TX.
DTR is used to transmit the serial clock signal, RTS is used
5V
LT1021-5
6 2
LTC1298 1/2 74HC74 4 C4

4 x 1N914 47µF 150µF
1 8 2 5
CS VCC D Q
+
510Ω 510Ω 2 7 4 1
INPUT 1 CH0 CLK 0.1µF PR CLR
+
3 6 3 6
INPUT 2 CH1 DOUT CK Q
510Ω 510Ω 4 5
GND DIN
D3 D4
1N914 1N914
4 3 2 1 51k SELECT
LTC1446 1/2 74HC74 TX
1 8 2 5 51k DIN
CLK VOUTB D Q 8 9 6 5
2 7 4 1 RTS
DIN VCC PR CLR
3 6 0.1µF 3 6 12 13 51k SCLK
CS/LD GND CK Q DTR
4 5
DOUT VOUTA 7 14 11 10 DOUT
CTS
AOUT1 DI1466_01.eps
0.1µF
AOUT2
5V
Figure 6. Communicating Over the Serial Port, the LTC1298 and LTC1446 in SO-8
Create a Simple, Low Power, 2-Channel Analog Interface for PCs
Listing 1. C Code to Configure the Analog Interface
#define port 0x3FC /* Control register, RS232 */

#define inprt 0x3FE /* Status reg. RS232 */
#define LCR 0x3FB /* Line Control Register */
#define high 1
#define low 0
#define Clock 0x01 /* pin 4, DTR */
#define Din 0x02 /* pin 7, RTS */
AN87-7
Application Note 87
#define Dout 0x10 /* pin 8, CTS input */
#include<stdio.h>
#include<dos.h>
#include<conio.h>
/* Function module sets bit to high or low */
void set_control(int Port,char bitnum,int flag)
{
char temp;
temp = inportb(Port);
if (flag==high)
temp |= bitnum; /* set output bit to high */
else
temp &= ~bitnum; /* set output bit to low */
outportb(Port,temp);
}
/* This function brings CS high or low (consult the schematic) */
void CS_Control(direction)
{
if (direction)
{
set_control(port,Clock,low); /* set clock high for Din to be read */
set_control(port,Din,low); /* set Din low */
set_control(port,Din,low); /* set Din high to make CS goes high */
}
else {
outportb(port, 0x01); /* set Din & clock low */
Delay(10);
outportb(port, 0x03); /* Din goes high to make CS go low */
}
}
/* This function outputs a 24-bit (2x12) digital code to LTC1446L */
void Din_(long code,int clock)
{
int x;
for(x = 0; x<clock; ++x)
{
code <<= 1; /* align the Din bit */
if (code & 0x1000000)
{
set_control(port,Clock,high); /* set Clock low */
set_control(port,Din,high); /* set Din bit high */
}
else {
set_control(port,Clock,high); /* set Clock low */
set_control(port,Din,low); /* set Din low */
}
set_control(port,Clock,low); /* set Clock high for DAC to latch */
}
AN87-8
Application Note 87
}
/* Read bit from ADC to PC */
Dout_()
{
int temp, x, volt =0;
for(x = 0; x<13; ++x)
{
set_control(port,Clock,high);
set_control(port,Clock,low);
temp = inportb(inprt); /* read status reg. */
volt <<= 1; /* shift left one bit for serial transmission
*/
if(temp & Dout)
volt += 1; /* add 1 if input bit is high */
}
return(volt & 0xfff);
}
/* menu for the mode selection */
char menu()
{
printf(“Please select one of the following:\na: ADC\nd: DAC\nq: quit\n\n”);
return (getchar());
}
void main()
{
long code;
char mode_select;
int temp,volt=0;
/* Chip select for DAC & ADC is controlled by RS232 pin 3 TX line. When LCR’s bit 6 is set,
the DAC is selected and the reverse is true for the ADC. */
outportb(LCR,0x0); /* initialize DAC */
outportb(LCR,0x64); /* initialize ADC */
while((mode_select = menu()) != ‘q’)
{
switch(mode_select)
{
case ‘a’:
{
outportb(LCR,0x0); /* selecting ADC */
CS_Control(low); /* enabling the ADC CS */
Din_(0x680000, 0x5); /* channel selection */
volt = Dout_();
outportb(LCR,0x64); /* bring CS high */
set_control(port,Din,high); /* bring Din signal high */
printf(“\ncode: %d\n”,volt);
}
break;
case ‘d’:
AN87-9
Application Note 87
{
printf(“Enter DAC input code (0 – 4095):\n”);
scanf(“%d”, &temp);
code = temp;
code += (long)temp << 12; /* converting 12-bit to 24-bit word */
outportb(LCR,0x64); /* selecting DAC */
CS_Control(low); /* CS enable */
Din_(code,24); /* loading digital data to DAC */
outportb(LCR,0x0); /* bring CS high */
outportb(LCR,0x64); /* disabling ADC */
set_control(port,Din,high); /* bring Din signal high */
}
break;
}
}
}
THE LTC1594 AND LTC1598: MICROPOWER

4- AND 8-CHANNEL 12-BIT ADCS includes a simple, efficient serial interface that reduces
by Marco Pan interconnects and, thereby, possible sources of corrupt-
ing digital noise. Reduced interconnections also reduce
Micropower ADCs in Small Packages board size and allow the use of processors having fewer
I/O pins, both of which help reduce system costs.
The LTC1594 and LTC1598 are micropower 12-bit ADCs
that feature a 4- and 8-channel multiplexer, respectively. The LTC1594 and LTC1598 include an auto shutdown
The LTC1594 is available in a 16-pin SO package and the feature that reduces power dissipation when the converter
LTC1598 is available in a 24-pin SSOP package. Each ADC is inactive (whenever the CS signal is a logic high).
ANALOG INPUTS 5V
0V TO 5V 1 24 C6
RANGE CH5 CH4 0.015µF
1µF
2 23
CH6 CH3 R4, 7.5k R2, 7.5k
3
CH7 CH2
22 +
4 1/2 C4
21
GND CH1 LT1368 0.03µF
5 20 C2
CLK LTC1598 CH0 5V 0.1µF
–
6 19
CS MUX VCC
7 18 1µF
DIN MUXOUT
8 17
COM ADCIN
9 16 R1, 7.5k R3, 7.5k
GND VREF +
10 15 1/2
CS ADC VCC C5
11 14 0.015µF LT1368
C1
DOUT CLK C3 – 0.1µF
12 13 0.03µF
NC NC
DATA OUT
DATA IN 1598_02.eps
CHIP SELECT
CLOCK
Figure 7. Simple Data Acquisition System Takes Advantage of the LTC1598’s

MUX OUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion
AN87-10
Application Note 87
5V
1µF
5V
+
LTC1391
1 16 +
CH0 V+ 1µF
2 15
CH1 D +
3 14
CH2 V– 1/2 LT1368 5V
4 13
CH3 DOUT 0.1µF
5 12 – +
CH4 DIN
6 11 17 16 15, 19 1µF
CH5 CS ADCIN VREF VCC
7 10
CH6 CLK 64R 20 CH0
8 9
CH7 GND 32R 21 CH1 10
CS ADC
16R 22 CH2 6
CS MUX
8R 23 CH3 8-CHANNEL 12-BIT 5, 14
+ CLK
4R 24 CH4 MUX SAMPLING 11 µP/µC
ADC DOUT
2R 1 CH5 7
R 2 CH6
– DIN
R 3 CH7
LTC1598
12
18 MUXOUT NC
8 COM 13
NC
GND
4, 9
1598_03.eps
Figure 8. Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration
MUXOUT/ADCIN Loop signal and its output is applied to ADCIN. The LT1368 rail-
Economizes Signal Conditioning to-rail op amps used in the filter will, when lightly loaded
as in this application, swing to within 8mV of the positive
The MUXOUT and ADCIN pins form a very flexible external supply voltage. Since only one circuit is used for all
loop that allows PGA and/or processing analog input channels, each channel sees the same filter characteristics.
signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only Using MUXOUT/ADCIN Loop as PGA
one circuit is needed instead of one for each channel.
Figure 7 shows the loop being used to antialias filter Combined with the LTC1391 (as shown in Figure 8) the
several analog inputs. The output signal of the selected LTC1598’s MUXOUT/ADCIN loop and an LT1368 can be
MUX channel, present on the MUXOUT pin, is applied to used to create an 8-channel PGA with eight noninverting
R1 of the Sallen-Key filter. The filter bandlimits the analog gains for each channel. The output of the LT1368 drives
the ADCIN and the resistor ladder. The resistors above the
Table 1. PGA Gain for Each MUX Channel of Figures 8 and 9 selected MUX channel form the feedback for the LT1368.
Mux Channel Noninverting Gain Inverting Gain The loop gain for this amplifier is (RS1/RS2) + 1. RS1 is the
0 1 –1 summation of the resistors above the selected MUX chan-
1 2 –2 nel and RS2 is the summation of the resistors below the
2 4 –4 selected MUX channel. If CH0 is selected, the loop gain is
3 8 –8 1 since RS1 is 0. Table 1 shows the gain for each MUX
4 16 –16 channel. The LT1368 dual rail-to-rail op amp is designed
5 32 –32 to operate with 0.1µF load capacitors. These capacitors
6 64 –64 provide frequency compensation for the amplifiers, help
7 128 –128 reduce the amplifiers’ output impedance and improve
AN87-11
Application Note 87
5V
supply rejection at high frequencies. Because the LT1368’s
IB is low, the RON of the selected channel will not affect the +
loop gain given by the formula above. In the case of the 1/2 LT1368
0.1µF
inverting configuration of Figure 9, the selected channel’s –
RON will be added to the resistor that sets the loop gain.
5V
128R
8-Channel, Differential, 12-Bit A/D System
Using the LTC1391 and LTC1598 LTC1598 18 17 16 15, 19 1µF
MUXOUT ADCIN VREF VCC
128R 20 CH0
The LTC1598 can be combined with the LTC1391 8-
64R 21 CH1 10
channel, serial-interface analog multiplexer to create a 32R 22 CH2
CS ADC
6
CS MUX
differential A/D system. Figure 10 shows the complete 8- 16R 23 CH3 12-BIT
CLK
5, 14
+ SAMPLING
channel, differential A/D circuit. The system uses the 8R 24 CH4
ADC DIN
7
4R 1 CH5 11
LTC1598’s MUX as the noninverting input multiplexer 2R 2 CH6
– DOUT
and the LTC1391 as inverting input multiplexer. The R 3 CH7 NC

12
LTC1598’s MUXOUT drives the ADCIN directly. The 8 COM NC

13
GND
inverting multiplexer’s output is applied to the LTC1598’s 4, 9 1598_04.eps
COM input. The LTC1598 and LTC1391 share the CS, DIN,
and CLK control signals. This arrangement simultaneously
selects the same channel on each multiplexer and maxi-
mizes the system’s throughput. The dotted-line connec- Figure 9. Using the MUXOUT/ADCIN Loop of the LTC1598
tion daisy-chains the MUXes of the LTC1391 and LTC1598 to Form a PGA with Eight Inverting Gains
together. This configuration provides the flexibility to
select any channel in the noninverting input MUX with
respect to any channel in the inverting input MUX. This
5V
allows any combination of signals applied to the inverting
and noninverting MUX inputs to be routed to the ADC for LTC1598 18 17 16 15, 19 1µF
conversion. MUXOUT ADCIN VREF VCC
20 CH0
21 CH1 10
CS ADC
22 CH2 6
CS MUX
23 CH3 8-CHANNEL 12-BIT 5, 14
5V + CLK
24 CH4 MUX SAMPLING 7
ADC DIN
1 CH5 11
1µF 2 CH6
– DOUT
LTC1391
3 CH7 12
1 16 NC
CH0 CH0 V+ 13
2 15 8 COM NC
CH1 D GND
3 – 14
CH2 V 4, 9 1598_05.eps
4 13
CH3 DOUT
5 12
CH4 DIN
6 11
CH5 CS
7 10
CH6 CLK
8 9
CH7 CH7 GND
DIN
CLK
CS
DOUT
Figure 10. Using the LTC1598 and LTC1391 as an 8-Channel, Differential 12-Bit ADC System: Opening the Indicated Connection
and Shorting the Dashed Connection Daisy-Chains the External and Internal MUXes, Increasing Channel-Selection Flexibility.
AN87-12
Application Note 87
MUX THE LTC1419 WITHOUT SOFTWARE process repeats. At any time, the input multiplexer channel
by LTC Applications Staff can be reset to 0 by applying a logic-high pulse to pin 7 of
the counter.
The circuit shown in Figure 11 uses hardware instead of
software routines to select multiplexer channels in a data
This data acquisition circuit has a throughput of 800ksps
acquisition system. The circuit features the LTC1419
or 100ksps/channel. As shown in Figure 12, the SINAD is
800ksps 14-bit ADC. It receives and converts signals from
76.6dB for a full-scale ±2.5V, 1.19kHz sine wave input
a 74HC4051 8-channel multiplexer. Three of the four
signal.
output bits from an additional circuit, a 74HC4520 dual 4-
0
bit binary counter, are used to select a multiplexer chan- fSAMPLE = 100ksps
nel. A logic high power-on or processor-generated reset is –20 fIN = 1.19kHz
VIN = ±2.5V
applied to the counter’s pin 7. –40
AMPLITUDE (dB)
–60
After the counter is cleared, the multiplexer’s channel –80

selection input is 000 and the input to channel 0 is applied –100
to the LTC1419’s S/H input. The channel-selection counter
–120
is clocked by the rising edge of the convert start (CONVST)
signal that initiates a conversion. As each CONVST pulse –140
increments the counter from 000 to 111, each multiplexer 0 10 20 30 40 50

channel is individually selected and its input signal is INPUT FREQUENCY (kHz)
applied to the LTC1419. After each of the eight channels Figure 12. FFT of the MUXed LTC1419’s
DI_MUX_02.EPS
has been selected, the counter rolls over to zero and the Conversion of a Full-Scale 1.19kHz Sine Wave
5V –5V
10µF 10µF
5V
74HC4051
+
+
0.1µF
13 16 0.1µF 0.1µF
AIN O 0 VCC
LTC1419
14
AIN 1 1
15 3 1 28
AIN 2 2 COM +
AIN AVDD
12 2 27
AIN 3 3 1µF –
AIN DVDD
1 6 3 26
AIN 4 4 INH VREF VSS
5 8 4 25
AIN 5 5 GND COMP BUSY BUSY
2 + 10µF 0.1µF 5 24
AIN 6 6 AGND CS
4 7 6 23 CONVERT
AIN 7 7 VSS D13 (MSB) CONVST
7 CONTROL
0.1µF 22
A B C D12 RD
8 21
D11 SHDN
9 20
74HC4520 3 4 5 6 –5V D10 D0
10 19
1Q0 1Q1 1Q2 1Q3 D9 D1
14 1 11 18
2Q3 1CLK D8 D2
13 2 12 17
2Q2 1CE D7 D3
12 7 13 16
2Q1 1CLEAR D6 D4
11 15 14 15
2Q0 2CLEAR DGND D5
10 16 DI_MUX_01.EPS
2CE VCC 5V
2CLK GND
DATA 0–13
9 8 0.1µF
CLEAR
COUNT
Figure 11. This Simple Stand-Alone Circuit Requires no Software to Sequentially Sample
and Convert Eight Analog Signal Channels at 14-bit Resolution and 100ksps/Channel.
AN87-13
Application Note 87
THE LTC1590 DUAL 12-BIT DAC The PGA’s gain is set using the following equation:
IS EXTREMELY VERSATILE
by LTC Applications Staff n
VOUT = –VIN 2
CMOS multiplying DACs make versatile building blocks D
that go beyond their basic function of converting digital
data into analog signals. This article details some of the where VOUT = output voltage
VIN = input voltage
other circuits that are possible when using the LTC1590 n = DAC resolution in bits
dual, serially interfaced 12-bit DAC. D = value of code applied to DAC
(min code = 001H)
The circuit shown in Figure 13 uses the LTC1590 to create The gain is adjustable from 4096/4095 to 4096/1. A code
a digitally controlled attenuator using DACA and a proof 0 is meaningless, since this results in infinite gain and
grammable gain amplifier (PGA) using DACB. The the amplifier operates open loop. With either configura-
attenuator’s gain is set using the following equation: tion, the attenuator’s and PGA’s gain are set with 12 bits
accuracy.
VOUT = –VIN D
2n A further modification to the basic attenuator and PGA is
shown in Figure 14. In this circuit, DACA’s attenuator
where VOUT = output voltage circuit is modified to give the output amplifier a gain set by
VIN = input voltage the ratio of resistors R3 and R4. The equation for this
n = DAC resolution in bits attenuator with output gain is
D = value of code applied to DAC
(min code = 000H)
The attenuator’s gain varies from 4095/4096 to 1/4096. A VOUT = –VIN 16D
2n
code of 0 can be used to completely attenuate the input
signal.
5V VIN A
0.1µF PROGRAMMABLE
±10V 15V
ATTENUATOR
16 1 2 0.01µF
LTC1590 33pF
VREF A RFB A
OUT1A 3 2 – 8
13 DIN
DATA IN
24-BIT SHIFT REGISTER AND LATCH
1
DACA 1/2 LT1358 VOUT A
14 CLK
SERIAL CLOCK OUT2A 4 3 +
CHIP SELECT/ 11 CS/LD VOUT = –VIN D
DAC LOAD 2n
4 DOUT
DATA OUT
15 CLR
CLEAR
n
OUT2B 5 5 VOUT = –VIN 2
+ D
7
DACB 1/2 LT1358 VOUT B
OUT1B 6 6
7 AGND – 4
0.01µF
VREF B RFB B
10 DGND
33pF
9 8
DI1590_01.EPS
PROGRAMMABLE
VIN B GAIN AMPLIFIER –15V
±10V
Figure 13. Driving DACA’s Reference Input (VREF) and Tying the Feedback Resistor (RFB) to the Op Amp’s Output Creates a
12-Bit- Accurate Attenuator. Reversing the VREF and RFB Connections Configures DACB as a Programmable-Gain Amplifier.
AN87-14
Application Note 87
VIN A
±10V
5V
0.1µF
1k 15k 15V
R4
15k
16 1 2 0.01µF
33pF
R3
1k
VREF A RFB A
OUT1A 3 2 – 8
13 DIN
DATA IN
1
DACA 1/2 LT1358 VOUT A
14 CLK
SERIAL CLOCK OUT2A 4 3 +
11 CS/LD VOUT = –VIN 16D
CHIP SELECT/ 2n
DAC LOAD
4 DOUT
DATA OUT LTC1590
15 CLR
CLEAR
n
OUT2B 5 5 VOUT = –VIN 2
+ 16D
7
DACB 1/2 LT1358 VOUT B
OUT1B 6 6
7 AGND – 4
0.01µF
VREF B RFB B
10 DGND
9 8 33pF
15k
DI1590_02.EPS
1k
R1 –15V
R2
1k 15k
VIN B
±10V
Figure 14. Modifying the Basic Attenuator and PGA Creates Gain for the
Attenuator (R3 and R4) and Attenuation at the PGA’s Input (R1 and R2).
With the values shown, the attenuator’s gain has a range The cutoff frequency range is a function of the DAC’s
of –1/256 to –16. This range is easily modified by changing resolution and the digital data that sets the effective
the ratio of R3 and R4. In the other half of the circuit, an resistance. The effective resistance is
attenuator has been added to the input of DACB, config-
ured as a PGA. The equation for this PGA with input n
attenuation is RREF = RI 2
D
n Using this effective resistance, the cutoff frequency is

VOUT = –VIN 2
16D
fC = D
This sets the gain range from effectively –1/16 to –256. 2n+1 • π • RI • CI
Again, this range can be modified by changing the ratio of
R1 and R2. The cutoff frequency range varies from 0.0000389/RC to
0.159/RC. As an example, to set the minimum cutoff
The LTC1590 can also be used as the control element that frequency to 10Hz, make RI = 8.25k and CI = 470pF. At an
sets a lowpass filter’s cutoff frequency. This is shown in input code of 1, the cutoff frequency is 10Hz. The cutoff
Figure 15. The DAC becomes an adjustable resistor that frequency increases linearly with increasing code,
sets the time constant of the integrator formed by U4 and becoming 40.95kHz at a code of 4095. Generally, as the
CI. With the integrator enclosed within a feedback loop, a code changes by ±1 bit, the cutoff frequency changes by
lowpass filter is created. an amount equal to the frequency at D = 1. In this example,
the cutoff frequency changes in 10Hz steps.
AN87-15
Application Note 87
15V
10k
10k
0.01µF
VIN A
10k 2 – 8
U2A 1
1/2 LT1358
3 + 15V 15V
0.01µF
5V 1 2 0.01µF
16 3 8
VREF A RFB A +
0.1µF OUT1A 3 2 – 8 U4A 1
VOUT A
1/2 LT1358
U3A
1 2
DACA 1/2 LT1358 –
13 DIN OUT2A 4 3 + RI
DATA IN CI
14 CLK
SERIAL CLOCK
11 fC = D
CHIP SELECT/ CS/LD U1 LTC1590
DAC LOAD 2n+1 • π • RI • CI
4 DOUT
DATA OUT
OUT2B 5 5
CLEAR
15 CLR + CI
DACB
U3B 7 RI 6 –
1/2 LT1358
OUT1B 6 6 U4B 7
7 AGND – 4
0.01µF 1/2 LT1358 VOUT B
10 DGND
VREF B RFB B 5 +
4 0.01µF
9 8
5
+
U2B 7 –15V –15V
10k 1/2 LT1358
VIN B 6
– 4 0.01µF
10k
10k
DI1590_03.EPS
–15V
Figure 15. This LTC1590-Controlled Dual Single-Pole Lowpass Filter Uses RI and the DAC’s Input Code to Create
an Effective Resistance that Sets the Integrator’s Time Constant and, Therefore, the Circuit’s Cutoff Frequency.
NEW 16-BIT SO-8 DAC HAS 1LSB MAX INL AND DNL
OVER INDUSTRIAL TEMPERATURE ❏ ±1LSB maximum INL and DNL over the industrial
by Jim Brubaker and William C. Rempfer temperature range
New generations of industrial systems are moving to 16 ❏ Ultralow, 1nV-s glitch impulse
bits and hence require high performance 16-bit data
converters. The new LTC1595/LTC1596 16-bit DACs pro- ❏ ±10V output capability
vide the easiest to use, most cost effective, highest perfor- ❏ Small SO-8 package (LTC1595)
mance solution for industrial and instrumentation applica-
tions. The LTC1595/LTC1596 are serial input, 16-bit, ❏ Pin-compatible upgrade for industry-standard 12-bit
multiplying current output DACs. Features of the new DACs (DAC8043/8143 and AD7543)
DACs include:
AN87-16
Application Note 87
0V–10V and ±10V Output Capability VREF
(–10V TO 10V)
5V
Precision 0V–10V Outputs with One Op Amp 8 1 2 33pF

VDD VREF RFB
7
CLOCK CLK
Figure 16 shows the circuit for a 0V–10V output range. 6
SRI
3 –
DATA LTC1595 OUT1
5 VOUT
The DAC uses an external reference and a single op amp LOAD LD LT1001 0V TO
in this configuration. This circuit can also perform 2- GND + –VREF
4
quadrant multiplication where the reference input is driven
by a ±10V input signal and VOUT swings from 0V to –VREF. 1595_04.EPS
The full-scale accuracy of the circuit is very precise

Figure 16. With a Single External Op Amp, the DAC
because it is determined by precision-trimmed internal Performs 2-Quadrant Multiplication with ±10V Input and
resistors. The power dissipation of the circuit is set by the 0V to –VREF Output. With a Fixed –10V Reference, it
op amp dissipation and the current drawn from the DAC Provides a Precision 0V–10V Unipolar Output.
reference input (7k nominal). The supply current of the
DAC itself is less than 10µA.
VOUT
An advantage of the LTC1595/LTC1596 is the ability to 5V/DIV
choose the output op amp to optimize the accuracy,
speed, power and cost of the application. Using an LT1001
provides excellent DC precision, low noise and low power GATED VOUT
500µV/DIV
dissipation (90mW total for Figure 16’s circuit). For higher
speed, an LT1007, LT1468 or LT1122 can be used. The
LT1122 will provide settling to 1LSB in 3µs for a full-scale 1µs/DIV
transition. Figure 17 shows the 3µs settling performance
obtained with the LT1122. The feedback capacitor in Figure 17. When Used with an LT1122 (in the Circuit of Figure
Figure 16 ensures stability. In higher speed applications, 16), the LTC1595/LTC1596 Can Settle in 3µs to a Full-Scale
Step. The Top Trace Shows the Output Swinging from 0V to 10V.
it can be used to optimize transient response. In slower The Bottom Trace Shows the Gated Settling Waveform Settling
applications, the capacitor can be increased to reduce to 1LSB (1/3 of a Division) in 3µs.
glitch energy and provide filtering.
R2 R3
VREF 20k 20k
(–10V TO 10V)
5V
0.1µF
8 1 2
33pF
VDD VREF RFB
7
CLK
µP
6
SRI LTC1595 OUT1
3 – R1
5
LD
10k –
1/2 LT1112
VOUT
GND + (–VREF TO VREF)
1/2 LT1112
4 +
1595_05.EPS
Figure 18. With a Dual Op Amp, the DAC Performs 4-Quadrant Multiplication.
With a Fixed 10V Reference, it Provides a ±10V Bipolar Output.
AN87-17
Application Note 87
Precision ±10V Outputs with a Dual Op Amp resistors. A good way to provide good matching and save
board space is to use a pack of matched 20k resistors (the
Figure 18 shows a bipolar, 4-quadrant multiplying appli- 10k unit is formed by placing two 20k resistors in parallel).
cation. The reference input can vary from –10V to 10V and
VOUT swings from –VREF to +VREF. If a fixed 10V reference The LT1112 dual op amp is an excellent choice for high
is used, a precision ±10V bipolar output will result. precision, low power applications that do not require high
speed. The LT1469 or LT1124 will provide faster settling.
Unlike the unipolar circuit of Figure 16, the bipolar gain Again, with op amp selection the user can optimize the
and offset will depend on the matching of the external speed, power, accuracy and cost of the application.
LTC1659, LTC1448: SMALLEST RAIL-TO-RAIL

12-BIT DACS HAVE LOWEST POWER 2.7V to 5.5V VREF ≤ VCC
by Hassan Malik
In this age of portable electronics, power and size are the DIN VCC REF
primary concerns of most designers. The LTC1659 and µP VOUT

CONTROL
VOLTAGE
CLK LTC1659
the LTC1448 are rail-to-rail, 12-bit, voltage output DACs (0V TO VREF)
that address both of these concerns. The LTC1659 is a CS/LD GND
single DAC in an MSOP-8 package that draws only 250µA

from a 3V or 5V supply, whereas the LTC1448 is a dual
DAC in an SO-8 package that draws 450µA from a 3V or 5V 1659_01
Figure 19. 12-Bit DAC for Digital Control Loop
supply.
Figure 19 shows a convenient way to use the LTC1659 in

LT1236
a digital control loop where 12-bit resolution is required.
The output of the LTC1659 will swing from 0V to VREF, VIN IN OUT
(7.2V to 40V)
because there is a gain of one from the REF pin to VOUT at
GND
full-scale. Because the output can only swing up to VCC, 0.1µF
VREF should be less than or equal to VCC to prevent the loss
of codes and degradation of PSRR near full-scale.
DIN VCC REF
To obtain full dynamic range, the REF pin can be connected CONTROL
µP CLK LTC1659 VOUT VOLTAGE
to the supply pin, which can be driven from a reference to (OV TO 5V)
guarantee absolute accuracy (see Figure 20). The LT1236 CS/LD GND
is a precision 5V reference with an input range of 7.2V to
1659_02
40V. In this configuration, the LTC1659 has a wide output
swing of 0V to 5V. The LTC1448 can be used in a similar
Figure 20. 12-Bit DAC with Wide Output Swing
configuration where dual DACs are needed.
AN87-18
Application Note 87
AN SMBus-CONTROLLED 10-BIT, CURRENT OUTPUT, Digitally Controlled LCD Bias Generator
50µA FULL-SCALE DAC
by Ricky Chow Figure 21 is a schematic of a digitally controlled LCD bias
generator using a standard SMBus 2-wire interface. The
The LTC1427-50 is a 10-bit, current-output DAC with an LT1317 is configured as a boost converter, with the output
SMBus interface. This device provides precision, full- voltage (VOUT) determined by the values of the feedback
scale current of 50µA ±1.5% at room temperature (±2.5% resistors, R1 and R2. The LTC1427-50’s DAC current
over temperature), wide output voltage DC compliance output is connected to the feedback node of the LT1317.
(from –15V to (VCC – 1.3V)) and guaranteed monotonicity The LTC1427-50’s DAC current output increases or
over a wide supply-voltage range. It is an ideal part for decreases according to the data sent via the SMBus. As the
applications in contrast/brightness control or voltage DAC output current varies from 0µA to 50µA, the output
adjustment in feedback loops. voltage is controlled over the range of 12.7V to 24V. A
1LSB change in the DAC output current corresponds to an
11mV change in the output voltage.
L1 D1
VOUT*
VCC = 3.3V
6 5
R1
VIN SW
2–4 226k
CELLS LT1317 1%
3 2 LTC1427-50 µP
SHDN SHDN FB
1 8 (e.g., 8051)
R2 SHDN VCC
12.1k 2 7
1µF GND VC AD1 IOUT
1% 3 6
4 1 AD0 SCL P1.2
4700pF C1 4 5
1µF GND SDA P1.1
100k
P1.0
*VOUT = 12.7V–24V IN 11mV STEPS

15mA FROM 2 CELLS
35mA FROM 3 CELLS
L1 = 10µH (SUMIDA CD43

MURATA-ERIE LQH3C
OR COILCRAFT DO1608)
D1 = ON SEMICONDUCTOR MBR0530
Figure 21. Digitally Controlled LCD Bias Generator
AN87-19
Application Note 87
Interface Circuits
Tf ~ 10µs
T1/2 = 120µs
SIMPLE RESISTIVE SURGE PROTECTION FOR
VP
INTERFACE CIRCUITS
VOLTAGE
by LTC Applications Staff
VP/2
Surges and Circuits
Many interface circuits must survive surge voltages such Tf

as those created by lightning strikes. These high voltages T1/2
cause the devices within the IC to break down and conduct TIME
large currents, causing irreversible damage to the IC. TF CONTROLLED BY R2 × COUT

T1/2 CONTROLLED BY C1 × R1
Engineers must design circuits that tolerate the surges VP SET BY HV SUPPLY
expected in their environments. They can quantify the

surge tolerance of circuitry by using a surge standard. Figure 23. LTC Surge-Test Waveform
Standards differ mainly in their voltage levels and wave
forms. At LTC, we test surge resistance using the circuit Designing for Surge Tolerance
of Figure 22. We describe the voltage wave form (Figure
23) by its peak value VP, the “front time” TF (roughly, the Many designers enhance the surge tolerance of a circuit
rise time), and the “time to half-value” T1/2 (roughly, the by placing a transient voltage suppressor (TVS) in parallel
time from the beginning of the pulse to when the pulse with the vulnerable IC pins, as shown in Figure 24. The
decays to half of VP). Surges are similar to ESD, but TVS contains Zener diodes, which break down at a certain
challenge circuits in a different way. A surge may rise to voltage and shunt the surge current to ground. Thus, the
1kV in 10ms, whereas an ESD pulse might rise to 15kV in TVS clamps the voltage at a level safe for the IC. The TVS,
only a few ns. However, the surge lasts for more than like any protection circuitry, increases the manufacturing
100ms, whereas the ESD pulse decays in about 50ns. cost and complexity of the circuit. Alternately, designers
Thus, the surge challenges the power dissipation ability of can use a series resistor to protect the vulnerable pins, as
the protection circuitry, whereas the ESD challenges the shown in Figure 25. The resistor reduces the current
turn-on time and peak current handling. The Linear Tech-
nology LT1137A has on-chip circuitry to withstand ESD 1 14
VCC – VCC+
pulses up to 15kV (IEC 801-2). This circuitry also in- 0.1µF 0.1µF
1488
creases the surge tolerance of the LT1137A relative to a 2 13
standard 1488/1489.
3 12
RB R2
10k 75Ω, 2W
TVS
4 11
TVS
VP + C1 R1 COUT
5 10
7µF 50Ω 0.05µF DUT
HV SUPPLY
3kV 3W 4kV
6 9
TVS
TF CONTROLLED BY R2 × COUT
7 8
T1/2 CONTROLLED BY C1 × R1
VP SET BY HV SUPPLY
TVS
Figure 22. LTC Surge-Test Circuit: TF Controlled by R2 • COUT; T1/2

Controlled by C1 • R1; VP Set by HV Supply Figure 24. 1488 Line Driver with TVS Surge Protection
AN87-20
Application Note 87
1 28
V+ V–
0.1µF 2 27 0.1µF
5V VCC
2V/DIV
2× 3 26
0.1µF LT1137A
2 × 0.1µF
4 25
RS
5 24
RS = 0Ω 5µs/DIV
RS
6 23 130kBd
(a)
RS
7 22
RS TO LOGIC
8 21
TO
LINE RS
9 20
2V/DIV
RS
10 19
RS
11 18
RS
12 17
RS = 600Ω 5µs/DIV
13 16 130kBd
5V ON/OFF (b)
0.1µF 14 15
Figure 27. Output Waveforms with Series Resistor
1 28
V+ V–
0.1µF
Figure 25. LT1137A with Resistive Surge Protection 0.1µF 2 27
5V VCC
flowing into the IC to a safe level. Resistive protection 3 26

2 × 0.1µF LT1137A
simplifies design and inventory and may offer lower cost. 2 × 0.1µF
4 25
The resistance must be large enough to protect the IC, but
SCOPE
not so large that it degrades the frequency performance of RS
5 24 130k baud
the circuit. Larger surge amplitudes require increased RS
6 23
resistance to protect the IC. More robust ICs need less +
2.5nF 3kΩ RS
1200 7 22
LT1137A SAFE CURVE
1488 SAFE CURVE RS
1000 8 21
RS
SAFE SURGE VP (V)
800 9 20
RS
600 10 19
RS
400 11 18
RS
200 12 17
0 13 16
5V ON/OFF
0 100 200 300 400 500 600
R SERIES (Ω)
14 15
Figure 26. Safe Curves for 1488 (SN75188N) and LT1137A. Safe
Curves Represent the Highest VP for Which No IC Damage
Occurred After 10 Surges Figure 28. Testing Line Driver Output Waveform
AN87-21
Application Note 87
resistance for protection against a given surge amplitude. surface mount resistors are not suitable for protecting the
Linear’s LT1137A is protected by a much smaller resistor LT1137A. If you use surface mount components, you may
than a 1488, as shown in Figure 26. These curves are need ratings of 1W or more. With the LT1137A, you can
empirical “rules of thumb.” You should test actual circuits. use carbon film 1/4W through-hole resistors against surges
up to about 900V, and 1/2W carbon film resistors against
The series resistor may have an adverse effect on the surges up to about 1200V. Unfortunately, using series or
frequency performance of the circuit. When protecting a parallel combinations of resistors does not increase the
receiver, the resistor has little effect. Figures 27a and 27b surge handling as one would expect.
show the effect of a 600Ω resistor on the driver-output
wave form. These waveforms were obtained with the test Resistive Surge Protection
circuit of Figure 28. A 600Ω resistor is adequate for 1kV
surges, but has minimal effect on the driver wave form up The LT1137A has proprietary circuitry that makes it more
to 130kbaud, even with a worst-case load of 3kΩ||2.5nF. robust against ESD and surges than the standard 1488/
1489. The greater surge tolerance of the LT1137A makes
You must choose the series resistor carefully to withstand it practical to use resistive surge protection, reducing
the surge. Unfortunately, neither voltage ratings nor power inventory and component cost relative to TVS surge
ratings provide an adequate basis for choosing surge- protection. The major considerations are the surge toler-
tolerant resistors. Usually, through-hole resistors will ance required, the resulting resistor value needed, resistor
withstand much larger surges than surface mount resis- robustness and frequency performance.
tors of the same value and power rating. Typical 1/8 Watt
THE LTC1343 AND LTC1344 FORM A SOFTWARE-

SELECTABLE MULTIPLE-PROTOCOL INTERFACE PORT supports an echoed clock and loop-back configuration
USING A DB-25 CONNECTOR that helps eliminate glue logic between the serial controller
by Robert Reay and the line transceivers.
Introduction A typical application is shown in Figure 29. Two LTC1343s

and one LTC1344 form the interface port using a DB-25
With the explosive growth in data networking equipment connector, shown here in DTE mode.
has come the need to support many different serial proto-
cols using only one connector. The problem facing inter- Each LTC1343 contains four drivers and four receivers
face designers is to make the circuitry for each serial and the LTC1344 contains six switchable resistive termi-
protocol share the same connector pins without introduc- nators. The first LTC1343 is connected to the clock and
ing conflicts. The main source of frustration is that each data signal lines along with the diagnostic LL (local loop-
serial protocol requires a different line termination that is back) and TM (test mode) signals. The second LTC1343 is
not easily or cheaply switched. connected to the control-signal lines along with the diag-
nostic RL (remote loop-back) signal. The single-ended
With the introduction of the LTC1343 and LTC1344, a driver and receiver could be separated to support the RI
complete software-selectable serial interface port using (ring-indicate) signal. The switchable line terminators in
an inexpensive DB-25 connector becomes possible. The the LTC1344 are connected only to the high speed clock
chips form a serial interface port that supports the V.28 and data signals. When the interface protocol is changed
(RS232), V.35, V.36, RS449, EIA-530, EIA-530A or X.21 via the digital mode selection pins (not shown), the drivers
protocols in either DTE or DCE mode and is both NET1 and and receivers are automatically reconfigured and the
NET2 compliant. The port runs from a single 5V supply and appropriate line terminators are connected.
AN87-22
Application Note 87
CTS DSR DCD DTR RTS RL TM RXD RXC TXC SCTE TXD LL
LTC1343 LTC1343
D4 D3 D2 D1 D4 D3 D2 D1
R4 R3 R2 R1 R4 R3 R2 R1
LTC1344
13 5 22 6 10 8 23 20 19 4 21 1 7 25 16 3 9 17 12 15 11 24 14 2 18
DSR B
DSR A (107)
CTS B
CTS A (106)
DTR B
DTR A (108)
RTS B
RTS A (105)
RL A (140)
SHIELD (101)
SGND (102)
TM A (142)
RXD B
RXD A (104)
RXC B
RXC A (115)
DCD B
DCD A (109)
SCTE B
SCTE A (113)
TXD B
TXD A (103)
LL A (141)
TXC B
TXC A (114)
DB-25 CONNECTOR
Figure 29. LTC1343/LTC1344 Typical Application
BALANCED
INTERCONNECTING
GENERATOR CABLE LOAD
Review of Interface Standards
CABLE
TERMINATION RECEIVER
The serial interface standards RS232, EIA-530, EIA-530A, A A'
RS449, V.35, V.36 and X.21 specify the function of each
signal line, the electrical characteristics of each signal, the
connector type, the transmission rate and the data ex-
C B'
change protocols. The RS422 (V.11) and RS423 (V.10)
standards merely define electrical characteristics. The C'
RS232 (V.28) and V.35 standards also specify their own Figure 30. Typical V.10 Interface
electrical characteristics. In general, the US standards A'
start with RS or EIA, and the equivalent European stan- A LTC1343
LTC1344 R5
dards start with V or X. The characteristics of each R1 R8 20k
51.5Ω 6k
interface are summarized in Table 2. R6 RECEIVER
10k
S1 S3
R3
Table 2 shows only the most commonly used signal lines. S2 124Ω
Note that each signal line must conform to only one of four R7
R2 R4
electrical standards, V.10, V.11, V.28 or V.35. 51.5Ω
B 20k
10k
B'
S4
V.10 (RS423) Interface
C' GND
A typical V.10 unbalanced interface is shown in Figure 30.

A V.10 single-ended generator (output A with ground C) Figure 31. V.10 Receiver Configuration
AN87-23
Application Note 87
Table 2. Interface Summary
Clock and Data Signals Control Signals Test Signals
TXD SCTE TXC RXC RXD RT S DTR DSR DCD CTS RI LL RL TM
CCITT# (103) (113) (114) (115) (104) (105) (108) (107) (109) (106) (125) (141) (140) (142)
RS232 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
EIA-530 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 ———
V.10 V.10 V.10
EIA-530A V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.11 V.11 V.10 V.10 V.10 V.10
RS449 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.10 V.10
V.35 V.35 V.35 V.35 V.35 V.35 V.28 ———
V.28 V.28 V.28 ——— ——— ——— ———
V.36 V.11 V.11 V.11 V.11 V.11 V.11 ———

V.11 V.11 V.11 ———
V.10 V.10 V.10
X.21 V.11 V.11 V.11 V.11 V.11 V.11 ——— ———
V.11 ——— ——— ——— ——— ———
is connected to a differential receiver with input A' con- receiver end with a minimum value of 100Ω. The termina-
nected to A and input B' connected to the signal-return tion resistor is optional in the V.11 specification, but for
ground C. The receiver’s ground C' is separate from the the high speed clock and data lines, the termination is
signal return. Usually, no cable termination between A' required to prevent reflections from corrupting the data. In
and B' is required for V.10 interfaces. The V.10 receiver V.11 mode, all switches are off except S1 inside the
configuration for the LTC1343 and LTC1344 is shown in LTC1344, which connects a 103Ω differential termination
Figure 31. impedance to the cable, as shown in Figure 33.
In V.10 mode, switches S1 and S2 inside the LTC1344 and

V.28 (RS232) Interface
S3 inside the LTC1343 are turned off. Switch S4 inside the
A typical V.28 unbalanced interface is shown in Figure 34.
LTC1343 shorts the noninverting receiver input to ground
A V.28 single-ended generator (output A with ground C) is
so the B input at the connector can be left floating. The
connected to a single-ended receiver with input A' con-
cable termination is then the 30k input impedance to the
nected to A and ground C' connected via the signal return
ground of the LTC1343 V.10 receiver.
ground to C. In V.28 mode, all switches are off except S3
V.11 (RS422) Interface inside the LTC1343, which connects a 6k impedance (R8)
to ground in parallel with 20k (R5) plus 10k (R6), for an
A typical V.11 balanced interface is shown in Figure 32. A combined impedance of 5k, as shown in Figure 35. The
V.11 differential generator with outputs A and B and noninverting input is disconnected inside the LTC1343
ground C is connected to a differential receiver with receiver and connected to a TTL level reference voltage for
ground C', input A' connected to A and input B' connected a 1.4V receiver trip point.
A'
to B. The V.11 interface has a differential termination at the A LTC1343
LTC1344 R5
BALANCED R1 R8
INTERCONNECTING 51.5Ω 20k
6k
GENERATOR CABLE LOAD R6 RECEIVER
10k
CABLE S1 S3
TERMINATION RECEIVER R3
S2 124Ω
A A'
R2 R7
R4 10k
100Ω 51.5Ω 20k
B
MIN
B B' B'
S4
C C'
C' GND
Figure 32. Typical V.11 Interface Figure 33. V.11 Receiver Configuration
AN87-24
Application Note 87
BALANCED LOAD
INTERCONNECTING GENERATOR BALANCED CABLE
GENERATOR CABLE LOAD INTERCONNECTING TERMINATION RECEIVER
CABLE CABLE
TERMINATION RECEIVER A A'
A A' 50Ω 50Ω

125Ω 125Ω
50Ω 50Ω
B B'
C C'
C C'
Figure 34. Typical V.28 Interface Figure 36. Typical V.35 Interface
A' A'
A LTC1343 A LTC1343
LTC1344 R5 LTC1344 R5
R1 R8 R1 R8
20k 51.5Ω 20k
51.5Ω 6k 6k
R6 R6 RECEIVER
RECEIVER 10k
10k
S1 S3 S1 S3
R3 R3
S2 124Ω S2 124Ω
R2 R7 R2 R7
R4 R4 10k
51.5Ω 10k 51.5Ω 20k
B 20k B
B' B'
S4 S4
C' GND C' GND
Figure 35. V.28 Receiver Configuration Figure 37. V.35 Receiver Configuration
V.35 Interface side of the center resistor is brought out to a pin so it can
be bypassed with an external capacitor to reduce common
A typical V.35 balanced interface is shown in Figure 36. A mode noise, as shown in Figure 38.
V.35 differential generator with outputs A and B and
ground C is connected to a differential receiver with Any mismatch in the driver rise and fall times or skew in
ground C', input A' connected to A and input B' connected driver propagation delays will force current through the
to B. The V.35 interface requires T or delta network center termination resistor to ground, causing a high
termination at the receiver end and the generator end. The frequency common mode spike on the A and B terminals.
receiver differential impedance measured at the connector This spike can cause EMI problems that are reduced by
must be 100 ±10Ω, and the impedance between shorted capacitor C1, which shunts much of the common mode
terminals (A' and B') and ground (C') is 150 ±15Ω. energy to ground rather than down the cable.
In V.35 mode, both switches S1 and S2 inside the LTC1344 A
are on, connecting the T-network impedance, as shown in LTC1344 51.5Ω

Figure 37. Both switches in the LTC1343 are off. The 30k
V.35
input impedance of the receiver is placed in parallel with DRIVER
S1
S2 ON
the T-network termination, but does not affect the overall 124Ω ON
input impedance significantly.
51.5Ω
B
The generator differential impedance must be 50Ω to C1
150Ω, and the impedance between shorted terminals (A 100pF
C
and B) and ground (C) is 150Ω ±15Ω. For the generator
termination, switches S1 and S2 are both on and the top Figure 38. V.35 Driver Using the LTC1344
AN87-25
Application Note 87
Table 3. LTC1343/LTC1344 Mode Selection
CTRL/
LTC1343 Mode Name M2 M1 M0 CLK D1 D2 D3 D4 R1 R2 R3 R4
V.10/RS423 0 0 0 X V.10 V.10 V. 1 0 V.10 V.10 V.10 V.10 V.10
RS530A clock & data 0 0 1 0 V.10 V.11 V. 1 1 V.11 V.11 V.11 V.11 V.10
RS530A control 0 0 1 1 V.10 V.11 V.10 V.11 V.11 V.10 V.11 V.10
Reserved 0 1 0 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
X.21 0 1 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.35 clock & data 1 0 0 0 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28
V.35 control 1 0 0 1 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
RS530/RS449/V.36 1 0 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.28/RS232 1 1 0 X V.28 V.28 V. 2 8 V.28 V.28 V.28 V.28 V.28
No Cable 1 1 1 X Z Z Z Z Z Z Z Z
21
LATCH
LTC1344
DCE/
DTE M2 M1 M0 (DATA)
22 23 24 1
CONNECTOR
(DATA)
R1, 10k
LTC1343 VCC
17
M0
R2, 10k
20 18 VCC
CTRL/CLK M1
R3, 10k
22 VCC
19
LATCH M2 NC
R4, 10k
VCC
21
DCE/DTE NC
CABLE
LTC1343
21
DCE/DTE
19
M2
20 18
VCC CTRL/CLK M1
22 17
LATCH M0
(DATA)
Figure 39. Mode Selection by Cable
AN87-26
Application Note 87
PORT #1 The interface protocol may be selected by simply plugging
M0 the appropriate interface cable into the connector. The
M1 mode pins are routed to the connector and are left uncon-
CONNECTOR #1
M2
nected (1) or wired to ground (0) in the cable, as shown in
DCE/DTE
Figure 39.
The pull-up resistors R1–R4 ensure a binary 1 when a pin

LATCH
is left unconnected and also ensure that the two LTC1343s
PORT #2 and the LTC1344 enter the no-cable mode when the cable
M0
is removed. In the no-cable mode, the LTC1343 power
M1
supply current drops to less than 200µA and all LTC1343
CONNECTOR #2
M2
driver outputs and LTC1344 resistive terminators are
DCE/DTE
forced into a high impedance state. Note that the data latch
pin, LATCH, is shorted to ground for all chips.
LATCH
CONTROLLER
The interface protocol may also be selected by the serial
PORT #3 controller or host microprocessor, as shown in Figure 40.
M0 M0
M1 M1
CONNECTOR #3
The mode selection pins M0, M1, M2 and DCE/DTE can be

M2 M2
DCE/DTE DCE/DTE
shared among multiple interface ports, while each port
LATCH 1
has a unique data-latch signal that acts as a write enable.
LATCH 2
When the LATCH pin is low, the buffers on the MO, M1,
LATCH 3 LATCH M2, CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high, the buffers latch the
data, and changes on the input pins will no longer affect
Figure 40. Mode Selection by Controller the chip.
The mode selection may also be accomplished by using

LTC1343/LTC1344 Mode Selection jumpers to connect the mode pins to ground or VCC.
The interface protocol is selected using the mode select Loop-Back

pins M0, M1, M2 and CTRL/CLK, as summarized in Table
3. The CTRL/CLK pin should be pulled high if the LTC1343 The LTC1343 contains logic for placing the interface into
is being used to generate control signals and pulled low if a loop-back configuration for testing. Both DTE and DCE
used to generate clock and data signals. loop-back configurations are supported. Figure 41 shows
a complete DTE interface in the loop-back configuration
For example, if the port is configured as a V.35 interface, and Figure 42 the DCE loop-back configuration. The loop-
the mode selection pins should be M2 = 1, M1 = 0, M0 = back configuration is selected by pulling the LB pin low.
0. For the control signals, CTRL/CLK = 1 and the drivers
and receivers will operate in RS232 (V.28) electrical mode. Enabling the Single-Ended Driver and Receiver
For the clock and data signals, CTRL/CLK = 0 and the
drivers and receivers will operate in V.35 electrical mode, When the LTC1343 is being used to generate the control
except for the single-ended driver and receiver, which will signals (CTRL/CLK = high) and the EC pin is pulled low, the
operate in the RS232 (V.28) electrical mode. The DCE/DTE DCE/DTE pin becomes an enable for driver 1 and receiver
pin will configure the port for DCE mode when high, and 4 so their inputs and outputs can be tied together, as
DTE when low. shown in Figure 43.
AN87-27
Application Note 87
SERIAL LTC1343 LTC1344 LTC1344 LTC1343 SERIAL
CONTROLLER LL LL CONTROLLER
LL D1 R4 LL
TXD D2 TXD TXD 103Ω R3 TXD
SCTE D3 SCTE SCTE 103Ω R2 SCTE
D4 R1
TXC R1 103Ω TXC TXC D4 TXC
RXC R2 103Ω RXC RXC D3 RXC
RXD R3 103Ω RXD RXD D2 RXD
TM TM
TM R4 D1 TM
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE
DCE/DTE
DCE/DTE
LATCH
LATCH
LATCH
LATCH
M0
M1
M2
M0
M1
M2
M0
M1
M2
M0
M1
M2
LB
EC
LB
EC
1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0
LTC1343 LTC1343
RL RL
RL D1 R4 RL
RTS D2 RTS RTS R3 RTS
DTR D3 DTR DTR R2 DTR
D4 R1
DCD R1 DCD DCD D4 DCD
DSR R2 DSR DSR D3 DSR
CTS R3 CTS CTS D2 CTS
RI RI
RI R4 D1 RI
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE
LATCH
LATCH
M0
M1
M2
M0
M1
M2
LB
EC
LB
EC
1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0
Figure 41. Normal DTE Loop-Back Figure 42. Normal DCE Loop-Back
AN87-28
Application Note 87
LTC1343 4 of the control chip share the RL signal on connector pin
5
D1
39 21. With EC low and CTRL/CLK high, the DCE/DTE pin
21
becomes an enable signal.
DCE/DTE
16 26
R4 Single-ended receiver 4 can be connected to pin 22 to
VCC
20
CTRL/CLK
implement the RI (ring indicate) signal in RS232 mode
24 (see Figure 45). In all other modes, pin 22 carries the
EC
DSR(B) signal.
Figure 43. Single-Ended Driver and Receiver Enable A cable selectable multiprotocol interface is shown in
Figure 46. Control signals LL, RL and TM are not imple-
mented. The VCC supply and select lines M0 and M1 are
brought out to the connector. The mode is selected in the
The EC pin has no affect on the configuration when CTRL/ cable by wiring M0 (connector pin 18) and M1 (connector
CLK is high except to allow the DCE/DTE pin to become an pin 21) and DCE/DTE (connector pin 25) to ground (con-
enable. When DCE/DTE is low, the driver 1 output is nector pin 7) or letting them float. If M0, M1 or DCE/DTE
enabled. The receiver 4 output goes into three-state, and are floating, pull-up resistors R3, R4 and R5 will pull the
the input presents a 30k load to ground. signals to VCC. The select bit M1 is hard wired to VCC. When
the cable is pulled out, the interface goes into the no-cable
When DCE/DTE is high, the driver 1 output goes into three- mode.
state, and the receiver 4 output is enabled. The receiver 4
input presents a 30k load to ground in all modes except A cable-selectable multiprotocol interface found in many
when configured for RS232 operation, when the input popular data routers is shown in Figure 47. The entire
impedance is 5k to ground. interface, including the LL signal, can be implemented
using the tiny µDB-26 connector.
Multiprotocol Interface with DB-25
or µDB-26 Connectors Conclusion
A multiprotocol serial interface with a standard DB-25 The LTC1343 and LTC1344 allow the designer of a multi-
connector EIA-530 pin configuration is shown in Figure protocol serial interface to spend all of his time on the
44. (Figures 44–47 follow on pp. 30–33). The signal lines software rather than the hardware. Simply drop the chips
must be reversed in the cable when switching between down on the board, hook them up to the connector and a
DTE and DCE using the same connector. For example, in serial controller, apply the 5V supply voltage and you’re off
DTE mode, the RXD signal is routed to receiver 3, but in and running. In addition, the chip set’s small size and
DCE mode, the TXD signal is routed to receiver 3. The unique termination topology allow many ports to be
interface mode is selected by logic outputs from the placed on a board using inexpensive connectors and
controller or from jumpers to either VCC or GND on the cables.
mode-select pins. The single-ended driver 1 and receiver
AN87-29
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344
VCC
5V
14
VCC
1 44
C3 C2
2 43 1µF
1µF C1 42 2
1µF 4 CHARGE VEE
C4
3 PUMP DB-25 CONNECTOR
+ 3.3µF DCE/
41
C5 8 DTE M2 M1 M0
1µF LTC1343 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 DTE DCE
5 39 18
DTE_LL/DCE_TM D1 LL A TM A
38 2
6 TXD A RXD A
DTE_TXD/DCE_RXD D2 37 14
TXD B RXD B
36 24
7 SCTE A RXC A
DTE_SCTE/DEC_RXC D3 35 11
SCTE B RXC B
34
9
D4 33
10
12
32 15 TXC A TXC A
13
DTE_TXC/DCE_TXC R1 31 12
TXC B TXC B
30 17
14 RXC A SCTE A
DTE_RXC/DCE_SCTE R2 29 9
RXC B SCTE B
28 3
15 RXD A TXD A
DTE_RXD/DCE_TXD R3 27 16
RXD B TXD B
16 26 25
DTE_TM/DCE_LL R4 TM A LL A
20 21
CTRL DCE
22 19
LATCH M2
11 18
INVERT M1
25 17
423 SET M0
R1
100k
40
GND
23 24
LB EC VCC 7
SGND
1 44 1
C10 SHIELD
C11 2 43 1µF
1µF
C9 42
1µF 4 CHARGE
C13
3 PUMP
VCC 3.3µF
41 +
C12 8
1µF LTC1343
5 39 21
DTE_RL/DCE_RL D1 RL A RL A
38 4 RTS A CTS A
6
DTE_RTS/DCE_CTS D2 37 19 RTS B CTS B
36 20
7 DTR A DSR A
DTE_DTR/DCE_DSR D3 35 23
DTR B DSR B
34
9
D4 33
10
12
32 8
13 DCD A DCD A
DTE_DCD/DCE_DCD R1 31 10
DCD B DCD B
30 6
14 DSR A DTR A
DTE_DSR/DCE_DTR R2 29 22
DSR B DTR B
28 5
15 CTS A RTS A
DTE_CTS/DCE_RTS R3 27 13
CTS B RTS B
16 26
R4
20 21
VCC CTRL DCE
22 19
LATCH LATCH M2
11 18
INVERT M1
25 17
423 SET M0
R2
100k
40
GND
23 24
LB LB EC
DCE/DTE
M2
M1
M0
Figure 44. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
AN87-30
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344
VCC
5V
14
VCC
1 44
C3 C2
2 43 1µF
1µF C1 42 2
1µF 4 CHARGE VEE
C4
3 PUMP DB-25 FEMALE
3.3µF DCE/
41 +
CONNECTOR
C5 8 DTE M2 M1 M0
1µF LTC1343 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
5 39 25
TM D1 TM A (142)
38 3
6 RXD A (104)
RXD D2 37 16
RXD B
36 17
7 RXC A (115)
RXC D3 35 9
RXC B
34 15
9 TXC A (114)
TXC D4 33 12
10 TXC B
VCC 12 VCC
32
13
R1 31
30 24
14 SCTE A (113)
SCTE R2 29 11
SCTE B
28 2
15 TXD A (103)
TXD R3 27 14
TXD B
16 26 18
LL R4 LL A (141)
20 21
CTRL DCE VCC
22 19
LATCH M2
11 18
INVERT M1
25 17
423 SET M0
R1
100k
40
GND
23 24
LB EC VCC 7
SGND (102)
1 44 1
C10 SHIELD (101)
C11 2 43 1µF
1µF C9
42
1µF 4 CHARGE
C13
3 PUMP
VCC 3.3µF
41 +
C12 8
1µF LTC1343
5 39
RI D1
38 5 CTS A (106)
6
CTS D2 37 13 CTS B
36 6 DSR A (107)
7
DSR D3 35 22
DSR B/RI A (125)
34 8
9 DCD A (109)
DCD D4 33 10
10 DCD B
VCC
12
32
13
R1 31
30 20
14 DTR A (108)
DTR R2 29 23
DTR B
28 4
15 RTS A (105)
CTX R3 27 19
RTS B
16 26 21
RL R4 RL A (140)
20 21
VCC CTRL DCE RIEN = RS232
22 19
LATCH LATCH M2
11 18
INVERT M1
25 17
423 SET M0
R2
100k
40
GND
23 24
LB LB EC
M2
M1
M0
Figure 45. Controller-Selectable Multiprotocol DCE Port with Ring-Indicate and DB-25 Connector
AN87-31
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344
VCC
5V
14
VCC
1 44
C3 C2
2 43 1µF
1µF C1 42 2
1µF 4 CHARGE VEE
C4
3 PUMP DB-25 CONNECTOR
3.3µF DCE/
41 +
C5 8 DTE M2 M1 M0
1µF LTC1343 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
5 39
D1 VCC DTE DCE
38 2
6 TXD A RXD A
TXD B RXD B
36 24
7 SCTE A RXC A
SCTE B RXC B
34
9
D4 33
10
12
32 15 TXC A TXC A
13
TXC B TXC B
30 17
14 RXC A SCTE A
RXC B SCTE B
28 3
15 RXD A TXD A
RXD B TXD B
16 26
R4
20 21
CTRL DCE 7
22 19 SGND
LATCH M2 VCC
11 18
INVERT M1
25 17 1
423 SET M0 SHIELD
R1
100k
40
GND
23 24
LB EC VCC
1 44 VCC VCC VCC

C10
C11 2 43 1µF R3 R4 R5
1µF
C9 42 10k 10k 10k
1µF 4 CHARGE 25
C13 DCE/DTE
3 PUMP 21
VCC + 3.3µF M1
41
C12 8 18
1µF M0
LTC1343
5 39
D1
38 4 RTS A CTS A
6
36 20
7 DTR A DSR A
DTR B DSR B
34
9
D4 33
10
12
32 8
13 DCD A DCD A
DCD B DCD B
30 6
14 DSR A DTR A
DSR B DTR B
28 5
15 CTS A RTS A
DTE_CTS/ DCE_RTS R3 27 13
CTS B RTS B
16 26
R4
20 21
VCC CTRL DCE
22 19
LATCH M2 VCC
11 18
INVERT M1
25 17
423 SET M0
R2
100k CABLE WIRING FOR MODE SELECTION CABLE WIRING FOR DTE/DCE
40
GND MODE PIN 18 PIN 21 SELECTION
23 24
LB LB EC V.35 PIN 7 PIN 7 MODE PIN 25
EIA-530, RS449, NC PIN 7 DTE PIN 7
V.36, X.21 DCE NC
RS232 PIN 7 NC
Figure 46. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
AN87-32
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344
VCC
5V
14
VCC
1 44
C3 C2
2 43 1µF
1µF C1 42 2
1µF 4 CHARGE VEE
C4
3 PUMP µDB-26 CONNECTOR
3.3µF DCE/
41 +
C5 8 DTE M2 M1 M0
1µF LTC1343 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
5 39
D1 VCC DTE DCE
38 2
6 TXD A RXD A
TXD B RXD B
36 24
7 SCTE A RXC A
SCTE B RXC B
34
9
D4 33
10
12
32 15 TXC A TXC A
13
TXC B TXC B
30 17
14 RXC A SCTE A
RXC B SCTE B
28 3
15 RXD A TXD A
RXD B TXD B
16 26
R4
20 21
CTRL DCE 7
22 19 SGND
LATCH M2 VCC
11 18
INVERT M1
25 17 1
423 SET M0 SHIELD
R1
100k
40
GND
23 24
LB EC VCC
1 44 VCC VCC VCC

C10
C11 2 43 1µF R3 R4 R5
1µF
C9 42 10k 10k 10k
1µF 4 CHARGE 25
C13 DCE/DTE
3 PUMP 21
VCC + 3.3µF M1
41
C12 8 18
M0
1µF LTC1343
5 39
DTE_LL/DCE_LL D1
38 4 RTS A CTS A
6
36 20
7 DTR A DSR A
DTR B DSR B
34
9
D4 33
10
12
32 8
13 DCD A DCD A
DCD B DCD B
30 6
14 DSR A DTR A
DSR B DTR B
28 5
15 CTS A RTS A
CTS B RTS B
16 26 26
R4 LL B LL B
20 21
VCC CTRL DCE
22 19
LATCH M2 VCC
11 18
INVERT M1
25 17
423 SET M0
R2
100k CABLE WIRING FOR MODE SELECTION CABLE WIRING FOR DTE/DCE
40
GND MODE PIN 18 PIN 21 SELECTION
23 24
LB LB EC V.35 PIN 7 PIN 7 MODE PIN 25
EIA-530, RS449, NC PIN 7 DTE PIN 7
V.36, X.21 DCE NC
RS232 PIN 7 NC
Figure 47. Cable-Selectable Multiprotocol DTE/DCE Port with µDB-26 Connector
AN87-33
Application Note 87
VCC
THE LT1328: A LOW COST IRDA RECEIVER SOLUTION
FOR DATA RATES UP TO 4MBPS D2
HSDL-4220
by Alexander Strong RD2
6.8Ω
1/2W
IrDA SIR RD1
100Ω Q3 Q4
TRANSMIT
INPUT 2N7002 2N7002
The LT1328 circuit in Figure 48 operates over the full 1cm RD3
10k
to 1 meter range of the IrDA standard at the stipulated light
levels. For IrDA data rates of 115kbps and below, a 1.6µs DRIVER
pulse width is used for a zero and no pulse for a one. Light
levels are 40mW/sr (milliwatts per steradian) to 500mW/ Figure 50. IrDA Transmitter
1328_02.eps
sr. Figure 49 shows a scope photo for a transmitter input

(top trace) and the LT1328 output (bottom trace). Note IrDA FIR
that the input to the transmitter is inverted; that is, trans-
mitted light produces a high at the input, which results in The second fastest tier of the IrDA standard addresses
a zero at the output of the transmitter. The Mode pin (pin 576kbps and 1.152Mbps data rates, with pulse widths of
7) should be high for these data rates. 1/4 of the bit interval for zero and no pulse for one. The
1.152Mbps rate, for example, uses a pulse width of 217ns;
An IrDA- compatible transmitter can also be implemented the total bit time is 870ns. Light levels are 100mW/sr to
with only six components, as shown in Figure 50. Power 500mW/sr over the 1cm to 1 meter range. A photo of a
requirements for the LT1328 are minimal: a single 5V transmitted input and LT1328 output is shown in Figure
supply and 2mA of quiescent current. 51. The LT1328 output pulse width will be less than 800ns
C3
wide over all of the above conditions at 1.152Mbps. Pin 7
8
1000pF should be held low for these data rates and above.
IN VBIAS
FILT 7 HIGH – SIR 4ppm

MODE LOW – FIR
LIGHT IN C2 VCC (5V) AND 4PPM
LT1328
10nF
D1
FILT LO VCC
6 The last IrDA encoding method is for 4Mbps and uses
BPU22NF +
TEMIC
C1 C4 C5 pulse position modulation, thus its name: 4ppm. Two bits
330pF 0.1µF 10µF
GND DATA are encoded by the location of a 125ns wide pulse at one
of the four positions within a 500ns interval (2 bits •
TTL DATA OUT 1/500ns = 4Mbps). Range and input levels are the same as
for 1.152Mbps. Figure 52 shows the LT1328 reproduction
Figure 48. LT1328 IrDA Receiver—Typical Application of this modulation.
TRANSMITTER
TRANSMITTER INPUT
INPUT
LT1328 OUTPUT
LT1328 OUTPUT
200ns/DIV
2µs/DIV
Figure 49. IrDA 115kbps Modulation Figure 51. IrDA 1.152Mbps Modulation
AN87-34
Application Note 87
BIAS
TRANSMITTER
INPUT RFB
PHOTO-
DIODE
IN 1 8 VBIAS
D1 PREAMP C3
LT1328 OUTPUT RIN RGM
+
–
200ns/DIV
gm CELL
FILTER 2 7
Figure 52. IrDA 4ppm Modulation C1
C2
MODE
330pF
10nF
3 6
FILTER LO VCC
LT1328 Functional Description
–
Figure 53 is a block diagram of the LT1328. Photodiode GND 4 5 DATA
current from D1 is transformed into a voltage by feedback +

OUT
resistor RFB. The DC level of the preamp is held at VBIAS by

COMPARATOR
the servo action of the transconductance amplifier’s gm.
The servo action only suppresses frequencies below the
Rgm/CFILT pole. This highpass filtering attenuates interfer-
ing signals, such as sunlight or incandescent or fluorescent Figure 53. LT1328 Block Diagram
lamps, and is selectable at pin 7 for low or high data rates.
For high data rates, pin 7 should be held low. The highpass
filter breakpoint is set by the capacitor C1 at f = 25/(2π •
Rgm • C), where Rgm = 60k. The 330pF capacitor (C1) sets
a 200kHz corner frequency and is used for data rates Conclusion
above 115kbps. For low data rates (115kbps and below),
the capacitance at pin 2 is increased by taking pin 7 to a In summary, the LT1328 can be used to build a low cost
TTL high. This switches C2 in parallel with C1, lowering the receiver compatible with IrDA standards. Its ease of use
highpass filter breakpoint. A 10nF cap (C2) produces a and flexibility also allow it to provide solutions to numer-
6.6kHz corner. Signals processed by the preamp/gm ous other photodiode receiver applications. The tiny MSOP
amplifier combination cause the comparator output to package saves on PC board area.
swing low.
AN87-35
Application Note 87
INTERFACE
LTC1387 SINGLE 5V RS232/RS485 MULTIPROTOCOL LTC1387 CONTROLLER
TRANSCEIVER RS232
A
A RA
by Y.K. Sim RS485
120Ω
RA
Introduction RS232
B RB
B RB RX
RS485
The LTC1387 is a single 5V supply, logic-configurable,
single-port RS232 or RS485 transceiver. The LTC1387 Y
DY
offers a flexible combination of two RS232 drivers, two
DY
RS232 receivers, an RS485 driver, an RS485 receiver and DX1
an onboard charge pump to generate boosted voltages for Z DZ/SLEW

DZ VCC
true RS232 levels from a single 5V supply. The RS232 5V
ON
transceivers and RS485 transceiver are designed to share **TX2A-5V
(DPST)
RXEN
the same port I/O pins for both single-ended and differen- RXEN
7.5k
tial signal communication modes. The RS232 transceiver = DXEN
DXEN
supports both RS232 and EIA562 standards, whereas the *FMMT-
619 485/232
MODE
RS485 transceiver supports both RS485 and RS422 * ZETEX (516) 543-7100
** AROMAT (908) 464-3550
standards. Both half-duplex and full-duplex communica- 1387_02.eps
RS232 RS485 RS485 SHUTDOWN
tion are supported. MODE TRANSMIT MODE RECEIVE MODE MODE
RXEN = 1 RXEN = 0 RXEN = 1 RXEN = 0
DXEN = 0 DXEN = 1 DXEN = 0 DXEN = 0
MODE = 0 MODE = 1 MODE = 1 MODE = X
Figure 55. Full-Duplex RS232, Half-Duplex RS485

INTERFACE INTERFACE
LTC1387 CONTROLLER LTC1387 CONTROLLER
RS232
RS232
A RXD A
A RA A RA
RS485 RS485
120Ω 120Ω
RA RA
RX1
RS485 RS485
B RB B RB
B RB B RB
RS232
Y Y
DY Y DY
RS485
DY 120Ω
DX1 DY
DX1
RS485
Z DZ/SLEW Z DZ/SLEW
DZ VCC Z DZ VCC
ON ON
RXEN RXEN
RXEN RXEN
DXEN DXEN
DXEN DXEN
485/232 485/232
MODE MODE
1387_01.eps
1387_03.eps
RS232 RS232 RS485 RS485 SHUTDOWN

TRANSMIT MODE RECEIVE MODE TRANSMIT MODE RECEIVE MODE MODE RS232 MODE RS485 MODE SHUTDOWN MODE
RXEN = 0 RXEN = 1 RXEN = 0 RXEN = 1 RXEN = 0 RXEN = 1 RXEN = 1 RXEN = 0
DXEN = 1 DXEN = 0 DXEN = 1 DXEN = 0 DXEN = 0 DXEN = 1 DXEN = 1 DXEN = 0
MODE = 0 MODE = 0 MODE = 1 MODE = 1 MODE = X MODE = 0 MODE = 1 MODE = X
Figure 54. Half-Duplex RS232, Half-Duplex RS485 Figure 56. Full-Duplex RS232 (1-Channel), Full-Duplex RS422
AN87-36
Application Note 87
A logic input selects between RS485 and RS232 modes. INTERFACE
RS232 LTC1387 CONTROLLER
Three additional control inputs allow the LTC1387 to be RXD A
reconfigured easily via software to adapt to various com- A
RS485
RA
munication needs, including a one-signal line RS232 I/O 120Ω

RA
RX1
mode (see function tables in figures). Four examples of RS232
interface port connections are shown in Figures 54–57. B

CTS B
RB
RB
RX2
RS485
A SLEW input pin, active in RS485 mode, changes the RS232
driver transition between normal and slow slew-rate modes. Y

TXD Y
DY
RS485
In normal RS485 slew mode, the twisted pair cable must 120Ω
DY
be terminated at both ends to minimized signal reflection. DX1
RS232
In slow-slew mode, the maximum signal bandwidth is RTS Z DZ/SLEW
Z DZ DX2/SLEW
reduced, minimizing EMI and signal reflection problems. RS485 ON
ON
Slow-slew-rate systems can often use improperly termi-
RXEN
nated or even unterminated cables with acceptable results. RXEN
If cable termination is required, external termination resis- DXEN
DXEN
tors can be connected through switches or relays. 485/232
MODE
The LTC1387 features micropower shutdown mode, TERMINATE
loopback mode for self-test, high data rates (120kbaud for 1387_04.eps
RS232 and 5Mbaud for RS485) and 7kV ESD protection at RS232 MODE RS485 MODE SHUTDOWN MODE
ON = 1 ON= 1 ON = 0
the driver outputs and receiver inputs. RXEN = 1 RXEN = 1 RXEN = 0
DXEN = 1 DXEN = 1 DXEN = 0
MODE = 0 MODE = 1 MODE = X
Figure 57. Full-Duplex RS232 (2-Channel), Full-Duplex RS485

with Slew and Termination Control
A 10MB/s MULTIPLE-PROTOCOL CHIP SET SUPPORTS LTC1543 is a dedicated data/clock chip and the LTC1544
NET1 AND NET2 STANDARDS is a control-signal chip. The chip set supports the V.28
(RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21
by David Soo protocols in either DTE or DCE mode.
Introduction Figure 58 shows a typical application using the LTC1543,

LTC1544 and LTC1344A. By just mapping the chip pins to
Typical Application the connector, the design of the interface port is complete.
The figure shows a DCE mode connection to a DB-25
Like the LTC1343 software-selectable multiprotocol trans- connector.
ceiver, introduced in the August, 1996 issue of Linear
Technology , the LTC1543/LTC1544/LTC1344A chip set The LTC1543 contains three drivers and three receivers,
creates a complete software-selectable serial interface whereas the LTC1544 contains four drivers and four
using an inexpensive DB-25 connector. The main differ- receivers. The LTC1344A contains six switchable resis-
ence between these parts is the division of functions: the tive terminators that are connected only to the high speed
LTC1343 can be configured as a data/clock chip or as a clock and data signals. When the interface protocol is
control-signal chip using the CTRL/CLK pin, whereas the changed via the mode selection pins, M2, M1 and M0, the
AN87-37
Application Note 87
Cable-Selectable Multiprotocol Interface
Table 4. Mode-Pin Functions
LTC1543/LTC1544 The interface protocol may be selected by simply plugging
Mode Name M2 M1 M0
the appropriate interface cable into the connector. A cable-
Not Used 0 0 0
selectable multiprotocol DTE/DCE interface is shown in
EIA-530A 0 0 1
Figure 61. The mode pins are routed to the connector and
EIA-530 0 1 0
are left unconnected (1) or wired to ground (0) in the cable.
X.21 0 1 1
The internal pull-up current sources ensure a binary 1
V.35 1 0 0
when a pin is left unconnected and also ensure that the
RS449/V.36 1 0 1
LTC1543/LTC1544/LTC1344A enter the no-cable mode
RS232/V.28 1 1 0
when the cable is removed. In the no-cable mode, the
No Cable 1 1 1
LTC1543/LTC1544 power supply current drops to less
than 200µA and all of the LTC1543/LTC1544 driver out-
drivers, receivers and line terminators are placed in their puts will be forced into the high impedance state.
proper configuration. The mode pin functions are summa-
rized in Table 4. There are internal 50µA pull-up current Adding Optional Test Signal
sources on the mode select pins, DCE/DTE and the INVERT
pins. In some cases, the optional test signals local loopback
(LL), remote loopback (RL) and test mode (TM) are
required but there are not enough drivers and receivers
DTE vs DCE Operation available in the LTC1543/LTC1544 to handle these extra
signals. The solution is to combine the LTC1544 with the
The LTC1543/LTC1544/LTC1344A chip set can be LTC1343. By using the LTC1343 to handle the clock and
configured for either DTE or DCE operation in one of two data signals, the chip set gains one extra single-ended
ways. The first way is when the chip set is a dedicated DTE driver/receiver pair. This configuration is shown in Figure
or DCE port with a connector of appropriate gender. The 62.
second way is when the port has one connector that can
be configured for DTE or DCE operation by rerouting the Compliance Testing
signals to the chip set using a dedicated DTE or DCE cable.
A European standard EN 45001 test report is available for
Figure 58 is an example of a dedicated DCE port using a the LTC1543/LTC1544/LTC1344A chip set. The report
female DB-25 connector. The complement to this port is provides documentation on the compliance of the chip set
the DTE-only port using a male DB-25 connector, as to Layer 1 of the NET1 and NET2 standard. A copy of this
shown in Figure␣ 59. test report is available from LTC or from Detecon, Inc. at
1175 Old Highway 8, St. Paul, MN 55112.
If the port must accommodate both DTE and DCE modes,
the mapping of the drivers and receivers to connector pins Conclusion
must change accordingly. For example, in Figure 58,
driver 1 in the LTC1543 is connected to pin 3 and pin 16 In the world of network equipment, the product differen-
of the DB-25 connector. In DTE mode, as shown in Figure tiation is mostly in the software and not in the serial
59, driver 1 is mapped to pins 2 and 14 of the DB-25 interface. The LTC1543, LTC1544 and LTC1344A provide
connector. A port that can be configured for either DTE or a simple yet comprehensive solution to standards compli-
DCE operation is shown in Figure 60. This configuration ance for multiple-protocol serial interface.
requires separate cables for proper signal routing.
AN87-38
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
C13
3 28
1µF
C2
C3 1 1µF
27
1µF
DCE/DTE
C1 CHARGE 26 2
1µF 2 VEE
PUMP C4 C12
M2
M1
M0
4 + 3.3µF 1µF
25
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
1µF LTC1543 VCC 3
24
5 RXD A (104)
RXD D1 23 16
RXD B
22 17
6 RXC A (115)
RXC D2 21 9
RXC B
7
D3
20 15
8 TXC A (114)
TXC R1 19 12
TXC B
18 24
9 SCTE A (113)
SCTE R2 17 11
SCTE B
16 2
10 TXD A (103)
TXD R3 15 14
11 TXD B
M0 7
12 SGND (102)
M1
13
M2 1
14 SHIELD (101)
NC DCE/DTE
VCC DB-25 FEMALE

C10 C9 CONNECTOR
1µF 1µF 1 28
VCC VEE
2 27 C11
VDD GND 1µF
26 5
3 CTS A (106)
CTS D1 25 13
CTS B
24 6
4 DSR A (107)
DSR D2 23 22
DSR B
5
D3
LTC1544
22 8
6 DCD A (109)
DCD R1 21 10
DCD B
20 20
7 DTR A (108)
DTR R2 19 23
DTR B
18 4
8 RTS A (105)
RTS R3 17 19
RTS B
10 16 18
LL R4 LL A (141)
9
D4
11 15
M0 INVERT NC
12
M1
13
M2
14
NC DCE/DTE
M2
M1
M0
Figure 58. Controller-Selectable DCE Port with DB-25 Connector
AN87-39
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
C13
3 28 1µF
C2
C3 1 1µF
27
1µF
DCE/DTE
C1 CHARGE 26 2
1µF 2 VEE
PUMP C4 C12
M2
M1
M0
4 + 3.3µF 1µF
25
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
1µF LTC1543
24 2
5 TXD A (103)
TXD D1 23 14
TXD B
22 24
6 SCTE A (113)
SCTE D2 21 11
SCTE B
7
D3
20 15
8 TXC A (114)
TXC R1 19 12
TXC B
18 17
9 RXC A (115)
RXC R2 17 9
RXC B
16 3
10 RXD A (104)
RXD R3 15 16
11 RXD B
M0 7
12 SG
M1
13
M2 1
14 SHIELD
DCE/DTE
DB-25 MALE
C10 C9 VCC CONNECTOR
1µF 1µF 1 28
VCC VEE
2 27 C11
VDD GND 1µF
26 4
3 RTS A (105)
RTS D1 25 19
RTS B
24 20
4 DTR A (108)
DTR D2 23 23
DTR B
5
D3
LTC1544
22 8
6 DCD A (109)
DCD R1 21 10
DCD B
20 6
7 DSR A (107)
DSR R2 19 22
DSR B
18 5
8 CTS A (106)
CTS R3 17 13
CTS B
10 16 18
LL R4 LL A (141)
9
D4
11 15
M0 INVERT NC
12
M1
13
M2
14
DCE/DTE
M2
M1
M0
Figure 59. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
AN87-40
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
C13
3 28 1µF
C2
C3
1 27 1µF
1µF
DCE/DTE
C1 CHARGE 26 2
1µF 2 VEE
PUMP C4 C12
M2
M1
M0
4 + 3.3µF 1µF
25
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
1µF LTC1543 DTE DCE
24 2
5 TXD A RXD A
TXD B RXD B
22 24
6 SCTE A RXC A
DTE_SCTE/DCE_RXC D2 21 11
SCTE B RXC B
7
D3
20 15
8 S TXC A TXC A
S TXC B TXC B
18 17
9 RXC A SCTE A
RXC B SCTE B
16 3
10 RXD A TXD A
11 RXD B TXD B
M0 7
12 SG
M1
13
M2 1
14 SHIELD
DCE/DTE
VCC DB-25
C10 C9 CONNECTOR
1µF 1µF 1 28
VCC VEE
2 27 C11
VDD GND 1µF
26 4
3 RTS A CTS A
DTE_RTS/DCE_CTS D1 25 19
RTS B CTS B
24 20
4 DTR A DSR A
DTR B DSR B
5
D3
LTC1544
22 8
6 DCD A DCD A
DCD B DCD B
20 6
7 DSR A DTR A
DSR B DTR B
18 5
8 CTS A RTS A
CTS B RTS B
10 16 18
DTE_LL/DCE_LL R4 LL A LL A
9
D4
11 15
M0 INVERT NC
12
M1
13
M2
14
DCE/DTE
DCE/DTE
M2
M1
M0
Figure 60. Controller-Selectable DTE/DCE Port with DB-25 Connector
AN87-41
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
C13
3 28 1µF
C2
C3
1 27 1µF
1µF
DCE/DTE
C1 CHARGE 26 2
1µF 2 VEE
PUMP C4 C12
M2
M1
M0
4 + 3.3µF 1µF
25
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
1µF LTC1543 DTE DCE
VCC
24 2
5 TXD A RXD A
TXD B RXD B
22 24
6 SCTE A RXC A
SCTE B RXC B
7
D3
20 15
8 TXC A TXC A
TXC B TXC B
18 17
9 RXC A SCTE A
RXC B SCTE B
16 3
10 RXD A TXD A
11 RXD B TXD B
M0 7
12 SG
M1
13
NC M2 1
14 SHIELD
DCE/DTE
DB-25
CONNECTOR
C10 VCC
C9 25
1µF 1 28 DCE/DTE
1µF VCC VEE 21
2 27 C11 M1
VDD GND 1µF 18
M0
26 4
3 RTS A CTS A
RTS B CTS B
24 20
4 DTR A DSR A
DTR B DSR B
5
D3
LTC1544
22 8
6 DCD A DCD A
DCD B DCD B
20 6
7 DSR A DTR A
DSR B DTR B
18 5
8 CTS A RTS A
CTS B RTS B
10 16
R4
CABLE WIRING FOR MODE SELECTION CABLE WIRING FOR
9 MODE PIN 18 PIN 21 DTE/DCE SELECTION
D4
V.35 PIN 7 PIN 7 MODE PIN 25
11 RS449, V.36 NC PIN 7
M0 DTE PIN 7
12 RS232 PIN 7 NC DCE NC
M1
13
NC M2
14 15
DCE/DTE INVERT NC
Figure 61. Cable-Selectable Multiprotocol DTE/DCE Port
AN87-42
Application Note 87
C6 C7 C8
100pF 100pF 100pF
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
1 C13
44 1µF
C2
C3 2 1µF
43
1µF
DCE/DTE
C1 42 2
1µF CHARGE VEE
4 C4
PUMP C12
M2
M1
M0
3 + 3.3µF 1µF
41
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
8
1µF LTC1343
DTE DCE
5 39 18
DTE_LL/DCE_TM D1 LL A TM A
38 2
6 TXD A RXD A
TXD B RXD B
36 24
7 SCTE A RXC A
SCTE B RXC B
34
9
D4 33
10
12 32 15
13 TXC A TXC A
TXC B TXC B
30 17 SCTE A
14 RXC A
RXC B SCTE B
28 3 TXD A
15 RXD A
RXD B TXD B
16 26 25
DTE_TM/DCE_LL R4 TM A LL A
20 21 7
CTRL DCE SG
22 19
LATCH M2
11 18 1
INVERT M1 SHIELD
25 17
423SET M0
R1 VCC
100k
40 24
GND EC
LB
23 DB-25
LB CONNECTOR
C10 C9 VCC
1 28
1µF 1µF VCC VEE
2 27 C11
VDD GND 1µF
26 4
3 RTS A CTS A
RTS B CTS B
24 20
4 DTR A DSR A
DTR B DSR B
5
D3
LTC1544
22 8
6 DCD A DCD A
DCD B DCD B
20 6
7 DSR A DTR A
DSR B DTR B
18 5
8 CTS A RTS A
CTS B RTS B
10 16 21
DTE_RL/DCE_RL R4 RL A RL A
9
D4
11 15
M0 INVERT NC
12
M1
13
M2
14
DCE/DTE
DCE/DTE
M2
M1
M0
Figure 62. Controller-Selectable Multiprotocol DTE/DCE Port with RLL, LL, TM and DB-25 Connector
AN87-43
Application Note 87
NET1 AND NET2 SERIAL INTERFACE CHIP SET LTC1545, the optional circuits TM (Test Mode), RL (Remote
SUPPORTS TEST MODE Loopback) and LL (Local Loopback) can now be
by David Soo implemented.
Some serial networks use a test mode to exercise all of the
Figure 64 shows a typical application using the LTC1543,
circuits in the interface. The network is divided into local
LTC1545 and LTC1344A. By just mapping the chip pins to
and remote data terminal equipment (DTE) and data-
the connector, the design of the interface port is complete.
circuit-terminating equipment (DCE), as shown in Figure
The chip set supports the V.28, V.35, V.36, RS449, EIA-
63. Once the network is placed in a test mode, the local DTE
530, EIA-530A or X.21 protocols in either DTE or DCE
will transmit on the driver circuits and expect to receive the
mode. Shown here is a DCE mode connection to a DB-25
same signals back from either a local or remote DCE. These
connector. The mode-select pins, M0, M1 and M2, are
tests are called local or remote loopback.
used to select the interface protocol, as summarized in
Table 5.
The LTC1543/LTC1544/LTC1344A chip set has taken the
integrated approach to multiple protocol. By using this Table 5. Mode-Pin Functions
chip set, the Net1 and Net2 design work is done. The LTC1543/LTC1544
LTC1545 extends the family by offering test mode capabil- Mode Name M2 M1 M0
ity. By replacing the 6-circuit LTC1544 with the 9-circuit Not Used 0 0 0
EIA-530A 0 0 1
EIA-530 0 1 0
LOCAL LOCAL
LL REMOTE RL REMOTE X.21 0 1 1
DTE DCE DCE DTE
V.35 1 0 0
RS449/V.36 1 0 1
RS232/V.28 1 1 0
Figure 63. Serial Network
No Cable 1 1 1
AN87-44
Application Note 87
C6 C7 C8
100pF 100pF 100pF
Just a
marker
3 8 11 12 13
LTC1344A
VCC
5V
14 21
VCC LATCH
C13
3 28 1µF
C3 C2
1 27 1µF
1µF
DCE/DTE
C1 CHARGE 26 2
1µF 2 VEE
PUMP C4 C12
M2
M1
M0
4 + 3.3µF 1µF
25
C5 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1
1µF LTC1543 VCC 3
24
5 RXD A (104)
RXD D1 23 16
RXD B
22 17
6 RXC A (115)
RXC D2 21 9
RXC B
7
D3
20 15
8 TXC A (114)
TXC R1 19 12
TXC B
18 24
9 SCTE A (113)
SCTE R2 17 11
SCTE B
16 2
10 TXD A (103)
TXD R3 15 14
11 TXD B
M0 7
12 SGND (102)
M1
13
M2 1
14 SHIELD (101)
NC DCE/DTE
DB-25 FEMALE
C10 VCC CONNECTOR
C9
1µF 1µF 1 28
VCC VEE
2 27 C11
VDD GND 1µF
26 5
3 CTS A (106)
CTS D1 25 13
CTS B
24 6
4 DSR A (107)
DSR D2 23 22
DSR B
5
D3
LTC1544
22 8
6 DCD A (109)
DCD R1 21 10
DCD B
20 20
7 DTR A (108)
DTR R2 19 23
DTR B
18 4
8 RTS A (105)
RTS R3 17 19
RTS B
10 16 18
LL R4 LL A (141)
9
D4
11 15
M0 INVERT NC
12
M1
13
M2
14
NC DCE/DTE
M2
M1 1544 F23
M0
Figure 64. Typical Application: Controller-Selectable DCE Port with DB-25 Connector
AN87-45
Application Note 87
Operational Amplifiers/Video Amplifiers conventional amplifier would be limited to a battery volt-
age between 5V and ground, but the LT1491 can handle
LT1490/LT1491 OVER-THE-TOP DUAL AND QUAD battery voltages as high as 44V. The LT1491 can be shut
MICROPOWER RAIL-TO-RAIL OP AMPS down by removing VCC. With VCC removed the input
by Jim Coelho-Sousae leakage is less than 0.1nA. No damage to the LT1491 will
result from inserting the 12V battery backward.
Introduction
When the battery is charging, Amp B senses the voltage
The LT1490 is Linear Technology’s lowest power, lowest drop across RS. The output of Amp B causes QB to drain
cost and smallest dual rail-to-rail input and output opera- sufficient current through RB to balance the inputs of Amp
tional amplifier. The ability to operate with its inputs above B. Likewise, Amp A and QA form a closed loop when the
VCC, its high performance-to-price ratio and its availability battery is discharging. The current through QA or QB is
in the MSOP package, sets the LT1490 apart from other proportional to the current in RS; this current flows into
amplifiers. RG, which converts it back to a voltage. Amp D buffers and
amplifies the voltage across RG. Amp C compares the
An Over-the-Top Application output of Amp A and Amp B to determine the polarity of
the current through RS. The scale factor for VOUT with S1
The battery current monitor circuit shown in Figure 65 open is 1V/A. With S1 closed the scale factor is 1V/
demonstrates the LT1491’s ability to operate with its 100mA, and current as low as 5mA can be measured.
inputs above the positive supply rail. In this application, a
RS
CHARGER 0.2Ω
VOLTAGE +
1N4001
VBATTERY = 12V
RA
2k QA
+ 2N3904
1/4
RA' LT1491 –
2k A 1/4
– LT1491 LOGIC
C
+
RB
2k QB VSUPPLY = 5V, 0V
+ 2N3904
1/4
RB' LT1491
RL 2k B
–
+
1/4
RG LT1491 VOUT
10k D
–
LOGIC HIGH (5V) = CHARGING 90.9k
LOGIC LOW (0V) = DISCHARGING
IBATTERY =
(VOUT) VOUT
10k
(RS) (RG/RA) GAIN
= AMPS
GAIN
NOTE: RA = RB S1 = OPEN, GAIN = 1
S1 S1 = CLOSED, GAIN = 10
Figure 65. LT1491 Battery Current Monitor—an “Over-The-Top” Application
AN87-46
Application Note 87
THE LT1210: A 1-AMPERE, 35MHz to be switched into a high impedance, low current mode,
CURRENT FEEDBACK AMPLIFIER reducing dissipation when the device is not in use. The
by William Jett and Mitchell Lee LT1210 is available in the 7-pin TO-220 package, the 7-pin
DD surface mount package and the 16-pin SO-16 surface
Introduction mount package.
The LT1210 current feedback amplifier extends Linear Twisted Pair Driver
Technology’s high speed driver solutions to the 1 ampere
level. The device combines a 35MHz bandwidth with a Figure 66 shows a transformer-coupled application of the
guaranteed 1A output current, operation with ±5V to ±15V LT1210 driving a 100Ω twisted pair. This surge imped-
supplies and optional compensation for capacitive loads, ance is typical of PVC-insulated, 24 gauge, telephone-
making it well suited for driving low impedance loads. grade twisted pair wiring. The 1:3 transformer ratio allows
Short circuit protection and thermal shutdown ensure the just over 1W to reach the twisted pair at full output.
device’s ruggedness. A shutdown feature allows the device Resistor RT acts as a primary side back-termination. The
15V
+
4.7µF* 100nF
INPUT RT
+ 11Ω, 2.5W
LT1210 T1
–
1 3 RL = 100Ω,
2.5W
+ 4.7µF* 100nF
845Ω
–15V
*TANTALUM
274Ω T1 = MIDCOM 671-7783 OR EQUIVALENT
Figure 66. Twisted Pair Is Easily Driven for Applications Such as ADSL.
Voltage Gain is About 12. 5VP–P Input Corresponds to Full Output
15V
INPUT 5.6Ω
+ 2.5W
LT1210
– 680Ω
T1
220Ω 1 3 RL = 100Ω,
5W
– 910Ω
LT1210
+ 5.6Ω T1 = MIDCOM 671-7783 OR EQUIVALENT
2.5W
–15V
Figure 67. In a Bridge Configuration, the LT1210 Can Deliver Almost

5W to a Twisted Pair (and Another 5W to the Back Termination)
AN87-47
Application Note 87
RT = 50Ω
T1
2.5W
T1
RL = 50Ω, 4W
15V RL = 50Ω
15V 2.5W
INPUT
5VPP + 1µF
INPUT
LT1210 5VPP + 330nF
– 10nF LT1210
– 10nF
–15V
680Ω –15V
680Ω
220Ω
220Ω
T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2

T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2
Figure 68. Matched to a 50Ω Load with a Balun-Mode Figure 69. Wide Bandwidth can be Obtained with Even Higher
Transformer, this Circuit Delivers a Measured 35.6dBm (almost Impedance Transformations. Here, a 1:3 Step-Up Matches 100Ω
4W). Full-Power Band Limits are 15kHz to Slightly Over 10MHz and Develops Nearly 4.5W. A Measured +33dBm Reaches the
50Ω Load. Full-Power Band Limits Are 80kHz to 18MHz
overall frequency response is flat to within 1dB from
500Hz to 2MHz. Distortion products at 1MHz are below Suitable off-the-shelf components are available, such as
–70dBc at a total output power of 560mW (load plus the Coiltronics Versa-Pac™ series. These are hexafilar
termination), rising to –56dBc at 2.25W. wound and give power bandwidths in excess of 10MHz.
One disadvantage is that using a limited number of 1:1
On a ±15V supply, a maximum output power of 5W is windings makes it impossible to exactly transform 50Ω to
available when a 10Ω load is presented to the LT1210. the optimum 10Ω load. Nevertheless, there are several
With the transformer shown in Figure 66, a total load useful connections.
impedance of approximately 22Ω limits the output to
2.25W. Bridging allows nearly maximum output power to In Figure 68 the windings are configured for a 2:4 step-up,
be delivered into standard 1:3 data communications trans- reflecting 12.5Ω into the LT1210. The circuit exhibits 18dB
formers. Figure 67 shows a bridged application with two gain and drives 50Ω to nearly +36dBm. The large-signal,
LT1210s, delivering approximately 9W maximum into the low frequency response is limited by the magnetizing
load and termination. inductance of the transformer to about 15kHz. The high
frequency response is limited to 10MHz by the stack of four
At first glance the resistor values would suggest a gain secondary windings.
imbalance between the inverting and noninverting sides of
the bridge. On close inspection, however, it is apparent Reconfiguring the transformer windings allows double
that both sides operate at a closed loop gain of 4 relative termination at full power (Figure 69). Here the transformer
to the input signal. This ensures symmetric swing and reflects 11.1Ω and the amplifier delivers over +33dBm to
maximum undistorted output. the load. Paralleled input windings limit the low frequency
response to 80kHz, but fewer series secondary windings
Matching 50Ω Systems extend the high frequency corner to 18MHz.
Few practical systems exhibit a 10Ω impedance, so a The coupling capacitor shown in these examples is added
matching transformer is necessary for applications driv- to block current flow through the transformer primary,
ing other loads, such as 50Ω. Multifilar winding tech- arising from amplifier offsets. The capacitor value is based
niques exhibit the best high frequency characteristics. on setting XC equal to the reflected load impedance at the
AN87-48
Application Note 87
26
15V
INPUT 23
5VP–P + 20
LT1210
T1 17
– 10nF RL = 50Ω, 9W 14
GAIN (dB)
11
680Ω 8
5
100nF
2
220Ω
–1
–4
0.01 0.1 1.0 10.0 100
– 910Ω FREQUENCY (MHz)
LT1210
+
10nF Figure 71. Frequency Response of Figure 70's Circuit
–15V
T1 = CTX-01-13033-X2 VERSA-PAC
Another useful connection for the Versa-Pac transformer
is shown in Figure 70. A 2:3 transformation presents
Figure 70. In this Bridge Amplifier, the LT1210 Delivers
+39.5dBm (9W) to a 50Ω Load. Power Band Limits Range from
11.1Ω to each LT1210 in a bridge, delivering a whopping
40kHz to 14.5MHz. The Sixth, Otherwise-Unused Winding is 9W into 50Ω. In this circuit the lower frequency cutoff was
Connected in Parallel with One Secondary Winding to Avoid limited by the choice of coupling capacitor to approxi-
Parasitic Effects Arising from a Floating Winding. mately 40kHz (the transformer is capable of 15kHz). The
frequency response is shown in Figure 71.
frequency where XL of the primary is also equal to the Conclusion

reflected load. This isolates the amplifier from a low
impedance short at frequencies below transformer cutoff. The LT1210 combines high output current with a high slew
In applications where a termination resistor is positioned rate to form an effective solution for driving low impedance
between the LT1210 amplifier and the transformer, no loads. Power levels of up to 5W can be supplied to a load
coupling capacitor is necessary. Note that a low frequency at frequencies ranging from DC to beyond 10MHz.
signal, well below the transformer’s cutoff frequency,
could result in high dissipation in the termination resistor.
AN87-49
Application Note 87
THE LT1207: AN ELEGANT DUAL 60MHZ, 250mA fier. R1 produces heat when the LT1207 drives it differen-
CURRENT FEEDBACK AMPLIFIER tially. This heat lowers D1’s voltage. Differentially con-
by LTC Applications Staff nected A3 responds by driving R2, heating D2 and closing
the loop. A3’s DC output directly relates to the input
Introduction signal’s RMS value, regardless of input frequency or wave
shape. A4’s gain trim compensates residual LT1088 mis-
The LT1207 is a dual version of Linear Technology’s matches. The RC network around A3 frequency compen-
LT1206 current feedback amplifier. Each amplifier has sates the loop, ensuring good settling time.
60MHz bandwidth, guaranteed 250mA output current,
operates on ±5V to ±15V supply voltages and offers The LT1088 can suffer damage if the 250Ω input is driven
optional external compensation for driving capacitive loads. beyond 9VRMS at 100% duty cycle. An easy remedy to this
These features and capabilities combine to make it well possibility is to reduce the driver supply voltage. This,
suited for such difficult applications as driving cable loads, however, sacrifices crest factor. Instead, a means of
wide-bandwidth video and high speed digital overload protection is included. The LT1018 monitors
communication. D1’s anode voltage. Should this voltage become abnor-
mally low, A5’s output goes low and pulls A6’s input low.
LT1088 Differential Front End This causes A6’s output to go high, shutting down the
LT1207 and eliminating the overload condition. The RC
Using thermal conversion, the LT1088 wideband RMS/DC network on A6’s input delays the LT1207’s reactivation. If
converter is an effective solution for applications such as the overload condition remains, shutdown is reinstated.
RMS voltmeters, wideband AGC, RF leveling loops and This oscillatory action continues, protecting the LT1088
high frequency noise measurements. Its thermal conver- until the overload is corrected. The RMS/DC circuit’s 1%
sion method achieves vastly wider bandwidth than any error bandwidth and CMRR performance are shown in
other approach. It can handle input signals that have a Figures 73 and 74, respectively.
300MHz bandwidth and a crest factor of at least 40:1. The
thermal technique employed relies on first principles: a CCD Clock Driver
wave form’s RMS value is defined as its heating value in a
load. Another characteristic of the LT1088 is its low Charge-coupled-devices (CCDs) are used in many imag-
impedance inputs (50Ω and 250Ω), common to thermal ing applications, such as surveillance, hand-held and
converters. Though this low impedance represents a dif- desktop computer video cameras, and document scan-
ficult load to most drive circuits, the LT1207 can handle it ners. Using a “bucket-brigade,” CCDs require a precise
with ease. multiphase clock signal to initiate the transfer of light-
generated pixel charge from one charge reservoir to the
Featuring high input impedance and overload protection, next. Noise, ringing or overshoot on the clock signal must
the differential input, wideband thermal RMS/DC con- be avoided, since they introduce errors into the CCD
verter in Figure 72 performs true RMS/DC conversion over output signal. These errors cause aberrations and pertur-
a 0Hz to 10MHz bandwidth with less than 1% error, bations in a displayed or printed image.
independent of input-signal wave shape. The circuit con-
sists of a wideband input amplifier, RMS/DC converter and Two challenges surface in the effort to avoid these error
overload protection.1 The LT1207 provides high input sources when driving a CCD’s input. First, CCDs have an
impedance, gain and output current capability necessary input capacitance that varies over a range of 100pF to
to drive the LT1088’s input heater. The 5k/24pF network 2000pF and varies directly with the number of sensing
across the LT1207’s 180Ω gain-set resistor is used to elements (pixels). This presents a high capacitive load to
adjust a slight peaking characteristic at high frequencies, the clock-drive circuitry. Second, CCDs typically require a
ensuring 1% flatness at 10MHz. The converter uses clock signal whose magnitude is greater than the output
matched pairs of heaters and diodes and a control ampli- capabilities of 5V interfaces and control circuitry. An
AN87-50
0.022µF
1.5M 1k
3300pF
ZERO TRIM
(TRIM AT 1V OUTPUT)
9.09M
15V
0.1µF
10µF
LT1004
+
15V
5V 500Ω 1.2V
0.1µF 2.7k 2.7k

1k 2 8
– A3 1 1k
3 1,16 1/2 Q1
+ 1k LT1078 2N2219
A1 3
15 +
1/2
2 LT1207 4
– 0.01µF 9.09M
14
0.1µF
12 5
806Ω 3k
10µF 3 250Ω 250Ω 10
–5V R1 R2
+
10k
LT1088 5
FULL-SCALE +
24pF TRIM A4 7
1/2 VOUT
VIN 180Ω D1 D2 6 LT1078
10MHz –
5k 4 10k
TRIM 0.1µF
7
–15V
10µF 14
–15V
+
5V
0.1µF
0.1µF 806Ω 1 13 6 8 10k
5 8,9
–
A2 12
1/2 0.1µF
6 LT1207 7
+ 15V 15V 15V
11
0.1µF
3 8 1k 510k
+ A5 1N914
1 6
10µF 1/2 +
2 LT1018 A6 7 12k
–5V – 0.1µF 1/2 15V
+
15V 5 LT1018
– 4
0.1µF
2k
–15V
4.7k
LT1004 –15V
10k 1.2V
Figure 72. Differential Input 10MHz RMS/DC Converter has 1% Accuracy, High Input Impedance and Overload Protection.
10k
Application Note 87
AN87-51
Application Note 87
1.0
COMMON MODE REJECTION RATIO, VCM = 5VRMS

>>1000:1
A
1000:1
0.5 900:1
800:1
ERROR (%)
700:1
0 600:1
B
500:1
1% ERROR
400:1 POINT
–0.5 300:1 = 10.2MHz
200:1
100:1
–1.0 0
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 73. Error Plot for the Differential-Input RMS/DC Figure 74. Common Mode Rejection Ratio vs Frequency for the
Converter. Gain Boost at A2 Preserves 1% Accuracy but Differential-Input RMS/DC Converter. Layout, Amplifier
Causes Slight Peaking before Roll-Off. Boost Can be Set Bandwidth and AC Matching Characteristics Determine the Curve
for Maximum Bandwidth (A) or Minimum Error (B)
10µF
+
45pF 20V
0.1µF
SIMULATED
CCD ARRAY LOAD
1k 1k 1k 3 1,16
+
15 10Ω
180pF 91pF 1/2
LT1207 13
2
– 14
3300pF
5V 0.1µF 0.1µF
4
4
5
3 1Q 10µF
CLK 1CK 500kHz
2 –10V
1D 6
+
1 1Q 1k
2MHz
10 74HC74
9 500kHz 510k
11 2Q
2CK
12
2D 8
13 2Q
10µF
+
45pF 20V
0.1µF
1k 1k 1k 6 8,9
+
12 10Ω
180pF 91pF 1/2
LT1207 10
5
– 11
3300pF
0.1µF 0.1µF
7
10µF
–10V
+
1k
510k
Figure 75. The LT1207 Easily Tames the High Capacitance Loads of CCD Clock Inputs without Ringing or Overshoot
AN87-52
Application Note 87
A A
B B
Figure 76a. Trace A is the Quadrature Drive Signals. Trace B. Figure 76b. Trace A is the Quadrature Signals. Trace B
is the Voltage at the Input of the Simulated CCD of Figure 75, Shows the Voltage at the Input of the Simulated CCD of
Driven by HC Logic Figure 75, Driven by the LT1207
amplifying filter built around the LT1207 will meet both major weaknesses that lead to jitter and image distortion.
challenges. The CCD’s output is changing during charge transfer,
producing glitches that decay exponentially. Conversely,
Controlling clock signal rise and fall times is one way to the LT1207 circuit's output has a flat top and controlled
avoid ringing or overshoot. This is done by conditioning rise and fall. If an ADC is used to sample a CCD output, the
the clock signal with a nonringing Gaussian filter. The conversion will be much more accurate when the LT1207
circuit shown in Figure 75 uses the LT1207 to filter and circuit is used to clock the pixel changes. With the LT1207’s
amplify control circuitry clock output signals. To reduce filter configuration, the output has a controlled rise and fall
ringing and overshoot, each amplifier is configured as a time of approximately 300ns. Ringing and overshoot are
third-order Gaussian lowpass filter with a 1.6MHz cutoff absent from the LT1207’s output. Wide bandwidth, high
frequency. output current capability and external compensation allow
the LT1207 to easily drive the difficult load of a CCD’s clock
Figures 76a and 76b compare the response of a digital 5V input.
clock-drive signal and the output of the LT1207, each 1. Thanks to Jim Williams for this Circuit
driving a 3300pF load. The digital clock circuit has two
AN87-53
Application Note 87
MICROPOWER, DUAL AND QUAD JFET OP AMPS Applications
FEATURE C-LOAD CAPABILITY AND PICOAMPERE
INPUT BIAS CURRENTS Figure 77 is a track-and-hold circuit that uses a low cost
by Alexander Strong optocoupler as a switch. Leakages for these parts are
usually in the nano amp region with 1 to 5 volts across the
Introduction output. Since there is less than 2mV across the junctions,
less than 0.5pA leakage can be achieved for both opto-
The LT1462/LT1464 duals and the LT1463/LT1465 quads couplers. The input signal is buffered by one op amp while
are the first micropower op amps (30µA typical, 40µA the other buffers the stored voltage; this results in a droop
maximum per amp for the LT1462; 140µA typical, 200µA of 50µV/s with a 10nF cap.
maximum per amp for the LT1464) to offer both pico
ampere input bias currents (500fA typical) and unity-gain Figure 78 is a logging photodiode sensor using two
stability for capacitive loads up to 10nF. The outputs can LT1462 duals or an LT1463 quad. The low input bias
swing a 10k load to within 1.5 volts of either supply. Just current of the LT1462/LT1463 makes it a natural for
like op amps that require an order of magnitude more amplifying low level signals from high impedance trans-
supply current, the LT1462/LT1463 and the LT1464/ ducers. The 500fA of input bias current contributes only
LT1465 have open loop gains of 600,000 and 1,000,000, 0.4fA/√Hz of current noise. For example, a 1M input
respectively. These unique features, along with a 0.8mV impedance converts the noise current to a noise voltage of
offset, have not been incorporated into a single monolithic only 0.4nV/√Hz. Here, a photodiode converts light to a
amplifier before.
V+
1/4
LTC201 13 15
16
A
C1, 10nF
1 MCT2 5 POLYSTYRENE
4 14
V–
V+
5 2 – 8
+ 2 6 4
1/2 7 *R1 1/2 1
LT1464 LT1464 VOUT
6 3 +
IN – 1 MCT2 5
4
1/4 V–
LTC201 2
1
B 2 6 4
0.5pA
TYPICAL DROOP = = 0.05mV/SEC.
3 10nF
TOTAL SUPPLY CURRENT = 460µA MAX.
*R1 = 600Ω FOR ±15V SUPPLIES,
FUNCTION MODE IN A IN B MODE IN A IN B R1 = 0Ω FOR ±5V SUPPLIES
TRACK AND HOLD TRACK 0 0 HOLD 1 1

POSITIVE PEAK DETECTOR RESET 0 0 STORE 0 1
NEGATIVE PEAK DETECTOR RESET 0 0 STORE 1 0
LTC201 SWITCH IS OPEN FOR LOGIC “1” 1464_02.eps
Figure 77. Low-Droop Track-and-Hold Circuit/Peak Detector
AN87-54
Application Note 87
R8 Q1
100k 2N3904
D1 C5
1N4148 1µF
C1
1nF
R9
1M
+5
R1
100Ω 2 – 8 R2
24k DC
1/2 1 5 OUT
LT1462 + R5
C3
3 + C2 1/2 7 24k 3
200pF LT1462 + 0.47µF
4 6 1/2 1
C5
–5
– 200pF LT1462 +5
R4 2
PHOTODIODE 10M – C4
R7 R10 5 8
10M
+ 10µF
D2 50k 1/2 7
+
AC
1N4148 LT1462 OUT
D3 6
1N4148 – 4
R13
10k
R3 R11
100k –5 1M
R6
100k
R12
10k
Figure 78. Logging Photodiode Amplifier

1464_03.eps DBD
Conclusion
current, which is converted to a voltage by the first op amp. The LT1462/LT1464 duals and the LT1463/LT1465 quads
The first, second and third gain stages are logarithmic combine many advantages found in many different op
amplifiers that perform a logarithmic compression. A DC amps, such as low power, (LT1464/LT1465 are 140µA,
feedback path comprising R8, R9, C5 and Q1 is active only LT1462/LT1463 are 30µA typical per amplifier), wide
for no-light conditions, which are very rare, due to the input common mode range that includes the positive rail
picoampere sensitivity of the input. Q1 is off when light is and pico ampere input bias currents. Not only is the output
present, isolating the photodiode from C5. When the swing specified with 2k and 10k loads, gain is also
feedback path is needed, a small filtered current through specified for the same load conditions, which is unheard-
R8 keeps the output of the third op amp within an accept-
1.6
able range. The third op amp’s output voltage, which is
proportional to the photodiode current, can serve as a 1.4
logarithmic DC light meter. Figure 79 shows the relation- 1.2
ship between DC output voltage and photodiode current.

DC OUTPUT (v)
1.0
The AC component of the output of third op amp is 0.8
compressed logarithmically and passed through capacitor
0.6
C3 and pot R10 for amplitude control. The fourth op amp
0.4
amplifies this AC signal which is generated across R13.
The logarithmic compression of the AC photodiode cur- 0.2
rent allows the user to examine the AC signals for a wide 0

10 –11 10 –9 10 –7 10 –5 10 –3
range of input currents. PHOTODIODE CURRENT (A)
1464_04.eps
Figure 79. DC Output of Logging Photodiode Amplifier
AN87-55
Application Note 87
of for micropower op amps. The 1MHz (LT1464/LT1465) don’t forget the low 0.8mV offset voltage and DC gains of
or 250kHz (LT1462/LT1463) bandwidth self adjusts to 1 million (LT1464/LT1465) or 600,000 (LT1462/LT1463)
maintain stability for capacitive loads up to 10nF. And even with 10k loads.
THE LT1210: HIGH POWER OP AMP YIELDS it while the second LT1210 further amplifies the input
HIGHER VOLTAGE AND CURRENT signal. This telescoping arrangement can be cascaded
by Dale Eagar with additional stages to get more than ±30V. This ampli-
fier is stable into capacitive loads, is short-circuit pro-
Introduction tected and thermally shuts down when overheated.
The LT1210, a 1 amp current feedback operational amplifier, Extending Power Supply Voltages
opens up new frontiers. With 30MHz bandwidth, operation
on ±15V supplies, thermal shutdown and 1 amp of output Another method of getting high voltage from an amplifier
current, this amplifier single-handedly tackles many tough is the extended-supply mode (see “Extending Op Amp
applications. But can it handle output voltages higher than Supplies to Get More Voltage”; Linear Technology Vol-
±15V or currents greater than 1 ampere? This Design Idea ume IV Number 2 (June 1994), pp. 20–22). This involves
features a collection of circuits that open the door to high steering two external regulators with the power supply
voltage and high current for the LT1210. pins of an op amp to get a high voltage amplifier.
Fast and Sassy—Telescoping Amplifiers Figure 82 shows the LT1210 connected in the extended-
supply mode. Placing an amplifier in the extended-supply
Need ±30V? Cascading LT1210’s will get you there. This mode requires changing the return of the compensation
circuit (Figure 80) will provide the ±30V at ±1A and has node from the power supply pins to system ground. R9
13MHz of full-power bandwidth (see Figure 81). How does and C5 are selected for clean step response. The process
it work? The first LT1210 drives the “ground” of the of relocating the return of the compensation node slows
second LT1210 subcircuit, effectively raising and lowering the amplifier down to approximately 1MHz (see Figure␣ 83).
1k
30V
TIP 29
15V 1µF
1kΩ
1k
15V
1µF 1 4 1k
INPUT 300Ω –
1 4 7
– LT1210 OUTPUT
7 2 5
LT1210 + 6
60Ω 2 5
+ 6 3
3 0.01µF
0.01µF 6.2k
1µF
6.2k
–15V
15V
1µF TIP 30
1k
–30V
Figure 80. Telescoping Amplifiers
AN87-56
Application Note 87
30
25
20
50Ω LOAD
15
10
GAIN (dB)
5 FIGURE 80's CKT

+10dBM INPUT
50Ω LOAD
0
–5
–10
–15
–20
10K 100K 1M 10M 60M
FREQUENCY (Hz)
Figure 81. Gain vs Frequency Plot of Telescoping Amplifier
Figure 82’s circuit will provide ±1A at ±100V, is stable into Boosting Both Current and Voltage
capacitive loads and is short-circuit protected. The two
external MOSFETs need heat sinking. The current-boosted amplifier shown in Figure 85 can be
used to replace the amplifiers in Figure 80, yielding ±10A
Gateway to the Stars at ±30V. Placing the boosted amplifier in the circuits
shown in Figures 82 or 84 will yield peak powers into the
The circuit of Figure 82 can be expanded to yield much kilowatts.
higher voltages; the first and most obvious way is to use
higher voltage MOSFETs. This causes two problems: first, Thermal Management
high voltage P-channel MOSFETs are hard to get; second,
and more importantly, at ±1A the power dissipated by the When the LT1210 is used with external transistors to
MOSFETs is too high for single packages. The solution is increase its output voltage and/or current range an
to build telescoping regulators, as shown in Figure 84. 100V
This circuit can provide ±1A of current at ±200V and has 100V
100k
100Ω
the additional power-dissipation ability of four MOSFETs. R8 IRF640
300Ω 15V
Boosting Output Current INPUT

R7
0.01µF
10k 1k P6KE
1 4
– 15A
220Ω
The current booster detailed in Figure 85 illustrates a LT1210
7
2 5
technique for amplifying the output current capability of an + 6 LOAD
C5 0.01
op amp while maintaining speed. Among the many nice- R9
9.1k 8pF 3
ties of this topology is the fact that both Q1 and Q2 are 15k P6KE
normally off and thus consume no quiescent current. 15A
15V
Once the load current reaches approximately 100mA, Q1
or Q2 turns on, providing additional drive to the output. AV = −
(
R8 R9 += R10 ) R10 300Ω
0.01µF
R8 R9 − R7 R10 100Ω
This transition is seamless to the outside world and takes IRF9640
100k
advantage of the full speed of Q1 and Q2. This circuit’s –100V
small-signal bandwidth and full-power bandwidth are –100V
shown in Figure 86. Figure 82. ±100V, ±1A Power Driver
AN87-57
Application Note 87
30
25 90Vp-p INTO 50Ω
20
15
10
GAIN (dB)
5
FIGURE 82 CKT
0
–5
–10
–15
–20
10K 100K 1M 10M 60M
FREQUENCY (Hz)
Figure 83. Gain vs Frequency Plot of Extended-Supply Amplifier
200V additional benefit can often be realized: system thermal

shutdown. Careful analysis of the thermal design of the
10k 0.47µF
250V
system can coordinate the overtemperature shutdown of
1W
the LT1210 with the junction temperatures of the external
15V IRF640 transistors. This essentially extends the umbrella of pro-
tection of the LT1210’s thermal shutdown to cover the
10k
1W external transistors. The thermal shutdown of the LT1210
IRF640 activates when the junction temperature reaches 150˚C
0.1µF
15V and has about 10˚C hysteresis. The thermal resistance
220Ω
RθJC of the TO-220 package (LT1210CY) is 5˚C/Watt).
300Ω
18V
10k
INPUT 1k
5W 1
– 4 ±1A
7 ±200V R1 0.01µF
0.033Ω
LT1210 6.2Ω
2 5 LOAD
+ 6
C5 Q1, D45VH4
R9
9.1k 8pF 3 0.01µF
3.6k
300Ω
1.8k 1 4
15V
IN –
0.1 7
100Ω LT1210 OUT
IRF9640 2 5
10k
+ 6
1W 15V 3
0.01
Q2, D44VH4
IRF9640
10k R2 0.033Ω
0.47µF 6.2Ω
1W 0.01µF
250V
–18V
–200V
Figure 84. Cascode Power Amplifier Figure 85. ±10A/1MHz Current-Boosted Power Op Amp
AN87-58
Application Note 87
8
4AP–P INTO 1Ω
7
6
50Ω LOAD
5
4
GAIN (dB)
FIGURE 85 CKT
3
+10dBM INPUT
1
1Ω LOAD
0
–1
–2
10K 100K 1M 10M
FREQUENCY (Hz)
Figure 86. Gain vs Frequency Response of Current-Boosted Amplifier
Summary
The LT1210 is a great part; its performance in terms of isn’t big enough for your needs, just add a couple of
speed, output current and output voltage is unsurpassed. transistors to dissipate the additional power and you are
Its C-Load™ output drive and thermal shutdown allow it to on your way. Only the worldwide supply of transistors
take its place in the real world—no kid gloves are required limits the amount of power you could command with one
here. If the generous output specification of the LT1210 of these parts.
NEW RAIL-TO-RAIL AMPLIFIERS: PRECISION used by both input and output signals, maximizing the
PERFORMANCE FROM MICROPOWER TO HIGH SPEED system’s dynamic range. Circuits that require signal sens-
by William Jett and Danh Tran ing near the positive supply are straightforward using a
rail-to-rail amplifier.
Introduction
Applications
Linear Technology’s latest offerings expand the range of
rail-to-rail amplifiers with precision specifications. Rail- The ability to accommodate any input or output signal that
to-rail amplifiers present an attractive solution for signal falls within the amplifier supply range makes these
conditioning in many applications. For battery-powered or amplifiers very easy to use. The following applications
other low voltage circuitry, the entire supply voltage can be demonstrate the versatility of the family of amplifiers.
6.81k 100pF
6.81k 11.3k 5.23k 47pF

VIN –
5.23k 10.2k
330pF 1/2 LT1498 –
+ 1000pF 1/2 LT1498 VOUT
+
VS
—
2 R2R_04.eps
Figure 87. 100kHz 4th Order Butterworth Filter
AN87-59
F
Application Note 87
10 10 10
0 VS = 3V VS = 3V
–10 f = 20kHz VO = 2.7VP-P
VS = 3V
–20 VIN = 2.7VP-P 1 1
–30
THD + NOISE (%)

GAIN (dB)
–40
THD (%)
–50 0.1 0.1
–60
–70
–80 0.01 0.01
–90
–100
–110 0.001 0.001
100 1k 10k 100k 1M 10M 0.01 0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz) AMPLITUDE (VP-P) FREQUENCY (Hz)
R2R_05.eps R2R_06.eps R2R_07.eps
Figure 88. Filter Frequency Response Figure 89. Filter Distortion Figure 90. Filter Distortion
vs Amplitude vs Frequency
100kHz 4th Order Butterworth Filter for 3V Operation
The filter shown in Figure 87 uses the low voltage opera- precision VOS specifications over the entire rail-to-rail
tion and wide bandwidth of the LT1498. Operating in the input range and have open loop gains of one million or
inverting mode for lowest distortion, the output swings more. These characteristics, combined with low voltage
rail-to-rail. The graphs in Figures 88–90 display the mea- operation, makes for truly versatile amplifiers.
sured lowpass and distortion characteristics with a 3V
power supply. As seen from the graphs, the distortion with 5V
a 2.7VP–P output is under 0.03% for frequencies up to the VIN1 +

cutoff frequency of 100kHz. The stop band attenuation of LT1218 S/D VOUT
the filter is greater than 90dB at 10MHz. –
Multiplexer
5V
A buffered MUX with good offset characteristics can be
VIN2 +
constructed using the shutdown feature of the LT1218. In
LT1218 S/D
shutdown, the output of the LT1218 assumes a high –
impedance, so the outputs of two devices can be tied
together (wired OR, as they say in the digital world). As
shown in Figure 91, the shutdown pins of each LT1218 are INPUT
SELECT R2R_08.eps
driven by a 74HC04 buffer. The LT1218 is active with the 74HC04
shutdown pin high. The photo in Figure 92 shows the
switching characteristics with a 1kHz sine wave applied to Figure 91. MUX Amplifier
one input and the other input tied to ground. As shown,
each amplifier is connected for unity gain, but either
amplifier or both could be configured for gain. VIN1
VOUT
Conclusion
INPUT
SELECT
The latest members of LTC’s family of rail-to-rail amplifiers
expand the versatility of rail-to-rail operation to micro-
power and high speed applications. The devices maintain Figure 92. MUX Amplifier Waveforms
AN87-60
Application Note 87
LT1256 VOLTAGE-CONTROLLED AMPLITUDE LIMITER which have a very large dynamic range. Although this
by Frank Cox circuit was developed for video signals, it can be used to
adaptively compress any signal within the 40MHz band-
Amplitude-limiting circuits are useful where a signal should
width of the LT1256.
not exceed a predetermined maximum amplitude, such as
when feeding an A/D or a modulator. A clipper, which The LT1256 video fader is connected to mix proportional
completely removes the signal above a certain level, is amounts of input signal and clipped signal to provide a
useful for many applications, but there are times when it is voltage-controlled variable gain. The clipped signal is
not desirable to lose information. For instance, when video provided by a discrete circuit consisting of three transis-
signals have amplitude peaks that exceed the dynamic tors. Q1 acts as an emitter follower until the input voltage
range of following processing stages, simply clipping the exceeds the voltage on the base of Q2 (the breakpoint
peaks at the maximum level will result in the loss of all voltage or VBP). When the input voltage is greater than
detail in the areas where clipping takes place. Often these VBP, Q1 is off and Q2 clamps the emitters of the two
well illuminated areas are the primary subject of the scene. transistors to VBP plus a VBE. Q3, an NPN emitter follower,
Because these peaks usually correspond to the highest
level of luminosity, they are referred to as “highlights.” One
way to preserve some of the detail in the highlights is to
automatically reduce the gain (compress) at high signal
levels.
The circuit in Figure 93 is a voltage-controlled breakpoint

amplifier that can be used for highlight compression.
When the input signal reaches a predetermined level (the
breakpoint), the amplifier gain is reduced. As both the
breakpoint and the gain for signals greater than the
breakpoint are voltage programmable, this circuit is useful Figure 94. Multiple-Exposure Photograph of a Single
for systems that adapt to changing signal levels. Adaptive Line of Monochrome Video, Showing Four Different
highlight compression finds use in CCD video cameras, Levels of Compression
5V
Q1, Q2 = 2N4957 2k 1.5k

LT1256
Q3 = 2N2857
–
VIDEO Q3
IN 100Ω
Q1 Q2 + 1.5k 5V
VIDEO
75Ω 2k 75Ω OUT
10k
TO VFS
–5V
1.5k LT1256, PIN 12
+
TO VCONTROL
5V LT1004-2.5 100k LT1256, PIN 3
100Ω
BREAK POINT –
VOLTAGE
+
LT1363
–
510Ω
1.5k
–5V
Figure 93. Voltage-Controlled Amplitude Limiter
AN87-61
Application Note 87
buffers the output and drops the voltage a VBE and thus the Figure 94 is a multiple-exposure photograph of a single
DC level of the input signal is preserved to the extent line of monochrome video, showing four different levels of
allowed by the VBE matching and temperature tracking of compression ranging from fully limited signal to unproc-
the transistors used. The breakpoint voltage at the base of essed input signal. The breakpoint is set to 40% of the
Q2 must remain constant when this transistor is turning on peak amplitude to clearly show the effect of the circuit;
or the signal will be distorted. The LT1363 maintains a low normally only the top 10% of video would be compressed.
output impedance well beyond video frequencies and
makes an excellent buffer.
THE LT1495/LT1496: 1.5µA RAIL-TO-RAIL OP AMPS

by William Jett
readout is taken from a 0µA–200µA, 500Ω analog meter;
Introduction the LT1495 supplies a current gain of 1000 in this applica-
tion. The op amp is configured as a floating I-to-I con-
Micropower rail-to-rail amplifiers present an attractive verter. It consumes only 3µA when not in use, so there is
solution for battery-powered and other low voltage cir- no need for an on/off switch. Resistors R1, R2 and R3 set
cuitry. Low current is always desirable in battery-powered the current gain. R3 provides a ±10% full- scale adjust for
applications, and a rail-to-rail amplifier allows the entire the meter movement. With a 3V supply, maximum current
supply range to be used by both the inputs and the output, in the meter is limited by R2 + R3 to less than 300µA,
maximizing the system’s dynamic range. Circuits that protecting the movement. Diodes D1 and D2 and resistor
require signal sensing near either supply rail are easier to R4 protect the inputs from faults up to 200V. Diode
implement using rail-to-rail amplifiers. However, until currents are below 1nA in normal operation, since the
now, no amplifier combined precision offset and drift maximum voltage across the diodes is 375µV, the VOS of
specifications with a maximum quiescent current of 1.5µA. the LT1495. C1 acts to stabilize the amplifier, compensat-
ing for capacitance between the inverting input and ground.
Operating on a minuscule 1.5µA per amplifier, the LT1495 The unused amplifier should be connected as shown for
dual and LT1496 quad rail-to-rail amplifiers consume minimum supply current. Error terms from the amplifier
almost no power while delivering precision performance (base currents, offset voltage) sum to less than 0.5% over
associated with much higher current amplifiers. the operating range, so the accuracy is limited by the
analog meter movement.
The LT1495/LT1496 feature “Over-The-Top” operation:
the ability to operate normally with the inputs above the C1
100pF
positive supply. The devices also feature reverse-battery
protection. R1
10M
R4
Applications 10k
–
1/2
– 1.5V
LT1495
INPUT D1, D2 1/2
The ability to accommodate any input or output signal that CURRENT 2× LT1495 +
1N914
+ R2 1.5V
falls within the amplifier supply range makes the LT1495/ 9k
LT1496 very easy to use. The following applications R3

2k
highlight signal processing at low currents.
µA 0µA TO
Nanoampere Meter 200µA
1495_05.eps
A simple 0nA–200nA meter operating from two flashlight

cells or one lithium battery is shown in Figure 95. The Figure 95. 0nA–200nA Current Meter
AN87-62
Application Note 87
100k
1kHz. As with all RC filters, the filter characteristics are
15nF 15nF
determined by the absolute values of the resistors and
e IN
215k 215k
+ capacitors, so resistors should have a 1% tolerance or
215k 10k
100nF 1/2 LT1495 better and capacitors a 5% tolerance or better.
30nF
– 100nF
200k Battery-Current Monitor
VS = 5V, 0V
10nF with Over-the-Top Operation
IS = 2µA + eIN/150k
ZEROS AT 50Hz AND 60Hz 100k The bidirectional current sensor shown in Figure 98 takes
advantage of the extended common mode range of the
80.6k 10k LT1495 to sense currents into and out of a 12V battery
15nF 15nF
100nF
while operating from a 5V supply. During the charge cycle,
+ op amp A1 controls the current in Q1 so that the voltage
169k
169k 169k 100nF
1/2 LT1495 OUTPUT drop across RA is equal to IL • RSENSE. This voltage is then
30nF – amplified at the charge output by the ratio of RA to RB.
200k During this cycle, amplifier A2 sees a negative offset,
10nF
which keeps Q2 off and the discharge output low. During
the discharge cycle, A2 and Q2 are active and operation is
100k similar to that during the charge cycle.
LT1495/96 •TA03
Conclusion
Figure 96. 6th Order 10Hz Elliptic Lowpass Filter
6th Order, 10Hz Elliptic Lowpass Filter The LT1495/LT1496 extends Linear Technology’s range
of rail-to-rail amplifier solutions to a truly micropower
Figure 96 shows a 6th order, 10Hz elliptic lowpass filter level. The combination of extremely low current and
with zeros at 50Hz and 60Hz. Supply current is primarily precision specifications provides designers with a versa-
determined by the DC load on the amplifiers and is tile solution for battery-operated devices and other low
approximately 2µA + VO/150k (9µA for VO = 1V). The power systems.
overall frequency response is shown in Figure 97. The
notch depth of the zeros at 50Hz and 60Hz is nearly 60dB
and the stopband attenuation is greater than 40dB out to IL RSENSE
CHARGE 0.1Ω
0
DISCHARGE 12V
5V
–10
– RA RA
–20
–
A2 A1
GAIN (dB)
1/2 LT1495 RA RA 1/2 LT1495

+
–30
+
–40 Q2 Q1
2N3904 2N3904 1495_08.eps
–50 DISCHARGE CHARGE

OUT OUT R 
VO = IL  B  R SENSE
RB RB  RA 
–60
0 10 100 1000 FOR R A = 1k
FREQUENCY (Hz) R B = 10k
1495_07.eps VO 1V
=
Figure 97. Frequency Response of Figure IL A
96’s 6th Order Elliptic Lowpass Filter Figure 98. Battery-Current Monitor
AN87-63
Application Note 87
SEND CAMERA POWER AND VIDEO thus corrupting the signal. The circuit shown in Figure 99
ON THE SAME COAX CABLE takes a different approach to the problem by using all
by Frank Cox active components.
Because remotely located video surveillance cameras do The circuitry at the monitor end of the coax cable supplies
not always have a ready source of power, it is convenient all the power to the system. U1, an LT1206 current
to run both the power and the video signal through a single feedback amplifier, forms a gyrator or synthetic inductor.
coax cable. One way to do this is to use an inductor to The gyrator isolates the low impedance power supply from
present a high impedance to the video and a low imped- the cable by maintaining a reasonably high impedance
ance to the DC. The difficulty with this method is that the over the video bandwidth while, at the same time, contrib-
frequency spectrum of a monochrome video signal ex- uting only 0.1Ω of series resistance. This op amp needs to
tends down to at least 30Hz. The composite color video have enough bandwidth for video and sufficient output
spectrum goes even lower, with components at 15Hz. drive to supply 120mA to the camera. The selected part has
This implies a rather large inductor. For example, a 0.4H a guaranteed output current of 250mA and a 3dB band-
inductor has an impedance of only 75Ω at 30Hz, which is width of 60MHz, making it a good fit. Because the video
about the minimum necessary. Large inductors have a needs to be capacitively coupled, there is no need for split
large series resistance that wastes power. More impor- supplies; hence a single 24V supply is used. The 24V
tantly, large inductors can have a significant amount of supply also gives some headroom for the voltage drop in
parasitic capacitance and stand a good chance of going long cable runs.
into self resonance below the 4MHz video bandwidth and
C2
4.7µF C3 C5 C6 Q1
0.1µF ZETEX ZTX749 100' RG58/U
TANT 1000µF U3 1000µF 20V DC
+ + OUT LT1086CT-12 IN + R4 R5 R6
2k 10k 75Ω
+ C7
R1
12V C1 10k 1000µF
20µF
3 C4
+
CAMERA + 7 1000µF R3
VIDEO 1k
+
R2 U4 6
OUT
10k LT1363
2
– 4
562Ω
24V 24V
24V
C10 R12 0.1µF

+ 4.7µF 1000µF 10k
0.1µF 3 C13
+
TANT R7 7 R17
2.32k
+ 100µF
C9 U2 6 75Ω TO
R9 20µF FILM LT1363 MONITOR
+
510k R13 2
10k – 4 R14
562Ω
R8 +
11.5k 4.7µF 24V R10
0.1Ω
2 4 R16
+
U1 7 R15 280Ω
LT1206CT 280Ω C11
1 5
– 6
51pF
3 NC
+ C12
1000µF
R11, 100Ω
DI_VID_01.eps
Figure 99. Circuit Transmits Video and 12V Power on the Same Coax Cable
AN87-64
Application Note 87
The camera end has an LT1086 fixed 12V regulator (U3) to the LT1206 is set to 20V to give headroom between the
supply 12V to a black and white CCD video camera. U4, an supply and the video.
LT1363 op amp, supplies the drive for Q1, a fast, high
current transistor. Q1, in turn, modulates the video on the U2, another LT1363 video-speed op amp, receives video
20V DC. The collector of Q1 is the input to the 12V from the cable, supplies some frequency equalization and
regulator. This point is AC ground because it is well drives the cable to the monitor. Equalization is used to
bypassed as required by U3. U1 is set up to deliver 20V to compensate for high frequency roll off in the camera cable.
the cable. Because the 12V regulator in the camera end The components shown (R16, C11) gave acceptable mono-
needs 1.5V of dropout voltage, the balance of 6.5V can be chrome video with 100 feet of RG58/U cable.
dropped in the series resistance of the cable. The output of
200µA, 1.2MHz RAIL-TO-RAIL OP AMPS HAVE LT1491 op amps, with substantial improvements in speed.
OVER-THE-TOP INPUTS The LT1638 is five times faster than the LT1490.
by Raj Ramchandani
Battery Current Monitor
Introduction
The battery-current monitor shown in Figure 100 demon-
The LT1638 is Linear Technology’s latest general-pur- strates the LT1639’s ability to operate with its inputs
pose, low power, dual rail-to-rail operational amplifier; the above the positive rail. In this application, a conventional
LT1639 is a quad version. The circuit topology of the amplifier would be limited to a battery voltage between 5V
LT1638 is based on Linear Technology’s popular LT1490/ and ground, but the LT1639 can handle battery voltages
RS
CHARGER 0.2Ω
VOLTAGE +
1N4001
VBATTERY = 12V
RA
2k QA
+ 2N3904
1/4
RA' LT1639 –
2k A 1/4
– LT1639 LOGIC
C
+
RB
2k QB VSUPPLY = 5V, 0V
+ 2N3904
1/4
RB' LT1639
RL 2k B
–
+
1/4
RG LT1639 VOUT
10k D
–
LOGIC HIGH (5V) = CHARGING
LOGIC LOW (0V) = DISCHARGING
(VOUT)
90.9k
VOUT 10k
IBATTERY =
(RS) (RG/RA ) GAIN
= AMPS
GAIN
NOTE: RA = RB S1 = OPEN, GAIN = 1
S1 S1 = CLOSED, GAIN = 10
Figure 100. LT1639 Battery Current Monitor—an Over-The-Top Application
AN87-65
Application Note 87
as high as 44V. The LT1639 can be shut down by removing through QA or QB is proportional to the current in RS. This
VCC. With VCC removed, the input leakage is less then current flows into RG and is converted into a voltage.
0.1nA. No damage to the LT1639 will result from inserting Amplifier D buffers and amplifies the voltage across RG.
the 12V battery backward. Amplifier C compares the outputs of amplifier A and
amplifier B to determine the polarity of current through RS.
When the battery is charging, amplifier B senses the
The scale factor for VOUT with S1 open is 1V/A. With S1
voltage drop across RS. The output of amplifier B causes
closed the scale factor is 1V/100mA and currents as low
QB to drain sufficient current through RB to balance the
as 5mA can be measured.
inputs of amplifier B. Likewise, amplifier A and QA form a
closed loop when the battery is discharging. The current
LOW DISTORTION RAIL-TO-RAIL OP AMPS HAVE response and can drive low impedance loads, which
0.003% THD WITH 100kHz SIGNAL makes them suitable for high performance applications.
by Danh Tran The following applications demonstrate the versatility of
these amplifiers.
Introduction
The LT1630/LT1632 duals and LT1631/LT1633 quads are 400kHz 4th Order Butterworth Filter for 3V Operation
the newest members of Linear Technology’s family of rail-
to-rail op amps, which provide the best combination of AC The circuit shown in Figure 101 makes use of the low
performance and DC precision over the widest range of voltage operation and the wide bandwidth of the LT1630 to
supply voltages. The LT1630/LT1631 deliver a 30MHz create a 400kHz 4th order lowpass filter with a 3V supply.
gain-bandwidth product, a 10V/µs slew rate and 6nV/√Hz The amplifiers are configured in the inverting mode for the
input-voltage noise. Optimized for higher speed lowest distortion and the output can swing rail-to-rail for
applications, the LT1632/LT1633 have a 45MHz gain- the maximum dynamic range. Figure 102 displays the
bandwidth product, a 45V/µs slew rate and 12nV/√Hz frequency response of the filter. Stopband attenuation is
input voltage noise. greater than 85dB at 10MHz. With a 2.25VP-P, 100kHz
input signal, the filter has harmonic distortion products of
Applications less than –87dBc.
The ability to accommodate any input and output signals

that fall within the device’ s supplies makes these amplifi-
10
ers very easy to use. They exhibit a very good transient
0
–10
–20
–30
GAIN (dB)
2.32k 47pF
–40
2.32k 6.65k – 2.74k 22pF 3V
VIN –50
2.74k 5.62k –
220pF 1/2 LT1630 –60
+ 470pF 1/2 LT1630 VOUT –70
+ VS = 3V, 0V
–80
VIN = 2.25VP-P
VS/2 1630/31 TA01 –90
0.1k 1k 10k 100k 1M 10M
FREQUENCY (Hz)
1630/31 TA02
Figure 102. Frequency Response of Filter

Figure 101. Single-Supply, 400kHz, 4th Order Butterworth Filter in Figure 101
AN87-66
Application Note 87
40dB Gain, 550kHz Instrumentation Amplifier Common mode range can be calculated by the equations
shown with Figure 103. For example, the common mode
An instrumentation amplifier with a rail-to-rail output range is from 0.15V to 2.65V if the output voltage is at one-
swing, operating from a 3V supply, can be constructed half of the 3V supply. The common mode rejection is
with the LT1632, as shown in Figure 103. The amplifier has greater than 110dB at 100Hz when trimmed with resistor
a nominal gain of 100, which can be adjusted with resistor R1. Figure 103 shows the amplifier’s cutoff frequency of
R5. The DC output level is equal to the input voltage (VIN) 550kHz.
between the two inputs multiplied by the gain of 100.
R5 450Ω
R4 20k
50
40
R2 2k DIFFERENTIAL
30
INPUT
3V 20
R1 20k
–
VOLTAGE GAIN (dB)

10 VS = 3V
R3 2k – AV = 100
1.5V ± 1/2
LT1632
0
–10
–IN
+ 1/2
LT1632 OUT –20 COMMON MODE
+IN
+ –30
INPUT
–40
–50
LOWER LIMIT COMMON MODE INPUT VOLTAGE –60
VCML =
( (
VOUT(DC) R2
AV R5
+ 0.1V
1.0
1.1
AV =
R4
R3 ( 1+
R2
R1
+
R3 + R2
R5 ( = 100 –70
100 1k 10k 100k
FREQUENCY (Hz)
1M 10M
1562 TA09
UPPER LIMIT COMMON MODE INPUT VOLTAGE BW = 550kHz
VCMH =
( (
VOUT(DC) R2
AV R5
+ 2.85V
1.0
1.1
VOUT(DC) = (+IN – (–IN))DC × GAIN Figure 104. Frequency Response of
Figure 103’s Instrumentation Amplifier
Figure 103. Single-Supply Instrumentation Amplifier
THE LT1167: PRECISION, LOW COST, LOW POWER Applications

INSTRUMENTATION AMPLIFIER REQUIRES A SINGLE
GAIN-SET RESISTOR Single-Supply Pressure Monitor
by Alexander Strong
The LT1167’s low supply current, low supply voltage
Introduction operation and low input bias current (350pA max) allow it
to fit nicely into battery powered applications. Low overall
The LT1167 is the next-generation instrumentation ampli- power dissipation necessitates using higher impedance
fier designed to replace the previous generation of mono- bridges. Figure 105 shows the LT1167 connected to a 3kΩ
lithic instrumentation amps, as well as discrete, multiple bridge’s differential output. The picoampere input bias
op amp solutions. Instrumentation amplifiers differ from currents will still keep the error caused by offset current to
operational amplifiers in that they can amplify input sig- a negligible level. The LT1112 level shifts the LT1167’s
nals that are not ground referenced. The output of an reference pin and the ADC’s analog ground pins above
instrumentation amplifier is referenced to an external ground. This is necessary in single-supply applications
voltage that is independent of the input. Conversely, the because the output cannot swing to ground. The LT1167’s
output voltage of an op amp, due to the nature of its and LT1112’s combined power dissipation is still less than
feedback, is referenced to the differential and common the bridge’s. This circuit’s total supply current is just 3mA.
mode input voltage.
AN87-67
Application Note 87
5V
3k 3k 20k
REF DIGITAL
G = 100 3 7 DATA
3k 3k 499Ω + 10k LTC1286 SERIAL
8
6 OUTPUT
+IN
1 LT1167
2 5
– +
4
–IN
20k 1/2 LT1112
1167_02.eps
Figure 105. Single-Supply Pressure Monitor
ADC Signal Conditioning
The LT1167 is shown in Figure 106 changing a differential 0

SUPPLY VOLTAGE = ±5V
signal into a single-ended signal. The single-ended signal –20 fIN = 5.5kHz
is then filtered with a passive 1st order RC lowpass filter fSAMPLE = 400ksps
SINAD = 70.6dB
and applied to the LTC1400 12-bit analog-to-digital con- AMPLITUDE (dB)
–40 LT1167 GAIN = 10
verter (ADC). The LT1167’s output stage can easily drive
–60
the ADC’s small nominal input capacitance, preserving
signal integrity. Figure 107 shows two FFTs of the ampli- –80
fier/ADC’s output. Figures 107a and 107b show the results
of operating the LT1167 at unity gain and a gain of ten, –100
respectively. This results in a typical SINAD of 70.6dB. –120

0 25 50 75 100 125 150 175 200
FREQUENCY (kHz)
5V (A) 1167 CC .eps
10µF 10µF
R1 = ∞ 0
+
+
AV = 1 CX = 0.047µF
SUPPLY VOLTAGE = ±5V
AV = 10 R1 = 5.6kΩ CX = 0.033µF
fIN = 3kHz
–20
fSAMPLE = 400ksps
+5V 0.1µF 0.1µF SINAD = 70.6dB
0.1µF –40 LT1167 GAIN = 1
AMPLITUDE (dB)
3 1 –60
3 7 VREF VCC
+ DOUT 5 –80
1 1k 2
R1 LT1167 AIN LTC1400 CLK 6 SERIAL
8 INTERFACE
5 CONV 7 –100
– CX
4 GND VSS
2
4 8 –120
0 25 50 75 100 125 150 175 200
0.1µF 10µF FREQUENCY (kHz) 1167 BB .eps
0.1µF
–5V
+ (B)
–5V
1167 AA .eps Figure 107. Operating at a Gain of One (A) or
Figure 106. The LT1167 Converting Differential Signals to Single- Ten (B), Figure 106’s Circuit Achieves
Ended Signals; the LT1167 is Ideal for Driving the LTC1400 12-Bit Operation with a SINAD of 70.6dB
AN87-68
Application Note 87
Current Source +VS
VIN+
3 7
RG + R1
8
Figure 108 shows a simple, accurate, low power program- 6 +
VX
–
1 LT1167
mable current source. The differential voltage across pins 2 5
2 and 3 is mirrored across RG. The voltage across RG is VIN– –
4
IL
amplified and applied across R1, defining the output –
– VS
current. The 50µA bias current flowing from pin 5 is
LT1464
buffered by the LT1464 JFET operational amplifier, which
[( ) ( )]
+
increases the resolution of the current source to 3pA. VX V IN+ − V IN− G
IL= =
R1 R1
G = 49.4k Ω + 1
LOAD
Nerve-Impulse Amplifier RG
1167_04.eps
The LT1167’s low current noise makes it ideal for ECG Figure 108. Precision Current Source
monitors that have MΩ source impedances. Demonstrat-
ing the LT1167’s ability to amplify low level signals, the
circuit in Figure 109 takes advantage of the amplifier’s The ability to operate at ±3V on 0.9mA of supply current
high gain and low noise operation. This circuit amplifies makes the LT1167 ideal for battery-powered applications.
the low level nerve impulse signals received from a patient Total supply current for this application is 1.7mA. Proper
at pins 2 and 3 of the LT1167. RG and the parallel safeguards, such as isolation, must be added to this circuit
combination of R3 and R4 set a gain of ten. The potential to protect the patient from possible harm.
on LT1112’s pin 1 creates a ground for the common mode
signal. The LT1167’s high CMRR of 110db ensures that Conclusion
the desired differential signal is amplified and unwanted
common mode signals are attenuated. Since the DC The LT1167 instrumentation amplifier delivers the best
portion of the signal is not important, R6 and C2 make up precision, lowest noise, highest fault tolerance, plus the
a 0.3Hz highpass filter. The AC signal at LT1112’s pin 5 is ease of use provided by single-resistor gain setting. The
amplified by a gain of 101 set by R7/R8 + 1. The parallel LT1167 is offered in 8-pin PDIP and SO packages. The SO
combination of C3 and R7 forms a lowpass filter that uses significantly less board space than discrete designs.
decreases this gain at frequencies above 1kHz.
PATIENT/CIRCUIT 3V
PROTECTION/ISOLATION
+INPUT 0.3Hz HIGHPASS

C1
R1 R3, 30k
3 7
RG, 6k + C2, 0.47µF 3V
8
LT1167 6 5 8
R4, 30k 1 G = 10
+
R2, 1M 2 5 + 7
R6 OUTPUT
– 1/2 LT1112
1V/mV
4 1M
6
+ – 4
–3V
– 2
R7, 10k
–3V
PATIENT 1
GROUND 1/2 LT1112 R8 C3, 15nF
+ 3 100
1167_05.eps
–INPUT
AV = 101
POLE AT 1kHz
Figure 109. Medical ECG Monitor
AN87-69
Application Note 87
LEVEL SHIFT ALLOWS CFA VIDEO AMPLIFIER TO diodes will turn off. The load will be disconnected from the
SWING TO GROUND ON A SINGLE SUPPLY CFA output and connected through the feedback resistor
by Frank Cox to the network of R6 and R7. This causes about 150mVDC
to appear at the output, instead of the 0V that should be
A current feedback (CFA) video amplifier can be made to there.
run off a single supply and still amplify ground-referenced
video with the addition of a simple and inexpensive level The ground-referenced video signal at the input needs to
shifter. The circuit in Figure 110 is an amplifier and cable be level shifted into the input common mode range of the
driver for a current output video DAC. The video can be LT1227 (3V above negative supply). R4 and R5 shift the
composite or component but it must have sync. The single input signal to 3V. In the process, the input video is
positive supply is 12V but could be as low as 6V for the attenuated by a factor of 2.5. For correct gain, no offset and
LT1227. with a zero source impedance, R4 would be 1.5k. To
compensate for the presence of R3, R4 is made 1.5k
The output of the LT1227 CFA used here can swing to minus R3, or 1.46k. The trade off is a gain error of about
within 2.5V of the negative supply with a 150Ω load over 1.5%. If R4 is left 1.5k, the gain is correct, but there is an
the commercial temperature range of 0°C to 70°C. Five offset error of 75mV. R6, R7 and R8 set the gain and the
diodes in the feedback loop are used, in conjunction with output offset of the amplifier. A noninverting gain of five is
C5, to level shift the output to ground. The video from the taken to compensate for the attenuation in the input level
output of the LT1227 charges C5 and the voltage across it shifter and the cable termination.
allows the output to swing to ground or even slightly
negative. However, the level of this negative swing will The voltage offset on the output of this circuit is a rather
depend on the video signal and so will be unpredictable. sensitive function of the value of the input resistors. For
When the scene is black, there must be sync on the video instance, an error of 1% in the value of R6 will cause an
for C5 to remain charged. A zero-level component video offset of 30mV (1% of 3V) on the output. This is in addition
signal with no sync will not work with this circuit. The CFA to the offset error introduced by the op amp. Precision
output will try to go to zero, or as low as it can, and the resistor networks are available (BI Technologies,
12V
5V
75Ω VIDEO SOURCE C3 47µF
USED FOR TESTING
+
SOURCE
C1 C2
R1 75Ω 10µF + 4.7µF
R5 C5 4.7µF
R6 C4
*R2 1k FILM FILM
499Ω 0.1µF
77.37Ω
B +
R9 75Ω LOAD
*R4 LT1227
1.46k
– 5× 1N4148 R10
75Ω
R8 1.5k A
*R3 R7
38.1Ω 1.5k
*RESISTORS ARE A COMBINATION OF TWO 1% VALUES,

R2 IS A SERIES COMBINATION OF 75Ω AND 2.37Ω
R3 IS A PARALLEL COMBINATION OF 75Ω AND 77.3Ω
R4 IS A SERIES COMBINATION OF 1.3k + 160Ω = 1.46k
ALL RESISTORS ARE 1% METAL FILM
Figure 110. Amplifier and Cable Driver for Current-Output Video DAC
AN87-70
Application Note 87
714-447-2345) with matching specifications of 0.1% or function. The LTC201A analog switch and C1 store the
better. These could be used for the level shifting resistors, offset error during blanking. The clamp pulse should be
although this would make adjustments like the one made 3µs or wider and should occur during blanking. It can
to R4 difficult. conveniently be made by delaying the sync pulse with one
shots. If the sync tip is clamped, the clamp pulse must
Fortunately, there is always synchronization information start after and end before the sync pulse or offset errors
associated with video. A simple circuit can be used to DC will be introduced. The integrator made with the LT1632
restore voltage offsets produced by resistor mismatch, op adjusts the voltage at point B (see Figure 110) to correct
amp offset or DC errors in the input video. Figure 111 the offset.
shows the additional circuitry needed to perform this
12V
5V
13
R1
1/2 LTC201A C2 6800pF
10k
FILM
3, 14 2, 15 R3 10k
C1
12V C3
R2 10µF
10k FILM 0.1µF
TO FIGURE 110, –
POINT A R7 10k
1/2 LT1632 TO FIGURE 110,
5V
+ POINT B
1, 16 4, 5 R4
VIDEO 1.40k
R5
HOLD 50k
5V
C4 0.1µF
DC RESTORE LEVEL
0V
(ADJUST FOR DESIRED
SAMPLE R6 BLANKING LEVEL)
CLAMP PULSE 20k
Figure 111. DC Restore Subcircuit
LT1468: AN OPERATIONAL AMPLIFIER FOR FAST, 16-Bit DAC Current-to-Voltage Converter

16-BIT SYSTEMS with 1.7µs Settling Time
by George Feliz
The key AC specification of the circuit of Figure 112 is
Introduction settling time as it limits the DAC update rate. The settling
time measurement is an exceptionally difficult problem
The LT1468 is a single operational amplifier that has been that has been ably addressed by Jim Williams, in Linear
optimized for accuracy and speed in 16-bit systems. Technology Application Note 74. Minimizing settling time
Operating from ±15V supplies, the LT1468 in a gain of is limited by the need to null the DAC output capacitance,
–1 configuration will settle in 900ns to 150µV for a 10V which varies from 70pF to 115pF, depending on code. This
step. The LT1468 also features the excellent DC capacitance at the amplifier input combines with the
specifications required for 16-bit designs. Input offset feedback resistor to form a zero in the closed-loop fre-
voltage is 75µV max, input bias current is 10nA maximum quency response in the vicinity of 200kHz–400kHz. With-
for the inverting input and 40nA maximum for the nonin- out a feedback capacitor, the circuit will oscillate. The
verting input and DC gain is 1V/µV minimum. choice of 20pF stabilizes the circuit by adding a pole at
AN87-71
Application Note 87
10V
VREF 20pF 15V

16 6k
DAC – OPTIONAL NOISE FILTER
INPUTS 2k
LTC1597 LT1468 VOUT
DAC COUT
70pF–115pF + 50pF
–15V
1LSB = 25.4nA 153µV
FULL SCALE = 1.67mA 10V
Figure 112. 16-Bit DAC I/V Converter with 1.7µs Settling Time
1.3MHz to limit the frequency peaking and is chosen to to-noise ratio (SNR) of 90dB implies 56µVRMS noise at the
optimize settling time. The settling time to 16-bit accuracy input. The noise for the amplifier, 100Ω/3000pF filter and
is theoretically bounded by 11.1 time constants set by the a high value 10kΩ source is 15µVRMS, which degrades the
6kΩ and 20pF. Figure 112’s circuit settles in 1.7µs to SNR by only 0.3dB. The LTC1604 total harmonic distor-
150µV for a 10V step. This compares favorably with the tion (THD) is a low –94dB at 100kHz. The buffer/filter
1.33µs theoretical limit and is the best result obtainable combination alone has 2nd and 3rd harmonic distortion
with a wide variety of LTC and competitive amplifiers. This better than –100dB for a 5VP-P, 100kHz input, so it does
excellent settling requires the amplifier to be free of not degrade the AC performance of the ADC.
thermal tails in its settling behavior.
The buffer also drives the ADC from a low source imped-
The LTC1597 current output DAC is specified with a 10V ance. Without a buffer, the LTC1604 acquisition time
reference input. The LSB is 25.4nA, which becomes 153µV increases with increasing source resistance above 1k and
after conversion by the LT1468, and the full-scale output therefore the maximum sampling rate must be reduced.
is 1.67mA, which corresponds to 10V at the amplifier With the low noise, low distortion LT1468 buffer, the ADC
output. The zero-scale offset contribution of the LT1468 is can be driven at maximum speed from higher source
the input offset voltage and the inverting input current resistances without sacrificing AC performance.
flowing through the 6k feedback resistor. This worst-case
total of 135µV is less than one LSB. At full-scale there is an The DC requirements for the ADC buffer are relatively
insignificant additional 10µV of error due to the 1V/µV modest. The input offset voltage, CMRR (96dB minimum)
minimum gain of the amplifier. The low input offset of the and noninverting input bias current through the source
amplifier ensures negligible degradation of the DAC’s resistance, RS, affect the DC accuracy, but these errors are
outstanding linearity specifications. an insignificant fraction of the ADC offset and full-scale
errors.
With its low 5nV/√Hz input voltage noise and 0.6pA/√Hz
input current noise, the LT1468 contributes only an addi- 5V
tional 23% to the DAC output noise voltage. As with any 15V
RS
precision application, and particularly with wide band- VIN +
100Ω 16
width amplifiers, the noise bandwidth should be mini- LT1468 LTC1604
ADC
OUTPUTS
mized with an external filter to maximize resolution. –
3000pF
–15V
ADC Buffer –5V
530kHz NOISE FILTER
The important amplifier specifications for an analog-to-

digital converter buffer application (Figure 113) are low
noise and low distortion. The LTC1604 16-bit ADC signal- Figure 113. ADC Buffer
AN87-72
Application Note 87
Telecommunications Circuits Not Your Standard Bench Supply
HOW TO RING A PHONE WITH A QUAD OP AMP Ring-tone generation requires two high voltages, 60VDC
by Dale Eagar and –180VDC. Figure 114 details the switching power
supply that delivers the volts needed to run the ring-tone
Requirements circuit. This switcher can be powered from any voltage
from 5V to 30V, and is shut down when not in use,
When your telephone rings, exactly what is the phone conserving power. The transformer and optocoupling
company doing? This question comes up frequently, as it yield a fully floating output. Faraday shields in the trans-
seems everyone is becoming a telephone company. former eliminate most switcher noise, preventing mystery
Deregulation opens many new opportunities, but if you system noise problems later. Table 6 is the build diagram
want to be the phone company you must ring bells. The of the transformer used in the switching power supply.
voltage requirement for ringing a telephone bell is a
87VRMS 20Hz sine wave superimposed on –48VDC. Quad Op Amp Rings Phones
An Open-Architecture Ring-Tone Generator When a phone rings, it rings with a cadence, a sequence
of rings and pauses. The standard cadence is one second
What the module makers offer is a solution to a problem ringing followed by two seconds of silence. We use the
that, by its nature, calls for unusual design techniques. first 1/4 of the LT1491 as a cadence oscillator (developed
What we offer here is a design that you can own, tailor to in Figures 115 and 116) whose output is at VCC for one
your specific needs, lay out on your circuit board and put second and then at VEE for two seconds (see Figure 120).
on your bill of materials. Finally, you will be in control of the V+
black magic (and high voltages) of ring-tone generation. R1 R2
F
+
LT1491
60V –
MUR160
T1 R3
2
= PRIMARY GROUND = SECONDARY GROUND
70T #34 0.47µF C1
7
F V–
5V TO 30V
+ 5 1
5 220µF
20T #26 200T #34 0.47µF
VIN NOTE: F REPRESENTS A FLOATING GROUND,
4 4 8 NOT EQUAL TO OR
SW –180V
LT1070 3A 6 3
MUR160
60V 60V
10k 1
2 1 FREQ
FB VC V+
180V
0.01 GND
3
5 4N28 2 V–
2k
2
R1 = R
10k 4 1 3 2
RING 2N3904 330Ω
1
FREQ =
R3 C1
10k 0.1µF
DUTY FACTOR = 50%
DI_RING_01.eps
DI_RING_02.eps
Figure 114. The Switching Power Supply Figure 115. Op Amp Intentionally Oscillates
AN87-73
Application Note 87
V+ V+
R1 R2 100K 150K
47k 10k
F +
F +
R4 LT1491
LT1491
33k
–
– R3 HIGH = OSCILLATE
1.6M 500K
C1
1µF 0.1µF
F
V–
V–
V+
1 SEC 2 SEC
V+ GATE
V–
V+
V–
OUT
1 V–
FREQ =
Hz 1
3 S
DUTY FACTOR = 33.3% 20
OUTPUT STARTS HIGH ON POWERUP. DUTY FACTOR = 50%
DI_RING_03.eps
Figure 116. Duty Factor is Skewed Figure 117. Gated 20Hz Oscillator
DI_RING_04.eps
This sequence repeats every three seconds, producing the Square Wave Plus Filter Equals Sine Wave
all-too-familiar pattern.
Thevenin will tell you that the output impedance of the
The actual ringing of the bell is performed by a 20Hz AC sequencer shown in Figure 118 is 120kΩ. This impedance
sine wave signal at a level of 87VRMS, superimposed on can be recycled and used as the input resistance of the filter
–48VDC. The 20Hz signal is implemented with the second that follows. The filter detailed in Figure 119 uses the
amplifier in the LT1491 (Figure 117) which acts as a gated Thevenin resistor on its input, yielding a slick, compact
20Hz oscillator. Connecting the circuit shown in Figure design while distorting the nice waveform on the node
116 to the circuit shown in Figure 117 and adding three labeled “square out” to a half sine wave, half square wave.
resistors yields the sequencer as shown in Figure 118. The
waveform, labled “Square Out,” is the fourth trace in Appending the filter to the waveform sequencer creates
Figure 120. This waveform is the output of Figure 121. the waveform engine detailed in Figure 119. The output of
this waveform engine is shown in the bottom trace in
10k 300k
100K 150k
+ + 300k SQUARE
LT1491 LT1491 WAVE
47k 33k
OUT
– –
1.6M
F CR1 1N4148 500k 620k
1µF 0.1µF
20Hz
CADENCE
F
V–
V–
DI_RING_05.eps
Figure 118. Sequencer: Cadenced 20Hz Oscillator
AN87-74
Application Note 87
C4
0.047µF Table 6. Ring-Tone High Voltage Transformer Build Diagram
Materials
– 2 EFD 20–15–3F8 Cores

RTHEVEVIN R11 LT1491 SINE
120k 10k OUT 1 EFD 20–15–8P Bobbin
+
OUTPUT 2 EFD 20– Clip
IMPEDANCE OF
C3
FIGURE 118
0.068µF 2 0.007" Nomex Tape for Gap
F Start Pin 1 200T #34
Figure 119. Filter to Remove the Sharp Edges

DI_RING_06.eps Winding 1 Term Pin 8
Figure 120. This waveform engine is shown in block form 1 Wrap 0.002" Mylar Tape
in Figure 122. Start Pin 2 70T #34
Winding 2 Term Pin 7

Mapping Out the Ring-Tone Generator in Block Form
1 Wrap 0.002" Mylar Tape
We now build a system-level block diagram of our ring Connect Pin 3 1T Foil Tape Faraday Shield
tone generator. We start with the waveform engine of
1 Wrap 0.002" Mylar Tape
Figure 122, add a couple of 15V regulators and a DC offset Shields
(47k resistor), then apply some voltage gain with a high Connect Pin 6 1T Foil Tape Faraday Shield
voltage amplifier to ring the bell. This hypothetical sys- 1 Wrap 0.002" Mylar Tape
tem-level block diagram is detailed in Figure 123. Figure
Start Pin 4 20T #26
124 shows the output waveform of the ring tone genera-
tor; the sequenced ringing starts when the high voltage Winding 3 Term Pin 5
supply (Figure 114) is turned on, and continues as long as Finish with Mylar Tape
the power supply is enabled.
NEXT
RING
1 SEC 2 SEC What’s Wrong with This Picture (Figure 123)
ON
POWER
OFF Careful scrutiny of Figure 123 reveals an inconsistency:
even though the three fourths of the LT1491 in the
V+
waveform engine block are powered by ±15V, the final
CADENCE
amplifier is shown as powered from 60V and –180V; this
V–
poses two problems: first the LT1491 is a quad op amp
V+
and all four sections have to share the same supply pins,
20Hz and second, the LT1491 will not meet specification when
V– powered from 60V and –180V. This is because 240V is
greater than the absolute maximum rating of 44V (V+ to
2 +
5 V V-). Linear Technology products are noted for their
SQUARE
OUT robustness and conservative “specmanship,” but this is
2 –
5
V going too far. It is time to apply some tricks of the trade.
2 +
5 V
SINE
OUT
2 –
V
5
DI_RING_07.eps
Figure 120. Timing of Waveform Engine
AN87-75
Application Note 87
0.068µF
10k 620k
100K 10k
F
– GATED
+ + LT1491 SINE WAVE
300k 150k OUTPUT
LT1491 LT1491 +
47k 33k
– –
F 1N4148 0.47µF
1.6M 16k 620k
0.47µF F
1µF
F
DI_RING_08.eps
V–
Figure 121. Waveform synthesizer
Building High Voltage Amplifiers amplifier, because they can both take the voltage and
dissipate the power required to provide the ring voltage
Setting aside the waveform engine for a moment, we will and current. By connecting the op amp to the regulators,
develop a high voltage amplifier. We start with the ±15V one gets a free cascode high voltage amplifier. This is
regulators shown in Figure 123; these are not your run-of- because the supply current for the op amp is also the
the-mill regulators, these are high differential voltage regulator current. The trouble one encounters when so
regulators, constructed as shown in Figure 125. Using doing is that the input common mode range of the op amp
these regulators and the final section of the LT1491 quad is not wide enough to accommodate the full output voltage
op amp, we can build a high voltage amplifier. We will use range of the composite amplifier. This would not be a
the ±15V regulators as the “output transistors” of our problem if the amplifier were used as a unity-gain nonin-
15V verting amplifier, but in this system we need gain to get
20Hz from our 12VP-P to 87VRMS.
V+ 6V
SINE SINE ON
OUT OUT POWER
WAVEFORM OFF
ENGINE VREF
REF 3 SEC
V– 42V
F –6V SINE –48V
OUT
–15V –138V
DI_RING_09.eps
DI_RING_11.eps
Figure 122. Waveform Engine Figure 124. System Output

60V
15V 47k +VIN REF REF –15V
15V REG
0.01µF
OUT IN
COM
100k 620Ω
V+ F 10k 150k
SINE
OUT IRF620
WAVEFORM 2N3906
ENGINE 15V
15V
REF – IRF9620
V– 2N3904
HV
F
+ RL 620Ω 100k
–15V REG
–15V F F
OUT IN
COM
REF REF +15V –VIN
F –180V DI_RING_10.eps
DI_RING_12.eps
Figure 123. High Voltage Amplifier Figure 125. High Differential Voltage Regulators
AN87-76
Application Note 87
RFF RFB RL RFF RFB
RFB
X AV = –
RFF
– V+ X + –
IN IN
+ RL
+ AV = –
RFB –
RFF
V– Y Y
Y Y
DI_RING_13.eps
X X X DI_RING_15.eps
Figure 126. Standard Op Amp Form Figure 128. Trade Inputs and Outputs
RFF RFB RFF RFB
RFB RL
AV = –
RFF
– + V+
+ Y
IN IN
– RL
+ – V–
X X X X DI_RING_14.eps
RFB
AV = –
DI_RING_16.eps
RFF
Figure 127. Hide the Batteries Inside the Op Amp Figure 129. Pull the Batteries Back out of the Amplifier
Moving the amplifier’s output transistor function out of the Darwinistic mood, we might see that the power supplies
op amp and into the ±15V regulators moves the effective (batteries) are in fact an integral part of our amplifier. Such
amplifier output from the op amp output to the center of an observation would lead us to redraw the circuit to look
the two supplies sourcing the ±15V regulators. This is a like Figure 127 where the center of the two batteries are
transformative step in the evolution of amplifiers from low brought out of the amplifier as the negative terminal of the
voltage op amps to high voltage, extended supply output.
amplifiers.
Once that is done, one is free to swap the polarities of the
Inverting Op Amp Circuit Gets Morphed inputs and outputs, yielding the circuit shown in Figure
128. Finally we pull the two batteries back out of the
Let’s focus on this transformative step as it relates to the amplifier to get our morphed inverting amplifier (Figure
simple inverting amplifier shown in Figure 126.* Were we 129). Isn’t assisting evolution fun?†
to look at the amplifier in Figure 126 in some strange
150k
0.01µF
15V REG 60V
15V
OUT IN
COM
V+ 10k
SINE
OUT
+ C6
WAVEFORM R18 R21
ENGINE LT1491
REF – RL
V–
47k
F
F
180V
–15V
OUT COM IN
–15V REG DI_RING_17.eps
Figure 130. Post-Evolution Block Diagram
AN87-77
Application Note 87
60V
R2
R16
47k
100k
R3 R5 Q1
10k 100k R6
IRF628 Q3
10k C3
C2 Z1 2N3904
0.047µF
0.47µF
5
+ R9 R11 15V 100k
3 D1 U1B 7 300k 10k 10
+ 1N4148 LT1491
+ R17
U1A 1 6 U1C 8
R1 – 4 620
LT1491 LT1491 13
33k 2 R7 9 –
– 16k C4 – U1D 14 R18
0.068µF LT1491 100
12
+
C1 R4 R8 R12 R14 C7
11 R23 R26
1µF 1.6M 620k R10 SMOOTHING FILTER 10k 47µF
10k 4.7k 2k
620k
+
R24
CADENCE OSCILLATOR 20Hz OSCILLATOR 430Ω *OPTO1
C5 R13 R15 R25
0.01µF 130k 47k 4.7k
Q5
2N3904
LOAD UP TO TEN PHONES
Z2 R19
15V 620
Q4
2N3906
Q2
*LED OF OPTO 1 ILLUMINATES WHEN THE PHONE IS OFF THE HOOK IRF9620 R21
POWER AMPLIFIER 150
R20
–180V 100K C6
0.033µF
DI_RING_18.eps
Figure 131. Ring-Tone Generator
Applying the evolutionary forces just described to the protected on its output from shorts to ground or to either
block diagram in Figure 123, we get the block diagram in the +60V or the –180V supply.
Figure 130. Actually Figure 130 contains three strangers,
R18, R21 and C6, parts not predicted by our evolutionary Conclusion
path (unless R18 = 0Ω and R21 is open) These parts are
needed because, in our metamorphosis going from Figure Here is a ring tone generator you can own, a robust circuit
127 to Figure 128, the amplifier’s internal compensation that is stable into any load. If your system design requires
node was moved from ground to the amplifier’s output. a circuit with different specifications, you can easily tailor
These parts correct the compensation for the new con- this circuit to meet your needs. Don’t hesitate to call us if
figuration. we can help you with your design.
Ring-Trip Sense Editor’s Notes:
* The grounds X and Y, shown in Figures 126–129, are for illustrating the
Now that we can ring the telephone, we must sense when effects of “evolution.” Ground X may be regarded as “arbitrary exemplary
the phone is picked up. This is done by sensing the DC ground,” and ground Y as “postmetamorphic exemplary ground.” Ground X
current flowing to the phone while it is ringing, using the and ground Y are not the same.
ring-trip sense circuit comprising R23–R26, C7, Q5 and † Evolutionary theory invloves pure, random chance. What you have done
Opto1 of Figure 131, the complete ring-tone generator. here requires purposeful thought and design.
This circuit will ring more than ten phones at once, and is
AN87-78
Application Note 87
A LOW DISTORTION, LOW POWER, SINGLE-PAIR Low Distortion Line Driver
HDSL DRIVER USING THE LT1497
by George Feliz and Adolfo Garcia The circuit of Figure 132 transmits signals over a 135Ω
twisted pair through a 1:1 transformer. The LT1497 dual
Introduction 125mA, 50MHz current feedback amplifier was chosen
for its ability to cleanly drive heavy loads, while consum-
High speed digital subscriber line (HDSL) interfaces sup- ing a modest 7mA maximum supply current per amplifier
port full-duplex data rates up to 1.544Mbps over 12,000 in a thermally enhanced SO-8 package. The driver
feet using two standard 135Ω twisted-pair telephone amplifiers are configured in gains of two (A1) and minus
wires. The high data rate is achieved with a combination of one (A2) to compensate for the attenuation inherent in the
encoding 2 bits per symbol using two-binary, one-quater- back-termination of the line and to provide differential
nary (2B1Q) modulation, and sophisticated digital signal drive to the transformer. The transmit power requirement
processing to extract the received signal. This perfor- for HDSL is 13.5dBm (22.4mW) into 135Ω, correspond-
mance is possible only with low distortion line drivers and ing to a 1.74VRMS signal. Since 2B1Q modulation is a 4-
receivers. In addition, the power dissipation of the trans- level pulse amplitude modulated signal, the crest factor
ceiver circuitry is critical because it may be loop-powered (peak to RMS) of this signal is 1.61. Thus, a 13.5dBm,
from the central office over the twisted pair. Lower power 2B1Q modulated signal yields 5.6VP-P across the 135Ω
dissipation also increases the number of transceivers that load. The corresponding output signal current is ±20.7mA
can placed in a single, non-forced–air enclosure. Single- peak. This modest drive level increases for varying line
pair HDSL requires the same performance as two-pair conditions and is tested with a standardized collection of
HDSL over a single twisted pair and operates at twice the test loops that can have line impedances as low as 25Ω.
fundamental 2B1Q symbol rate. In HDSL systems that use The LT1497’s high output current and voltage swing drive
2B1Q line coding, the signal passband necessary to carry the 135Ω line at the required distortion level of –72dBc.
a data rate of 1.544Mbps is 392kHz. This signal rate will be For a data rate of 1.544Mbps and 2-bit-per-symbol
used to quantify the performance of the LT1497 in this encoding, the fundamental frequency of operation is
article. 392kHz.
560Ω
5V
560Ω
–
A1 68.1Ω
1/2 LT1497
VIN +
1.1*
+
560Ω VOUT
135Ω
5.6VP-P
560Ω
–
– *MIDCOM 671-7807
A2 68.1Ω (800) 643-2661
1/2 LT1497
+
DI 1497 01.eps
–5V
Figure 132. LT1497 HDSL Driver
AN87-79
Application Note 87
0 0
AMPLITUDE (dBm)
AMPLITUDE (dBm)
–50 –50
2HD 3IMD 3IMD
–100 –100
100 200 300 400 500 600 700 800 900 1000 1100 100 200 300 400 500 600
DI 1497 02
FREQUENCY (kHz) FREQUENCY (Hz) DI 1497 03
Figure 133. Harmonic Distortion of Figure 132’s Circuit with a Figure 134. 2-Tone Intermodulation for Figure 132’s Circuit
400kHz Sine Wave and an Output Level of 5.6VP-P into 135Ω
The LT1497 provides such low distortion because it oper- With multicarrier applications such as discrete multitone
ates at only a fraction of its output current capability and modulation (DMT) becoming as prevalent as single-car-
is well within its voltage swing limitations. There are other rier applications, another important measure of amplifier
LTC amplifiers that can achieve this performance, but at dynamic performance is 2-tone intermodulation. This
the expense of higher power dissipation or a larger package. evaluation is a valuable tool to gain insight to amplifier
linearity when processing more than one tone at a time.
Performance
For this test, two sine waves at 300kHz and 400kHz were
The circuit of Figure 132 was evaluated for harmonic used with levels set to obtain 5.6VP-P across the 135Ω
distortion with a 400kHz sine wave and an output level of load. Figure 134 shows that the third-order intermodula-
5.6VP-P into 135Ω. Figure 133 shows that the second tion products are well below –72dB. With a 50Ω load,
harmonic is –72.3dB relative to the fundamental for the performance is within 1dB–2dB of that with the 135Ω
135Ω load. Third harmonic distortion is not critical, because load.
received signals are heavily filtered before being digitized
by an A/D converter. Performance with a 50Ω load (to Conclusion
simulate more challenging test loops) is slightly better at
–75dB. The output signal was attenuated to obtain maxi- The circuit presented provides outstanding distortion per-
mum sensitivity of the HP4195A network analyzer used for formance in an SO-8 package with remarkably low power
the measurements. dissipation. It is ideally suited for single pair digital sub-
scriber line applications, especially for remote terminals.
Comparators
ULTRALOW POWER COMPARATORS

INCLUDE REFERENCE
Undervoltage/ Overvoltage Detector
by James Herr
The LTC1440–LTC1445 family features 1µA comparators The LTC1442 can be easily configured as a window
with adjustable hysteresis and TTL/CMOS outputs that detector, as shown in Figure 135. R1, R2 and R3 form a
sink and source current and a 1µA reference that can drive resistive divider from VCC so that comparator A goes low
a bypass capacitor of up to 0.01µF without oscillation. The when VCC drops below 4.5V, and comparator B goes low
parts operate from a 2V to 11V single supply or a ±1V to when VCC rises above 5.5V. A 10mV hysteresis band is set
±5V dual supply. by R4 and R5 to prevent oscillations near the trip points.
AN87-80
Application Note 87
VCC
operation. Comparators A and B, along with R1, R2 and
R1 7 R3, monitor the battery voltage. When the battery voltage
1.33M V+
1% 3 IN+ A UNDERVOLTAGE drops below 2.65V comparator A’s output pulls low to
+ (4.5V)
OUT A 1 generate a nonmaskable interrupt to the microprocessor
to warn of a low-battery condition. To protect the battery
–
R2
POWER
from over discharge, the output of comparator B is pulled
84.5k
1% GOOD high by R7 when the battery voltage falls below 2.45V. P-
+ channel MOSFET Q1 and the LT1300 are turned off,
OUT B 8
4 IN – B
dropping the quiescent current to 20µA. Q1 is needed to
– OVERVOLTAGE prevent the load circuitry from discharging the battery
R3 5 HYST (5.5V)
392k
1% 6 REF through L1 and D1.
R4 R5
2.4M 10k LTC1442
5% 5%
V– Comparators C and D provide the reset input to the
C1
0.01µF
2 microprocessor. As soon as the boost converter output
rises above the 4.65V threshold set by R8 and R9, com-
Figure 135. Window Detector parator C turns off and R10 starts to charge C4. After
200ms, comparator D turns off and the Reset pin is pulled
Single-Cell Lithium-Ion Battery Supply high by R12.
Figure 136 shows a single cell lithium-ion battery to 5V Conclusion

supply with the low-battery warning, low-battery shut-
down and reset functions provided by the LTC1444. The With their built-in references, low supply current require-
LT1300 micropower step-up DC/DC converter boosts the ments and variety of configurations, Linear Technology’s
battery voltage to 5V using L1 and D1. Capacitors C2 and LTC1440–45 family of micropower comparators is ideal
C3 provide input and output filtering. for system monitoring in battery-powered devices such as
PDAs, laptop and palmtop computers and hand-held
The voltage-monitoring circuitry takes advantage of the instruments.
LTC1444’s open-drain outputs and low supply voltage
R1 L1
1.1M 3 10µH D1
5% 5 SUMIDA 1N5817
+ V+ CD54-100
A 2
1/4 LTC1444
R2 4
82.5k – + C2
1% R7 100µF
51k 6 7
5% VIN SW
1 CELL
6 – 4
SENSE
LITHIUM- B 1 3 1
ION R3 1/4 LTC1444 SHDN
BATTERY 1M 7 + HYST LT1300
3 2, 4
1% 14 5 Q1 R8 R10 R11
NC ILIM 732k 3.37M
2 MMFT2955ETI 51k
+ 1% 11 5% VCC
NC SEL 5%
R5 C3 + NMI
51k PWR GND GND 100µF R9 C 16 13 R12
5% 267k 1/4 LTC1444 + 51k µP
8 1 1% 10 D 15 5%
R4 R6 8 REF – 1/4 LTC1444 RESET
2.4M 430Ω 12
5% 5%
LTC1444 –
+ C1
REF
C4
1µF 9 V– 0.22µF
C2, C3: AUX TPSD107M010R0100 OR

SANYO OS-CON 16SA100M
Figure 136. Single-Cell to 5V Supply
AN87-81
Application Note 87
A 4.5ns, 4mA, SINGLE-SUPPLY, DUAL COMPARATOR VCC
2.7V–6V
OPTIMIZED FOR 3V/5V OPERATION
by Joseph G. Petrofsky 2k 1MHz–10MHz
CRYSTAL (AT-CUT)
Introduction 220Ω
620Ω
GROUND
The LT1720 is an UltraFast™ (4.5ns), low power (4mA/ + CASE
OUTPUT
comparator), single-supply, dual comparator designed to 1/2 LT1720
operate on a single 3V or 5V supply. These comparators –

feature internal hysteresis, making them easy to use, even
2k
with slowly moving input signals. The LT1720 is fabri-
cated in Linear Technology’s 6GHz complementary bipo-
0.1µF 1.8k
lar process, resulting in unprecedented speed for its low
power consumption.
Applications Figure 137. Simple 1MHz to 10MHz Crystal Oscillator
Crystal Oscillators
Figure 137 shows a simple crystal oscillator using one half and temperature. Crosstalk between the comparators,
of an LT1720. The 2k–620Ω resistor pair set a bias point usually a disadvantage in monolithic duals, has minimal
at the comparator’s noninverting input. The 2k–1.8k– effect on the LT1720 timing due to the internal hysteresis.
0.1µF path sets the inverting input node at an appropriate
DC average level based on the output. The crystal’s path The circuits of Figure 138 show basic building blocks for
provides resonant positive feedback and stable oscillation differential timing skews. The 2.5k resistance interacts
occurs. Although the LT1720 will give the correct logic with the 2pF typical input capacitance to create at least
output when one input is outside the common mode ±4ns delay, controlled by the potentiometer setting. A
range, additional delays may occur when it is so operated, differential and a single-ended version are shown. In the
opening the possibility of spurious operating modes. differential configuration, the output edges can be smoothly
Therefore, the DC bias voltages at the inputs are set near scrolled through ∆t = 0 with negligible interaction.
the center of the LT1720’s common mode range and the
220Ω resistor attenuates the feedback to the noninverting Fast Waveform Sampler
input. The circuit will operate with any AT-cut crystal from
1MHz to 10MHz over a 2.7V to 6V supply range. Figure 139 uses a diode-bridge-type switch for clean, fast
waveform sampling. The diode bridge, because of its
The output duty cycle for the circuit of Figure 137 is inherent symmetry, provides lower AC errors than other
roughly 50% but it is affected by resistor tolerances and, semiconductor-based switching technologies. This cir-
to a lesser extent, by comparator offsets and timings. cuit features 20dB of gain, 10MHz full power bandwidth
and 100µV/°C baseline uncertainty. Switching delay is less
Timing Skews than 15ns and the minimum sampling window width for
full power response is 30ns.
For a number of reasons, the LT1720 is an excellent choice
for applications requiring differential timing skew. The two The input waveform is presented to the diode bridge
comparators in a single package are inherently well switch, the output of which feeds the LT1227 wideband
matched, with just 300ps ∆tPD typical. Monolithic con- amplifier. The LT1720 comparators, triggered by the sample
struction keeps the delays well matched vs supply voltage command, generate phase-opposed outputs. These sig-
AN87-82
Application Note 87
LT1720 LT1720
CIN CIN
+ INPUT +
– 2.5k –
CIN CIN
INPUT 2.5k DIFFERENTIAL ±4ns 0ns–4ns SINGLE-

RELATIVE SKEW ENDED DELAY
CIN – CIN –
+ +
CIN CIN
VREF VREF
Figure 138. Timing-Skew Generation is Easy with the LT1720
nals are level shifted by the transistors, providing comple- the other two Schottkys provide for fast turn-off. A logic
mentary bipolar drive to switch the bridge. A skew com- AND gate could instead be used, but would add consider-
pensation trim ensures bridge-drive signal simultaneity ably more delay than the 300psec contributed by this
within 1ns. The AC balance corrects for parasitic capaci- discrete stage.
tive bridge imbalances. A DC balance adjustment trims
bridge offset. This circuit can detect coincident pulses as narrow as
2.5ns. For narrower pulses, the output will degrade grace-
The trim sequence involves grounding the input via 50Ω fully, responding, but with narrow pulses that don’t rise all
and applying a 100kHz sample command. The DC balance the way to high before starting to fall. The decision delay
is adjusted for minimal bridge ON vs OFF variation at the is 4.5ns with input signals 50mV or more above the
output. The skew compensation and AC balance adjust- reference level. This circuit creates a TTL compatible
ments are then optimized for minimum AC disturbance in output but it can typically drive CMOS as well.
the output. Finally, unground the input and the circuit is
ready for use. Pulse Stretcher
Coincidence Detector For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 141 acts as
High speed comparators are especially suited for interfac- a one-shot, stretching the width of an incoming pulse to a
ing pulse-output transducers, such as particle detectors, consistent 100ns. Unlike a logic one-shot, this LT1720-
to logic circuitry. The matched delays of a monolithic dual based circuit requires only 100pV-s of stimulus to trigger.
are well suited for those cases where the coincidence of
two pulses needs to be detected. The circuit of Figure 140 The circuit works as follows: Comparator C1 functions as
is a coincidence detector that uses an LT1720 and discrete a threshold detector, whereas comparator C2 is configured
components as a fast AND gate. as a one-shot. The first comparator is prebiased with a
threshold of 8mV to overcome comparator and system
The reference level is set to 1V, an arbitrary threshold. Only offsets and establish a low output in the absence of an
when both input signals exceed this will a coincidence be input signal. An input pulse sends the output of C1 high,
detected. The Schottky diodes from the comparator out- which in turn latches C2’s output high. The output of C2 is
puts to the base of the MRF-501 form the AND gate, while fed back to the input of the first comparator, causing
AN87-83
Application Note 87
5V
2.2k 2.2k
INPUT
±100mV FULL SCALE +
OUTPUT
LT1227 ±1V FULL-
1k
SCALE
–
909Ω
100Ω
= 1N5711
= CA3039 DIODE ARRAY AC BALANCE

(SUBSTRATE TO –5V) 2.5k
3pF
5V
1.5k 3.6k
1.1k 1.1k
0.1µF
+
CIN 1/2 LT1720
– 1.1k
SKEW
SAMPLE 2k COMP
1.1k
COMMAND
2.5k
10pF +
1/2 LT1720
2k – MRF501
MRF501
CIN
DC BALANCE
500Ω
11 8 680Ω
LM3045 820Ω
820Ω 9 6
10 13 7
51Ω 51Ω
–5V
Figure 139. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation
regeneration and latching both outputs high. Timing latching both outputs low. A new pulse at the input of C1
capacitor C now begins charging through R and, at the end can now restart the process. Timing capacitor C can be
of 100ns, C2 resets low. The output of C1 also goes low, increased without limit for longer output pulses.
AN87-84
Application Note 87
This circuit has an ultimate sensitivity of better than 14mV Conclusion
with 5ns–10ns input pulses. It can even detect an ava-
lanche generated test pulse of just 1ns duration with The new LT1720 dual 4.5ns single-supply comparators
sensitivity better than 100mV.1 It can detect short events feature high speeds and low power consumption. They are
better than the coincidence detector above because the versatile and easy-to-use building blocks for a wide vari-
one-shot is configured to catch just 100mV of upward ety of system design challenges.
movement from C1’s VOL, whereas the coincidence
detector’s 2.5ns specification is based on a full, legitimate 1 See Linear Technology Application Note 47, Appendix B. This circuit can
logic high. detect the output of the pulse generator described after 40dB of attenuation.
5V 5V
300Ω
+
MRF501
1/2 LT1720 (GROUND
51Ω
CASE LEAD)
3.9k
–
5V OUTPUT
1k
–
0.1µF
1/2 LT1720
+
4× 1N5711 300Ω
51Ω
COINCIDENCE COMPARATORS 300ps AND GATE
Figure 140. A 2.5ns Coincidence Detector
5V
15k 0.01µF
– OUTPUT
C1
PULSE SOURCE
1/2 LT1720
+ 100ns
50Ω
51Ω 24Ω
R 1k
6.8k
C
100pF
1N5711 –
C2
1/2 LT1720
+
2k 2k
2k
Figure 141. A 1ns Pulse Stretcher
AN87-85
Application Note 87
Instrumentation Circuits
A = 50mV/DIV
B = 5V/DIV
LTC1441-BASED MICROPOWER
C = 5V/DIV
VOLTAGE-TO-FREQUENCY CONVERTER
D = 1mA/DIV
by Jim Williams
E = 5V/DIV
Figure 142 is a voltage-to-frequency converter. A 0V–5V
input produces a 0Hz–10kHz output, with a linearity of HORIZ = 20µs/DIV
0.02%. Gain drift is 60ppm/°C. Maximum current con- Figure 143. Waveforms for the Micropower V/F Converter:
sumption is only 26µA, 100 times lower than currently Charge-Based Feedback Provides Precision Operation with
available units. Extremely Low Power Consumption.
To understand the circuit’s operation, assume that C1’s vides a path to ground. The voltage to which the 100pF unit
negative input is slightly below its positive input (C2’s charges is a function of Q1’s emitter potential and Q6’s
output is low). The input voltage causes a positive-going drop. C1’s CMOS output, purely ohmic, contributes no
ramp at C1’s input (trace A, Figure 143). C1’s output is voltage error. When the ramp at C1’s negative input goes
high, allowing current flow from Q1’s emitter, through high enough, C1’s output goes low (trace B) and the
C1’s output stage to the 100pF capacitor. The 2.2µF inverter switches high (trace C). This action pulls current
capacitor provides high frequency bypass, maintaining from C1’s negative input capacitor via the Q5 route (trace
low impedance at Q1’s emitter. Diode connected Q6 pro- D). This current removal resets C1’s negative input ramp
+V = 6.2 → 12V
LM334
10kHz 6.04k*
TRIM
+
2.2µF Q8
1.2M* 200k Q1
INPUT
0–5V
–
C1 LT1004
0.01 1/2 LTC1441 1.2V
+ x3 0.47µF
50pF
Q2
100k
Q3
100Hz TRIM
3M TYP
15k Q4
Q5 Q7
100pF†
74C14
OUTPUT
= HP5082-2810
Q6 10M
= 1N4148 2.7M
0.1
Q1, Q2, Q8 = 2N5089
ALL OTHER = 2N2222 –
† C2
= POLYSTYRENE
* = 1% METAL FILM 1/2 LTC1441
GROUND ALL UNUSED 74C14 INPUTS +
DIVF_01.eps
Figure 142. 0.02% V/F Converter Requires only 26µA Supply Current
AN87-86
Application Note 87
35
modulate the voltage drop in the Q2–Q4 trio. This
30 correction’s sign and magnitude directly oppose the
CURRENT CONSUMPTION (µA)
25 –120ppm/°C 100pF polystyrene capacitor’s drift, aiding

overall circuit stability. Q8’s isolated drive to the CMOS
20
SLOPE = 1.1µA/kHz inverter prevents output loading from influencing Q1’s
15 operating point. This makes circuit accuracy independent
10 of loading.
5
The Q1 emitter-follower delivers charge to the 100pF
0
0 1 2 3 4 5 6 7 8 9 10 11 12
capacitor efficiently. Both base and collector current end
FREQUENCY (kHz) up in the capacitor. The 100pF capacitor, as small as
DIVF_03.eps accuracy permits, draws only small transient currents
Figure 144. Current Consumption vs Frequency for the during its charge and discharge cycles. The 50pF–100k
V/F Converter: Charge/Discharge Cycles Account for
1.1µA/kHz Current Drain Increase positive feedback combination draws insignificantly small
switching currents. Figure 144, a plot of supply current
versus operating frequency, reflects the low power de-
to a potential slightly below ground. The 50pF capacitor sign. At zero frequency, comparator quiescent current and
furnishes AC positive feedback (C1’s positive input is trace the 12µA reference stack bias account for all current drain.
E) ensuring that C1’s output remains negative long enough There are no other paths for loss. As frequency scales up,
for a complete discharge of the 100pF capacitor. The the 100pF capacitor’s charge-discharge cycle introduces
Schottky diode prevents C1’s input from being driven the 1.1µA/kHz increase shown. A smaller value capacitor
outside its negative common mode limit. When the 50pF would cut power, but effects of stray capacitance and
unit’s feedback decays, C1 again switches high and the charge imbalance would introduce accuracy errors.
entire cycle repeats. The oscillation frequency depends
directly on the input-voltage-derived current. Circuit start-up or overdrive can cause the circuit’s AC-
coupled feedback to latch. If this occurs, C1’s output goes
Q1’s emitter voltage must be carefully controlled to get low; C2, detecting this via the 2.7M–0.1µF lag, goes high.
low drift. Q3 and Q4 temperature compensate Q5 and Q6 This lifts C1’s positive input and grounds the negative
while Q2 compensates Q1’s VBE. The three LT1004s are input with Q7, initiating normal circuit action.
the actual voltage reference and the LM334 current source
provides 12µA bias to the stack. The current drive provides To calibrate this circuit, apply 50mV and select the indi-
excellent supply immunity (better than 40ppm/V) and also cated resistor at C1’s positive input for a 100Hz output.
aids circuit temperature coefficient. It does this by using Complete the calibration by applying 5V and trimming the
the LM334’s 0.3%/°C tempco to slightly temperature input potentiometer for a 10kHz output.
BRIDGE MEASURES SMALL CAPACITANCE

capacitance. This required a circuit with high stability,
IN PRESENCE OF LARGE STRAYS
sensitivity and noise rejection, but one insensitive to stray
by Jeff Witt
capacitance caused by cables and shielding. I also wanted
Capacitance sensors measure a wide variety of physical battery operation and analog output for easy interfacing to
quantities, such as position, acceleration, pressure and other instruments. Two traditional circuit types have
fluid level. The capacitance changes are often much smaller drawbacks: integrators are sensitive to noise at the com-
than stray capacitances, especially if the sensor is re- parator and voltage-to-frequency converters typically mea-
motely placed. I needed to make measurements with a sure stray as well as sensor capacitance. The capacitance
50pF cryogenic fluid level detector, with only 2pF full-scale bridge presented here measures small transducer capaci-
change, hooked to several hundred pF of varying cable tance changes, yet rejects noise and cable capacitance.
AN87-87
Application Note 87
The bridge, shown in Figure 145, is designed around the The circuit operates from a single 5V supply and con-
LTC1043 switched-capacitor building block. The circuit sumes 800µA. If the capacitances at nodes A and C are
compares a capacitor, CX, of unknown value, with a kept below 500pF, the LT1078 micropower dual op amp
reference capacitor, CREF. The LTC1043, programmed may be used in place of the LT1413, reducing supply
with C1 to switch at 500Hz, applies a square wave of current to just 160µA.
amplitude VREF to node A, and a square wave of amplitude
VOUT and opposite phase to node B. When the bridge is If the relative capacitance change is small, the circuit can
balanced, the AC voltage at node C is zero, and be modified for higher resolution, as shown in Figure 146.
A JFET input op amp (LT1462) amplifies the signal before
demodulation for good noise performance, and the output
VOUT = VREF CX
CREF of the integrator is attenuated by R1 and R2 to increase the
sensitivity of the circuit. If ∆CX << CX, and CREF ≈ CX, then
Balance is achieved by integrating the current from node
C using an op amp (LT1413) and a third switch on the VOUT – VREF ≈ VREF ∆CX (R1 + R2)
CREF R2
LTC1043 for synchronous detection. With CREF = 500pF
and VREF = 2.5V, this circuit has a gain of 5mV/pF, and With CREF = 50pF, the circuit has a gain of 5V/pF and can
when measured with a DMM achieves a resolution of 10fF resolve 2fF. Supply current is 1mA. The synchronous
for a dynamic range of 100dB. It also rejects stray capaci- detection makes this circuit insensitive to external noise
tance (shown as ghosts in Figure 145) by 100dB. If this sources and in this respect shielding is not terribly impor-
rejection is not important, the switching frequency f can tant. However, to achieve high resolution and stability,
be increased to extend the circuit’s bandwidth, which is care should be taken to shield the capacitors being mea-
sured. I used this circuit for the fluid level detector men-
CREF tioned above, putting a small trim cap in parallel with CREF
BW = f to adjust offset and trimming R2 for proper gain.
COUT
COUT should be larger than CREF.
5V 1/2 LTC1043
5V
4 16
V+ COSC
C1
100k 6 0.01µF COUT
+ 17
V– 2.2nF
1/2 7 7
VREF LT1413
5 11 A
– 1/4 LTC1043
8 5V
CX
5 2 8
1µF LT1004-2.5 +
2 1/2 1
C VOUT
LT1413
6 3
– 4
13 CREF
12 B
14 VREF
NOTE: SHADED PARTS REPRESENT

PARASITIC CAPACITANCES
Figure 145. A Simple, High Performance Capacitance Bridge
AN87-88
Application Note 87
Bridge circuits are particularly suitable for differential CMRR for the circuit in Figure 146 exceeds 70dB. In this
measurements. When CX and CREF are replaced with two case, however, the output is linear only for small relative
sensing capacitors, these circuits measure differential capacitance changes.
capacitance changes, but reject common mode changes.
VIN 1/2 LTC1043

5V
4 16 3
V+ COSC + 10k 10k
1/2 1
0.01µF
100k 6 LT1462
+ 17 10M 2
V–
1/2 7 7
– 5V
LT1413 1/4 LTC1043
VREF
5 11
VREF 6 – 8
– 10k 1/2 7
8 5
LT1462
CX 2 5 +
100Ω
1µF LT1004-2.5 4
VREF 6
VREF
1µF
13 CREF
R2 12
100Ω 1% 5V
14
R1 8 – 2 100K
10.0k 1% 1 1/2
LT1413
+ 3
VREF
4
VOUT
Figure 146. A Bridge with Increased Sensitivity and Noise Performance
WATER TANK PRESSURE SENSING, This is because the very long wires required to intercon-
A FLUID SOLUTION nect the system cause IR drops, noise and other corrup-
by Richard Markell tion of the analog signal. The solution to this problem is to
implement a system that converts the analog to digital
Introduction signals at the sensor. In this application, we implement a
“liquid height to frequency converter.”
Liquid sensors require a media compatible, solid state
pressure sensor. The pressure range of the sensor is Circuit Description
dependent on the height of the column or tank of fluid that
must be sensed. This article describes the use of the E G Figure 147 shows the analog front-end of the system,
& G IC Sensors Model 90 stainless steel diaphragm, 0 to which includes the LT1121 linear regulator for powering
15psig sensor used to sense water height in a tank or the system. The LT1121 is a micropower, low dropout
column. linear regulator with shutdown. For micropower
applications of this or other circuits, the ability to shut
Because large chemical or water tanks are typically located down the entire system via a single power supply pin
outside in “tank farms,” it is insufficient to provide only an allows the system to operate only when taking data (perhaps
analog interface to a digitization system for level sensing. every hour), conserving power and improving battery life.
AN87-89
Application Note 87
TO FIGURE 148
(9V)
R21
5 R15 100k R18
8 1 9V
+
12V IN OUT 100k 249k
U1B 7
U3 R2 R3 LT1079
LT1121 C3 6
C1 18k 0.1µF 35.7k – R14
5 2 12 4 R6 100k
0.1µF SHDN OUT C2 +
1µF 14 823Ω
GND R1 R5 U1D
LT1034
3 13k 4.99k LT1079 3 6 R13
-1.2 13
– 3.32k
11 1 PRESSURE 5 2
–
10k SENSOR 10k
R4 U2A 1
POT MODEL 90 POT
4.99k LT1490
2 7 3
GND + VO
5k R8
INSIDE SENSOR IN MODEL 93 3.01k
REPLACES R13 AND 10k POT
MODEL 90/MODEL 93 R16

2 100k R19
E G & G IC SENSORS (408) 432-1800 – 249k
U1A 1
LT1079
3 R17
+ 100k R20
100k
DI_WT_01.eps
Figure 147. Pressure-Sensor Amplifier
FROM LT1121 (FIGURE 147) +9V
LM334
10kHz 6.04k*
INPUT TRIM +
2.2µF Q8
FROM 1.2M* 200k Q1
PRESSURE –
SENSOR C1
AMPLIFER 0.01µF LT1004
1/2 LTC1441 1.2V
(FIG 147)
+ x3 0.47µF
50pF
Q2
100k
Q3
100Hz TRIM
3M TYP
15k Q4
Q5 Q7
†
100pF 0.1
74C14
= HP5082-2810
OR 1N5711
Q6 10M
= 1N4148 2.7M 4 14 1
PRE VCC CLR
0.1µF 3 5 390k
Q1, Q2, Q8 = 2N5089 CLK Q
ALL OTHER = 2N2222 – 74C74
† C2 100k
= POLYSTYRENE 2 6
* = 1% METAL FILM 1/2 LTC1441 D Q
GROUND ALL UNUSED 74C14 AND 74C74 INPUTS PINS +
7
DI_WT_02.eps
Figure 148. This 0.02% V/F Converter Requires only 26µA Supply Current
AN87-90
Application Note 87
5.0
4.5
4.0
3.5
3.0
VOLTS
2.5
2.0
1.5
1.0
0.5
0
0 2 4 6 8 10 12 14 16
FEET
DI_WT_03.eps
Figure 149. Output Voltage vs Column Height
In Figure 147, U3, the LT1121, converts 12V to 9V to

power the system. The 12V may be obtained from a wall
cube or batteries.
The LT1034, a 1.2V reference, is used with U1D, 1/4 of an

LT1079 quad low power op amp, to provide a 1.5mA
current source to the pressure sensor. The reference
voltage is also divided down by R5, R8, R4 and the 10k
potentiometer and used to offset the output amplifier,
U2A, so that the signals are not too close to the supply Figure 150. Test Setup for Water-Column Sensor
rails. The voltage-to-frequency converter shown in Figure 148
has very low power consumption (26µA), 0.02% linearity,
Op amps U1A and U1B (each 1/4 of an LT1079) amplify the 60ppm/˚C drift and 40ppm/V power supply rejection.
bridge pressure sensor’s output and provide a differential
signal to U2A (an LT1490). Note that U2A must be a rail- In operation, C1 switches a charge pump, comprising Q5,
to-rail op amp. The system’s analog output is taken from Q6 and the 100pF capacitor, to maintain its negative input
U2A’s output. at 0V. The LT1004s and associated components form a
temperature-compensated reference for the charge pump.
Figure 149 plots the output voltage for the sensor system’s
6000
analog front end versus the height of the water column that
impinges on the pressure transducer. Note that the pres- 5000
sure change is independent of diameter of the water
4000
FREQUENCY (Hz)
column, so that a tank of liquid would produce the same

resulting output voltage. Figure 150 is a photograph of our 3000
test setup. SENSOR #2
2000
The remainder of the circuitry, shown in Figure 148, allows 1000

transmission of analog data over long distances. The SENSOR #1
circuit was designed by Jim Williams. The circuit takes a 0

0 2 4 6 8 10 12 14 16
DC input from 0V to 5V and converts it to a frequency. For FEET
the pressure circuit in Figure 147, this translates to Figure 151. Output Frequency vs Column DI_WT_05.eps
approximately 0Hz to 5kHz. Height for Two Model 90 Sensors
AN87-91
Application Note 87
The 100pF capacitor charges to a fixed voltage; hence, the Conclusion
repetition rate is the circuit’s only degree of freedom to
maintain feedback. Comparator C1 pumps uniform pack- A cost effective system is shown here consisting of a fluid
ets of charge to its negative input at a repetition rate pressure sensor, IC Sensors Model 90. This sensor’s
precisely proportional to the input-voltage-derived cur- output is fed to signal processing electronics that convert
rent. This action ensures that circuit output frequency is the low level DC output of the bridge-based pressure
determined strictly and solely by the input voltage. sensor to a frequency in the audio range depending on the
height of the fluid column impinging on the pressure
Figure 151 shows the output frequency versus column transducer.
height for two different Model 90 transducers. Note the
straight lines, which are representative of excellent linearity.
0.05µV/˚C CHOPPED AMPLIFIER REQUIRES a gain of 1000, presenting its output to a switched
ONLY 5µA SUPPLY CURRENT demodulator similar to the aforementioned modulator.
by Jim Williams
The demodulator output, a reconstructed, DC-amplified
Figure 152 shows a chopped amplifier that requires only
version of the circuit’s input, is fed to A1B, a DC gain stage.
5.5µA supply current. Offset Voltage is 5µV, with 0.05µV/
A1B’s output is fed back, via gain setting resistors, to the
˚C drift. A gain exceeding 108 affords high accuracy, even
input modulator, closing a feedback loop around the entire
at large closed-loop gains.
amplifier. The configuration’s DC gain is set by the feed-
back resistor’s ratio, in this case 1000.
The micropower comparators (C1A and C1B) form a
biphase 5Hz clock. The clock drives the input-related The circuit’s internal AC coupling prevents A1’s DC char-
switches, causing an amplitude-modulated version of the acteristics from influencing overall DC performance,
DC input to appear at A1A’s input. AC-coupled A1A takes accounting for the extremely low offset uncertainty noted.
IN
CCOMP
0.1µF
1 1/2 CD4016 1/2 CD4016
11
13 5V 12
Ø1 Ø2
2 1µF 10
1M –
+ 1µF
A1A 9 A1B OUT
3
Ø2
5
1M
LT1495
6
Ø1 + LT1495
–
10M 1M
4 8
Ø1 –5V
10M 10k
10M
5V
+
– C1B Ø2
LTC1440
C1A 10k
LTC1440
–
+
10M –5V
0.047µF
10M
Figure 152. 0.05µV/˚C Chopped Amplifier Requires only 5µA Supply Current
AN87-92
Application Note 87
The high open-loop gain permits 10ppm gain accuracy at bandwidth is low. Full-power bandwidth is 0.05Hz with a
a closed-loop gain of 1000. slew rate of about 1V/s. Clock-related noise, about 5µV,
can be reduced by increasing CCOMP, with commensurate
The desired micropower operation and A1’s bandwidth bandwidth reduction.
dictate the 5Hz clock rate. As such, the resultant overall
1000
4.5ns DUAL-COMPARATOR-BASED CRYSTAL
OSCILLATOR HAS 50% DUTY CYCLE AND 800
COMPLEMENTARY OUTPUTS
OUTPUT SKEW (ps)

by Joseph Petrofsky and Jim Williams 600
Figure 153’s circuit uses the LT1720 dual comparator in a 400

50% duty cycle crystal oscillator. Output frequencies of up
to 10MHz are practical. 200
0
The circuit of Figure 153 creates a pair of complementary 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
outputs with a forced 50% duty cycle. Crystals are narrow- AN70 F52
band elements, so the feedback to the noninverting input Figure 154. Output Skew Varies Only
is a filtered analog version of the square wave output. 800ps Over a 2.7V–6V Supply Excursion
Changing the noninverting reference level can therefore
vary the duty cycle. C1 operates as in the previous ex- crystal’s path provides resonant positive feedback, and
ample, where the 2k–600Ω resistor pair sets a bias point stable oscillation occurs. The DC bias voltages at the
at the comparator’s noninverting input. The 2k–1.8k– inputs are set near the center of the LT1720’s common
0.1µF path sets the inverting input at the node at an mode range and the 220Ω resistor attenuates the feedback
appropriate DC-average level based on the output. The to the noninverting input. C2 creates a complementary
2.7V–6V output by comparing the same two nodes with the oppo-
1MHz–10MHz
site input polarity. A1 compares band-limited versions of
2k
CRYSTAL (AT-CUT) the outputs and biases C1’s negative input. C1’s only
degree of freedom to respond is variation of pulse width;
220Ω
620Ω hence, the outputs are forced to 50% duty cycle. The
GROUND
+ CASE
circuit operates from 2.7V to 6V and the skew between the
C1
OUTPUT edges of the of the two outputs is as shown in Figure 154.
1/2 LT1720
– There is a slight duty-cycle dependence on comparator
100k
2k loading, so equal capacitive and resistive loading should
+ be used in critical applications. This circuit works well
1.8k A1 0.1µF
0.1µF LT1636 because of the two matched delays and rail-to-rail–style
– outputs of the LT1720
1k
0.1µF 100k
+
C2
OUTPUT
1/2 LT1720
–
Figure 153. Crystal Oscillator has Complementary Outputs and

50% Duty Cycle. A1’s Feedback Maintains Output Duty Cycle
Despite Supply Variations
AN87-93
Application Note 87
LTC1531 ISOLATED COMPARATOR for 100µs using the power stored on the isolated external
by Wayne Shumaker capacitor. A 4-input, dual-differential comparator samples
at the end of the reference pulse and transmits the result
Introduction back to the nonisolated side. The nonisolated, powered
side latches the result of the comparator and provides a
The LTC1531 is an isolated, self-powered comparator that zero-cross comparator output for triggering a triac.
receives power and communicates through internal isola-
tion capacitors. The internal isolation capacitors provide Applications
3000VRMS of isolation between the comparator and its
output. This allows the part to be used in applications that The LTC1531 can be used to isolate sensors such as in the
require high voltage isolated sensing without the need to isolated thermistor temperature controller in Figure 155.
provide an isolated power source. The isolated side pro- In this circuit, a comparison is made between the voltages
vides a 2.5V pulsed reference output that can deliver 5mA across a thermistor and a resistor that is driven by the 2.5V
AC
120V
R1
LOAD 1N4004 680k
25Ω R2 C1
TECCOR 47k 0.01µF
3k
Q4008L4 ISOLATION
3W
OR EQUIVALENT BARRIER
NEUTRAL + RTHERM =
1µF RO • eB (1/T – 1/TO)
750Ω B = 3807
150Ω VCC SHDN ZCPOS ZCNEG VPW
0.5W 1 TO = 297°K
VREG
1k ZCDATA 2.5V
2N2222 V1 THERM
+ T 30k
100µF V2 YSI 44008
DATA +
Q D V3
–
+ 20µF 390Ω
V4
5.6V VALID R4
DANGER! 50V CMPOUT
LETHAL VOLTAGES 50k
R5* R6
IN THIS SECTION! GND LTC1531 ISOGND
LED 1M 22k
–5.6V
1 1 1
1 = ISOLATED GROUND
*HYSTERESIS = 1°C AT TO
Figure 155. Isolated Thermistor Temperature Controller
ISOLATION
+ 1M
VCC 2.2µF LT1389 1.74M
BARRIER
10M
THERM
10.2k
VCC SHDN ZC + ZC – VPW 30k
VREG – 33k YSI 44008
2.5V
ZCDATA V1
LT1495 1.13k 10.7k
V2 + –
DATA +
VTRIP Q D V3
– K
V4 +
VALID CMPOUT GAIN SET FOR 0°C TO 200°C
GND LTC1531 ISOGND – 1531 TA08
UNUSED
LT1495 OP AMP
COLD JUNCTION COMPENSATES 0°C TO 60°C +
OUTPUT, VTRIP = 1 AT ≥100°C
RESPONSE TIME = 10 sec
RESOLUTION = 4mV ≥ 0.5°C
Figure 156. Overtemperature Detect
AN87-94
Application Note 87
VREG output. As the thermistor resistance rises with The LTC1531 can use the high impedance nature of
temperature, the voltage across the thermistor increases. CMPOUT as a duty-cycle modulator, as in the isolated
When it exceeds the voltage across R4, the comparator voltage sense application in Figure 157. The duty-cycle
output becomes zero and the triac control to the heater is output of the comparator is smoothed with the LT1490
turned off. Hysteresis can be added in the temperature rail-to-rail op amp to reproduce the voltage at VIN. The
control by using CMPOUT and R5. A 10° phase-shifted AC output time constant, R2 • C2, should approximately equal
line signal is supplied through R1, R2 and C1 to the zero- the input time constant, 35 • R1 • C1. The factor of 35
cross comparator for firing the triac. results from CMPOUT being on for only 100µs at an
average sample rate of 300Hz.
In the overtemperature detect application in Figure 156, an
isolated thermocouple is cold junction compensated with Conclusion
the micropower LT1389 reference and the Yellow Springs
thermistor. The micropower LT1495 op amp provides The LTC1531 is a versatile part for sensing signals that
gain to give an overall 0°C–200°C temperature range, require large isolation voltages. The ability of the LTC1531
adjustable by changing the 10M feedback resistor. The to supply power through the isolation barrier simplifies
isolated comparator is connected to compare at 1.25V or applications; it can be combined with other micropower
the center of the temperature range. In this case, VTRIP circuits in a variety of isolated signal conditioning and
goes high when the temperature exceeds 100°C. sensing applications.
VCC ISOLATION
RESOLUTION = 4mV
BARRIER
SETTLING TIME CONSTANT = 10 sec
R2
10M +
+
2.2µF
VCC SHDN ZC ZC – VPW
C2, 1µF VREG
2.5V VIN
ZCDATA V1 0V TO 2.5V
VCC R3 FULL-SCALE
V2
10M INPUT
– DATA +
Q D V3
VOUT –
0V – VCC LT1490 VCC V4
FULL-SCALE VALID
OUTPUT
+ CMPOUT
10k
GND LTC1531 R1 C1
ISOGND
1M 0.22µF
10k 1531 TA05
Figure 157. Isolated Voltage Detect
AN87-95
Application Note 87
Filters Delay-Equalized Elliptic Filter
THE LTC1560-1: A 1MHz/500kHz CONTINUOUS-TIME, Although elliptic filters offer high Q and a sharp transition
LOW NOISE, ELLIPTIC LOWPASS FILTER band, they lack a constant group delay in the passband,
by Nello Sevastopoulos which implies more ringing in the time-domain step
response. In order to minimize the delay ripple in the
Introduction passband of the LTC1560-1, an allpass filter (delay equal-
izer) is cascaded with the LTC1560-1, as shown in Figure
The LTC1560-1 is a high frequency, continuous-time, low 160. Figures 161 and 162 illustrate the eye diagrams
noise filter in an SO-8 package. It is a single-ended input, before and after the equalization, respectively.
single-ended output, 5th order elliptic lowpass filter with
a pin-selectable cutoff frequency (fC) of 1MHz or 500kHz. An eye diagram is a qualitative representation of the time-
domain response of a digital communication system. It
The LTC1560-1 delivers accurate fixed cutoff frequencies shows how susceptible the system is to intersymbol
of 500kHz and 1MHz without the need for internal or interference (ISI). Intersymbol interference is caused by
external clocks. erroneous decisions in the receiver due to pulse overlap-
ping and decaying oscillations of a previous symbol. A
pseudorandom 2-level sequence has been used as the
Applications and Experimental Results input of the LTC1560-1 to generate these eye diagrams.
The larger eye opening in Figure 162 is an indication of the
The LTC1560-1 can be used as part of a more complete equalization effect that leads to reduced ISI. Note that in
frequency-shaping system. Two representative examples Figure 160, the equalizer section has a gain of 2 for driving
follow. and back-terminating 50Ω cable and load. For a simple
unterminated gain-of-1 equalizer, the 40.2k resistor
Highpass-Lowpass Filter changes to 20k and the 49.9Ω resistor is removed from
the circuit. The 22pF capacitors are 1% or 2% dipped silver
As a typical application in communication systems, where mica or COG ceramic.
there is a need to reject DC and some low frequency
signals, a 2nd order RC highpass network can be inserted
in front of the LTC1560-1 to obtain a highpass-lowpass
response. Figures 158 and 159 depict the network and its
measured frequency response, respectively. Notice that
the second resistor in the highpass filter is the input
resistance of the LTC1560-1, which is about 8.1k. 10
0
15V –10
–20
LTC1560-1 0.1µF
–30
GAIN (dB)
1 8 1k 3 7
300pF 300pF + –40
2 7 8 –50
VIN (OR 5V) LT1360 VOUT
3 6 2 –60
8.1k
5V –
4
–5V 4 5 –70
0.1µF 0.01µF –80

1560_06.eps
–90
0.1µF 0.01µF 0.1µF 20 100 1000 10000
FREQUENCY (kHz)
–15V 1560_07.eps
Figure 159. Measured Frequency
Figure 158. A Highpass-Lowpass Filter Response of Figure 158’s Circuit
AN87-96
Application Note 87
Conclusion
The LTC1560-1 is a 5th order elliptic lowpass filter that larger, more expensive and less accurate solutions in
features a 10-bit gain linearity at signal ranges up to 1MHz. communications, data acquisitions, medical instrumen-
Being small and user friendly, the LTC1560-1 is suitable tation and other applications.
for any compact design. It is a monolithic replacement for
20k
22pF
40.2k
9.75k
5V
LTC1560-1 22pF
1 8 6.49k 2 0.1µF
+
1 6.65k 6 8
2 7
VIN (OR 5V) 1/2 LT1364 +
3 7 49.9Ω
3 6
5V – 1/2 LT1364 VOUT
4 5 5
–5V – 1560_08.eps
4
0.1µF 0.01µF
0.1µF
0.1µF 0.01µF
–15V
Figure 160. Augmenting the LTC1560-1 for Improved Delay Flatness
Figure 161. 2-level Eye Diagram of the LTC1560-1 Figure 162. 2-level Eye Diagram of the Equalized Filter
Before Equalization
AN87-97
Application Note 87
THE LTC1067 AND LTC1067-50: UNIVERSAL 4TH Some LTC1067 and LTC1067-50 Applications
ORDER LOW NOISE, RAIL-TO-RAIL SWITCHED
CAPACITOR FILTERS
by Doug La Porte High Dynamic-Range Butterworth Lowpass Filter with
Built-In Track-and-Hold Challenges Discrete Designs
LTC1067 and LTC1067-50 Overview
Figure 163 shows an LTC1067 configured as a 5kHz
The LTC1067 and the LTC1067-50 are universal, 4th order Butterworth lowpass filter. This circuit runs on a 3.3V
switched capacitor filters with rail-to-rail operation. Each power supply and uses an external logic gate to stop the
part contains two identical, high accuracy, very wide clock for track-and-hold operation. The transfer function
dynamic-range 2nd order filter building blocks. Each build- for this circuit, shown in Figure 164, is the classical
ing block, together with three to five resistors, provides Butterworth response. This circuit can be used with either
2nd order filter transfer functions, including lowpass, the LTC1067 or the LTC1067-50. The broad-band noise for
bandpass, highpass, notch and allpass. These parts can be the LTC1067 circuit is 45µVRMS and the DC offset is
used to easily design 4th order or dual 2nd order filters. typically less than 10mV. For the LTC1067-50, the broad-
band noise is 55µVRMS and the DC offset is typically less
Linear Technology’s FilterCAD™ for Windows® filter than 15mV.
design software fully supports designs with these parts.
This circuit has tremendous dynamic range, even on low
The center frequency of each 2nd order section is tuned by supply voltages. Figure 165 shows a plot of the LTC1067’s
an external clock. The LTC1067 has a 100:1 clock-to- signal-to-noise plus total harmonic distortion (SINAD) vs
center frequency ratio. The LTC1067-50’s clock-to-center input signal level for a 1kHz input at three different power
frequency ratio is 50:1. supply voltages. SINAD is limited for small signals by the
noise floor of the LTC1067, for medium signals by the
part’s linearity and for large signals by the output signal
swing. The part’s low noise input stage and excellent
linearity allow the SINAD to exceed 80dB for signals as
small as 700mVP-P, while the rail-to-rail output stage
maintains this level for input signals approaching the
CMOS LOGIC GATE

1 16 500kHz
3.3V V+ CLK 10.000
0.1µF 2 15 TRACK HOLD 0
NC AGND
3 14 –10.00
V+ V– 1µF
–20.00
4 13
SA SB –30.00
GAIN (dB)
R41, 40.2k LTC1067 R42, 76.8k

5 12 –40.00
LPA LPB
R31, 49.9k 6 11 R32, 40.2k –50.00
BPA BPB
R21, 40.2k R22, 76.8k –60.00
7 10
R11 HPA HPB
–70.00
52.3k 8 9
VIN INV A INV B –80.00
VOUT –90.00
RL1, 59k 1k 10k 100k
1067_03.EPS FREQUENCY (Hz)
1067_04.EPS
Figure 164. Transfer Function of the

Figure 163. High Dynamic-Range Butterworth LPF with Track-and-Hold Control LTC1067 5kHz Butterworth LPF
AN87-98
Application Note 87
–50.00 –50.00
VSUPPLY = ±5V
–55.00 –55.00
VSUPPLY = ±5V VSUPPLY = 5V
(NOISE + THD)/SIGNAL (dB)
(NOISE + THD)/SIGNAL (dB)

–60.00 –60.00
VSUPPLY = 5V VSUPPLY = 3.3V
–65.00 –65.00
VSUPPLY = 3.3V
–70.00 –70.00
–75.00 –75.00
–80.00 –80.00
–85.00 –85.00
–90.00 –90.00
–95.00 –95.00
–100.00 –100.00
0.1 1 10 0.1 1 10
INPUT VOLTAGE (Vp-p) INPUT VOLTAGE (VP-P)
1067_05.EPS 1067_06.EPS
Figure 165. Dynamic Range of LTC1067 Butterworth LPF Figure 166. Dynamic Range of LTC1067-50 Butterworth LPF
supply rails. Previous parts could not attain this high –100µV and the droop rate is less than –50µV/ms over the
dynamic range due to higher input noise levels, poor full temperature range. These numbers compare very
linearity and limited output-stage signal swing. The low favorably with dedicated track-and-hold amplifiers. When
noise and rail-to-rail output swing are especially crucial on the clock is restarted, the filter resumes normal operation
the lower 3.3V power supply, where every bit of detectable within ten clock cycles and the output will then correctly
signal range is precious. Figure 166 shows the same plot reflect the input as soon as the filter’s mathematical
for the LTC1067-50 circuit. The dynamic range is not quite response allows.
equal to that of the LTC1067, but is still very good. Recall
that, for the same clock frequency, the LTC1067-50 based Elliptic Lowpass Filter
filter has double the bandwidth and half the supply current
of the LTC1067. The LTC1067 family is capable of much more challenging
filters. Figure 167 shows the schematic for a 25kHz elliptic
The LTC1067 and LTC1067-50 also perform a track-and- lowpass filter using the LT1067-50 operating on a 5V
hold function. Stopping the clock holds the output of the supply. Maximum attenuation one octave from the –3dB
filter at its last value. The LTC1067 is the best performing corner is the design goal for this filter. Figure 168 shows
part in this area. The LTC1067’s hold step is less than the frequency response of the filter with the –3dB cutoff at
1 16
5V V+ CLK 1.25MHz
0.1µF 2 15
NC AGND
1µF
3 + 14
V V–
R61, 48.7k R62, 6.04k
4 13
SA SB
R51 LTC1067-50 R52
4.99k 5 12 4.99k
LPA LPB
R31, 49.9k R32, 21k
6 11
BPA BPB
R21, 20k R22, 24.9k RG, 21k
7 10
R11 HPA HPB
53.6k
VIN 8 9
INV A INV B
RH2, 487k
RH1, 93.1k –
RL1, 25.5k RL2, 20k 1/2 LT1498 VOUT

+
1067_07.EPS
Figure 167. 25kHz Elliptic Lowpass Filter
AN87-99
Application Note 87
10.000
1 16
0 V+ CLK fCLK = 500kHz
2 15
–10.00 NC AGND
3 14 1µF
–20.00 3.3V V+ V–
–30.00 0.1µF 4 LTC1067 13
GAIN (dB)
SA SB
–40.00
5 12 OUT
LPA LPB
–50.00 R32, 200k
R31, 200k 6 11
–60.00 BPA BPB
R21, 10k 7 10 R22, 10k
–70.00 R11 HPA/NA HPB/NB
200k 8 9
–80.00 IN INV A INV B
–90.00
1k 10k 100k 200k R12, 200k
FREQUENCY (Hz) 1067_09.eps
1067_08.EPS
Figure 168. Transfer Function of LTC1067-50 25kHz LPF Figure 169. Low Noise, Low Voltage Narrow BPF
25kHz and –48dB of attenuation at 50kHz. The broad-band To achieve success in designing narrow-band bandpass
noise of the filter is 85µVRMS and the DC offset is less than filters, you must start with precision components. In an LC
15mV typically. or RC design, you would have to start with 0.1% resistors,
1% inductors and 1% capacitors to have any hope of
Although Figure 167 shows the filter powered by a single finishing with a successful, repeatable design in produc-
5V supply, 3.3V or ±5V supply operation is also supported. tion. A competing solution, a digital filter implementation,
The maximum cutoff frequency is 15kHz for the 3.3V also requires precision components. The full input signal
supply and 35kHz for the ±5V supply. The same design and (signal, noise and out-of-band interference) must be cor-
schematic used with an LTC1067 will achieve a somewhat rectly digitized and then processed with a DSP device to
lower noise, lower DC-offset filter. With the LTC1067, the finally determine the tone’s presence. If an out-of-band
broad-band noise is 70µVRMS and the DC offset is typically interfering signal is 20dB greater than the desired tone, the
less than 10mV. The maximum operating frequencies for ADC must have an extra 20dB of dynamic range above the
the LTC1067 are one half of those for the LTC1067-50. signal’s requirement. To pull a small-signal tone from a
large signal interferer, you may need a 16-bit ADC to
digitize the signal just to get 12-bit resolution of the tone
Narrow-Band Bandpass Filter Design after processing. The added cost, power, board space and
Extracts Small Signals Buried in Noise development time make this approach unattractive.
Narrow-band bandpass filters are difficult to design but

are easily achievable with these parts. Most applications
0
for these filters involve extracting a low level signal from
a noisy environment. The noise may be the standard
broad-band, Gaussian-type noise or it may consist of –10
multiple interfering signals. For example, the signal may
GAIN (dB)
be a low level tone or a narrow-bandwidth modulated –20

signal, in a voice-band system. The presence of the tone
must be detected even while the large voice signals are
present. A narrow-band bandpass filter will allow the tone –30
to be separated and detected even in this hostile environ-

ment. Numerous systems also require a narrow bandpass –40
4.0 4.5 5.0 5.5 6.0
filter to be swept across a band looking for the tones. FREQUENCY (kHz)
Switched capacitor filters allow the filter to be swept by 1067_10.eps
simply changing the clock frequency. Figure 170. Frequency Response of Narrow BPF
AN87-100
Application Note 87
A precision switched capacitor filter provides a simple, Narrow-Band Notch Filter Design
small, low power, repeatable, inexpensive solution. The Reaches 80dB Notch Depth
older MF-10-type parts do not have the necessary fO
accuracy to achieve a reliable, repeatable design. Figure Narrow-band notch filters are especially challenging de-
169 shows the schematic of a narrow-band bandpass filter signs. The requirement for most notch filters is to remove
centered at 5kHz. The design uses two identical cascaded a particular tone and not affect any of the remaining signal
sections, each with a Q of 20. Multiply the individual Q of bandwidth. This requires an infinitesimally narrow filter
each section by 1.554 to calculate the total Q of a filter with that can only be approximated by a reasonably narrow
two identical fO, identical Q sections. This filter has a total bandwidth. These types of filters, like the narrow-band
Q of 31. For tunable filter applications, simply lowering the bandpass discussed above, require precision fO accuracy.
clock frequency lowers the center frequency of the filter. Figure 171 shows the schematic of this type of filter. This
Figure 170 shows the frequency response of this filter. The filter is a 1.02kHz notch filter that is often used in telecom-
broad-band noise of this filter is only 90µVRMS. Highly munication test systems.
selective bandpass filters are possible due to the LTC1067’s
excellent fO accuracy. One of the challenges of designing a switched capacitor
notch filter involves the broad-band nature of a notch filter.
Higher Q, narrower bandwidth filters are achievable with The broad-band noise can be aliased down into the band
0.1% resistors or matched resistor networks. An LTC1067 of interest. Optimal high performance notch filters should
mask-programmed part is ideal for these ultranarrow employ some form of noise-band limiting. To accomplish
filters. The well matched, on-chip resistors, coupled with the noise-band limiting, the design in Figure 171 places
specified test conditions, yield a fully functioning filter capacitors in parallel with the R2 resistors of each 2nd
module, in an SO-8 package, without any of the hassles or order section. This forms a pole, set at fP = 1/
cost of procuring precision resistors or resistor networks. (2 • π • R2 • C2), that will limit the bandwidth. This pole
frequency must be low enough to have a band-limiting
1 16 200Ω effect but must not be so low as to affect the notch filter’s
5V V+ CLK fCLK = 125kHz
0.1µF
response. The pole should be greater than thirty times the
2 15
NC AGND notch frequency and less than seventy-five times the
1µF
3 14
notch frequency for the best results. Figure 172 shows the
V+ V–
R61* R62* frequency response of the filter. Note that the notch depth
9.88k LTC1067 10k
4
SA SB
13 is greater than –80dB. Without the use of the C21 and C22,
R51* R52* the notch depth is only about –35dB.
4.99k 5 12 4.99k
LPA LPB
R32 R32
61.9k 6 11 464k 0
BPA BPB
R21 VOUT –10
R22
10k 7 75k
HPA/NA 10 –20
HPB/NB
C21** –30
C22**
300pF
30pF
–40
GAIN (dB)
R11
18.7k 8 9 –50
VIN*** INV A INV B
–60
RH1
–70
40.2k
1067_11.eps
–80
* R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS –90
** C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE
1 –100
(30)(f NOTCH) < < (75)(f NOTCH) WITHOUT 800 900 1000 1100 1200
2π(R2X)(C2X)
C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB FREQUENCY (Hz)
*** VIN ≤ 1.25VP-P LT1067_12.eps
Figure 172. Measured Frequency Response

Figure 171. Narrow-Band Notch Filter of Figure 171’s Narrow-Band Notch Filter
AN87-101
Application Note 87
UNIVERSAL CONTINUOUS-TIME FILTER inches (155 mm2 )—smaller than a U.S. 10-cent coin. This
CHALLENGES DISCRETE DESIGNS filter can also replace op amp–R-C active filter circuits and
by Max Hauser LC filters in applications requiring compactness, flexibil-
ity, high dynamic range or fewer precision components.
The LTC1562 is the first in a new family of tunable, DC-
accurate, continuous-time filter products featuring very
Each of the four 3-terminal Operational Filter™ building
low noise and distortion. It contains four independent 2nd
blocks in an LTC1562 has a virtual ground input, INV, and
order, 3-terminal filter blocks that are resistor program-
two outputs, V1 and V2. These are described in detail in the
mable for lowpass or bandpass functions up to 150kHz,
LTC1562 data sheet.
and has a complete PC board footprint smaller than a
dime. Moreover, the part can deliver arbitrary continuous- Dual 4th Order 100kHz Butterworth Lowpass Filter
time pole-zero responses, including highpass, notch and
elliptic, if one or more programming resistors are replaced The practical circuit in Figure 173 is a dual lowpass filter
with capacitors. The center frequency (f0) of the LTC1562 with a Butterworth (maximally-flat-passband) frequency
is internally trimmed, with an absolute accuracy of 0.5%,
response. Each half gives a DC-accurate, unity-passband-
and can be adjusted independently in each 2nd order
gain lowpass response with rail-to-rail input and output.
section from 10kHz to 150kHz by an external resistor.
With a 10V total power supply, the measured output noise
Other features include:
for one filter is 36µVRMS in a 200kHz bandwidth, and the
large-signal output SNR is 100dB. Measured THD at
❏ Rail-to-rail inputs and outputs 1VRMS input is –83.5dB at 50kHz and –80dB at 100kHz.
❏ Wideband signal-to-noise ratio (SNR) of 103dB Figure 174 shows the frequency response of one filter.
❏ Total harmonic distortion (THD) of –96dB at 20kHz,
–80dB at 100kHz 8th Order 30kHz Chebyshev Highpass Filter
❏ Built-in multiple-input summing and gain features;
capable of 118dB dynamic range Figure 175 shows a straightforward use of the highpass
❏ Single- or dual-supply operation, 4.75V to 10.5V total configuration. Each of the four cascaded 2nd order sections
❏ “Zero-power” shutdown mode under logic control has an external capacitor in the input path. The resistors in
❏ No clocks, PLLs, DSP or tuning cycles required Figure 175 set the f0 and Q values of the four sections to
realize a Chebyshev (equiripple-passband) response with
The LTC1562 provides eight poles of programmable con- 0.05dB ripple and a 30kHz highpass corner. Figure 176
tinuous-time filtering in a total surface mount board area shows the frequency response. Total output noise for this
(including the programming resistors) of 0.24 square circuit is 40µVRMS.
RIN2, 10k
RIN1 10
10k 1 20
VIN2 INV B INV C 0
RQ1, 5.62k 2 19 RQ2, 13k
V1 B V1 C –10
R21, 10k 3 18 R22, 10k
V2 B V2 C –20
5 16 VOUT2
V + LTC1562 V–
GAIN (dB)
5V –5V –30
0.1µF 6 15 0.1µF
SHDN AGND
VOUT1 –40
R23, 10k 8 13
V2 A V2 D
–50
9 12 R24, 10k
RIN3 V1 A V1 D
10k RQ3, 5.62k RQ4, 13k –60
10 11
VIN1 INV A INV D
–70
V– ALSO AT PINS 4, 7, 14 &17
ALL RESISTORS 1% METAL FILM RIN4, 10k –80
10k 100k 1M
FREQUENCY (Hz)
Figure 173. Dual, Matched 4th Order
100kHz Butterworth Lowpass Filter Figure 174. Frequency Response of Figure 173’s Circuit
1562 TA02
AN87-102
Application Note 87
CIN2 24pF
CIN1 TO CIN3
150pF
1 20 RIN2 37.4k
CIN INV B NV C
RQ1, 10.2k RQ2, 22.1k RIN1
2 19
V1 B V1 C CIN2 48.7k 1 20
R21, 35.7k 3 18 R22, 66.5k 150pF VIN INVB INVC
V2 B V2 C RQ1 30.1k 2 19 RQ2 13k
5 – 16 V1B LTC1562 V1C
5V V + LTC1562 V –5V
0.1µF 6 15 0.1µF
R21 31.6k 3 20-PIN SSOP 18 R22 57.6k
AGND V2B V2C
SHDN
8 13 5 16
V2 A V2 D 5V V+ V– – 5V
CIN3 R23, 107k 9 12 R24, 127k CIN4 0.1µF 0.1µF
V1 D 6 15
150pF V1 A 150pF SHDN AGND
RQ3, 54.9k 10 11 RQ4, 98.9k
FROM INV A INV D R23 31.6k 8 13 R24 32.4k
HP C V2A V2D
RQ3 34k 9 12 VOUT
V– ALSO AT PINS 4, 7, 14 &17; ALL RESISTORS 1% METAL FILM VOUT V1A V1D
11 RQ4 11.5k
1562 TA08
10
INVA INVD
Figure 175. 8th Order Chebyshev Highpass RIN4 32.4k
Filter with 0.05dB Ripple (fCUTOFF = 30kHz) RIN3 31.6k
50kHz, 100dB Elliptic Lowpass Filter CIN3 18pF V– ALSO AT PINS 4, 7, 14 &17
ALL RESISTORS 1% METAL FILM CIN4 10pF
Figure 177 illustrates how sharp-cutoff filtering can exploit

Figure 177. 50kHz Elliptic Lowpass Filter
the Operational Filter capabilities of the LTC1562. In this with 100dB Stopband Rejection
design, external capacitors are added and the virtual-
ground inputs of the LTC1562 sum parallel paths to obtain lowpass filters can be built from one LTC1562. The same
three notches in the stopband of a lowpass filter, as plotted technique can add additional real poles to other filter
in Figure 178. This response falls 100dB in a little more configurations as well, for example, augmenting Figure
than one octave; the total output noise is 60µVRMS with the 173’s circuit to obtain a dual 5th order filter from a single
rail-to-rail output for a peak SNR of 95dB from ±5V LTC1562.
supplies.
Conclusion
Quadruple 3rd Order 100kHz Butterworth Lowpass Filter
The LTC1562 is the first truly compact universal active
Another example of the flexibility of the virtual-ground filter, yet it offers instrumentation-grade performance
inputs is the ability to add an extra, independent real pole rivaling much larger discrete-component designs. It serves
with an R-C-R “T” network. In Figure 179, a 10k input applications in the 10kHz–150kHz range with an SNR as
resistor has been split into two parts and the parallel high as 100dB or more (16+ equivalent bits). The LTC1562
combination of the two forms a 100kHz real pole with the is ideal for modems and other communications systems
680pF external capacitor. Four such 3rd order Butterworth and for DSP antialiasing or reconstruction filtering.
10 20
0
0
–10
–20 –20
–30
GAIN (dB)
GAIN (dB)
– 40
–40
– 60
–50
–60 –80
–70
–100
–80
–90 –120
1k 10k 100k 1M 10 100 500
FREQUENCY (Hz) FREQUENCY (kHz)
1562 TA09
Figure 176. Frequency Response of Figure 175’s Circuit Figure 178. Frequency Response of Figure 177’s Circuit.
AN87-103
Application Note 87
RIN1A RIN1B RIN2B RIN2A
6.19k 3.83k 1 20 3.83k 6.19k
VIN1 IINV B INV C VIN2
CIN1 RQ1, 10k 19 RQ2, 10k CIN2
2
680pF V1 B V1 C 680pF
R21, 10k 3 18 R22, 10k
V2 B V2 C
VOUT1 5 16 VOUT2
5V V + LTC1562 V– –5V
0.1µF 6 15 0.1µF
SHDN AGND
R23, 10k 8 13
RIN3A RIN3B V2 A V2 D RIN4B RIN4A
6.19k 3.83k 9 12 R24, 10k 3.83k 6.19k
VIN3 V1 A V1 D VIN4
CIN3 RQ3, 10k 10 11 RQ4, 10k CIN4
680pF INV A INV D 680pF
VOUT3 VOUT4 1562 TA07
ALL RESISTORS = 1% METAL FILM
Figure 179. Quad 3-Pole 100kHz Butterworth Lowpass Filter
HIGH CLOCK-TO-CENTER FREQUENCY RATIO sums and differences of the clock and the input, in addition
LTC1068-200 EXTENDS CAPABILITIES OF SWITCHED to sums and differences of their harmonics. The input of
CAPACITOR HIGHPASS FILTER the filter must be band limited to remove frequencies that
by Frank Cox will mix with the clock and end up in the passband of the
filter. Unfortunately, the passband of a highpass filter
The circuit in Figure 180 is a 1kHz 8th order Butterworth
extends upward in frequency by its very nature. If you have
highpass filter built with the LTC1068-200, a switched
to band limit the input signal too much you will also limit
capacitor filter (SCF) building block. In the past, commer-
the passband of the filter, and hence its usefulness.
cially available switched capacitor filters have had limited
use as highpass filters because of their sampled-data
What makes this filter different is the 200:1 clock-to-center
nature. Sampled-data systems generate spurious fre-
frequency ratio (CCFR) and the internal sampling scheme
quencies when the sampling clock of the filter and the
of the LTC1068-200. Figure 181a shows the amplitude
input signal mix. These spurious frequencies can include
response of the filter plotted against frequency from
RH2 10k RH3 1.47k
LTC1068-200
1 28
INV B INV C
R21 20k 2 27 R22 10k
HPB/NB HPC/NC
R11 10k R31 10k 3 26 R32 24.3k
VIN BPB BPC
4 25
LPB LPC
R41 20k 5 24 R42 10k
SB SC
6 23
NC V– –5V
7 22
AGND NC 0.1µF
8 21
5V V+ CLK
9 20
0.1µF NC NC
10 19
SA SD 200kHz
R43 11.3k 11 18 R44 16.9k
LPA LPD
R33 10k 12 17 R34 10k
BPA BPD
13 16
HPA/NA HPD/ND
R23 11.3k 14 15 R24 16.9k
INV A INV D
VOUT
RH4 14.7k
Figure 180. LTC1068-200 1kHz 8th Order Butterworth Highpass Filter
AN87-104
Application Note 87
100Hz to 10kHz. For comparison, Figure 181b shows the and even above, albeit with some care. Figure 182b shows
same filter built with an LTC1068-25. This is a 25:1 CCFR the LTC1068-200 highpass filter with an input frequency
part. The 200:1 CCFR filter delivers almost 30dB more of 150kHz. There is a spurious signal at 50kHz, but even
ultimate attenuation in the stopband. A standard ampli- though there is no input filtering, the SFDR is still 60dB.
tude vs frequency plot of a highpass filter can be mislead- For input signals from 100kHz to 150kHz, the filter dem-
ing because it masks some of the aforementioned spuri- onstrates an SFDR of at least 60dB. The SFDR plot of the
ous signals introduced into the passband. Figure 182a is same filter built with the LTC1068-25 is shown in Figure
a spectrum plot of the 200:1 filter with a single 10kHz tone 183. Note that the lower CCFR (25:1) part still manages a
on the input. This plot shows that the spurious free respectable 55dB SFDR with a 10kHz input. The LTC1068-
dynamic range (SFDR) of the LTC1068 highpass filter is in 25 is used primarily for band-limited applications, such as
excess of 70dB. In fact, the filter has a 70dB SFDR for all lowpass and bandpass filters.
input signals up to 100kHz. In a 200kHz sampled-data Note:
system, you would normally need to band limit the input
below 100kHz, the Nyquist frequency. Because the The filters for this article were designed using Linear Technology’s Filter-
CAD™ (version 2.0) for Windows®. This program made the design and
LTC1068 uses double sampling techniques, its useful optimization of these filters fast and easy.
input frequency range extends to the Nyquist frequency
–10dB –10dB –10dB

10dB/DIV
10dB/DIV
10dB/DIV
100Hz 5kHz 10kHz 100Hz 5kHz 10kHz 200Hz 100kHz 200kHz

DI_1068_02a. EPS
DI_1068_02b. EPS
Figure 181a. Amplitude vs Figure 181b. Amplitude vs Frequency Figure 182a. Spectrum Plot of DI_1068_03a. EPS
Frequency Response of Figure Response of Comparable Filter Using Figure 180’s Circuit with a Single
180’s Circuit the LTC1068-25 10kHz Input
–10dB –10dB
10dB/DIV
10dB/DIV
200Hz 100kHz 200kHz 100Hz 12.5kHz 25kHz
DI_1068_03b. EPS
Figure 183. Spectrum Plot of a Comparable Filter DI_1068_04. EPS
Figure 182b. Spectrum Plot of Figure Using the LTC1068-25 with a Single 10kHz Input
180’s Circuit with a Single 150kHz Input Shows a Respectable 55dB SFDR.
AN87-105
Application Note 87
CLOCK-TUNABLE, HIGH ACCURACY, QUAD 2ND power filter applications, the LTC1068-50 power supply
ORDER, ANALOG FILTER BUILDING BLOCKS current is 4.5mA with a single 5V supply and 2.5mA with
a single 3V supply. The LTC1068 products are available in
by Philip Karantzalis
a 28-pin SSOP surface mount package. The LTC1068 (the
100:1 part) is also available in a 24-pin DIP package.
Introduction
LTC1068-200 Ultralow Frequency
The LTC1068 product family consists of four monolithic, Linear-Phase Lowpass Filter
clock-tunable filter building blocks. Each product contains
four matched, low noise, high accuracy 2nd order switched Figure 184 shows an LTC1068-200 linear-phase 1Hz
capacitor filter sections. An external clock tunes the center lowpass filter schematic and Figure 185 shows its gain
frequency of each 2nd order filter section. The LTC1068 and group delay responses. The clock frequency of this
products differ only in their clock-to-center frequency filter is 400 times the –3dB frequency (f–3dB or fCUTOFF).
ratio. The clock-to-center frequency ratio is set to 200:1 The large clock-to-fCUTOFF frequency ratio of this filter is
(LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or useful in ultralow frequency filter applications when mini-
25:1 (LTC1068-25). External resistors can modify the mizing aliasing errors could be an important consider-
clock-to-center frequency ratio. Designing filters with an ation. For example, the 1Hz lowpass filter shown in Figure
LTC1068 product is fully supported by the FilterCAD 2.0 184 requires a 400Hz clock frequency. For this filter, the
design software for Windows. The internal sampling rate input frequencies that can generate aliasing errors are in
of all the LTC1068 devices is twice the clock frequency. a band from 795Hz to 805Hz (2 • fCLK ±5 • f–3dB). For most
This allows the frequency of input signals to approach very low frequency signal-processing applications, the
twice the clock frequency before aliasing occurs. Maxi- signal spectrum is less than 100Hz. Therefore, Figure
mum clock frequency for LTC1068-200, LTC1068 and 184’s filter will process very low frequency signals without
LTC1068-25 is 6MHz with ±5V supplies; that for the significant aliasing errors, since its clock frequency is
LTC1068-50 is 2MHz with a single 5V supply. For low 400Hz and the aliasing inputs are in a small band around
800Hz.
RL1 23.2k
RL2 14.3k
LTC1068-200
1 28
INV B INV C
R21 12.4k 2 27 R22 15.4k
HPB/NB HPC/NC
R11 14.3k R31 10k 3 26 R32 10k
VIN BPB BPC
4 25 R52 5.11k
LPB LPC
R41 15.4k 5 24 R62 9.09k 10 1.0
SB SC
6 23 0 0.9
NC V– –5V
GAIN
7 22 –10 0.8
AGND NC
8 21 0.1µF –20 0.7
+
GROUP DELAY (s)
5V V CLK 400kHz
0.1µF 9 R64 9.09k
20 –30 0.6
GAIN (dB)
NC NC
10 19 R54 5.11k
SA SD –40 0.5
R43 12.4k 11 18 GROUP
LPA LPD VOUT –50 DELAY 0.4
R33 12.4k 12 17
BPA BPD –60 0.3
13 16 R34 10k
HPA/NA HPD/ND –70 0.2
R23 10k 14 15 R24 15.4k
INV A INV D –80 0.1
–90 0.0
RB3 23.2k 0.1 1 10
FREQUENCY (Hz)
RL3 23.2k
Figure 185. Gain and Group Delay
Figure 184. Linear-Phase Lowpass Filter: f–3dB = 1Hz = fCLK/400 Response of Figure 184’s Circuit.
AN87-106
Application Note 87
LTC1068-50 Single 3.3V Low Power LTC1068-25 Selective Bandpass Filter
Linear-Phase Lowpass Filter is Clock Tunable to 80kHz
Figure 186 is a schematic of an LTC1068-50-based, single Figure 188 shows a 70kHz bandpass filter based on the
3.3V, low power, lowpass filter with linear phase. The LTC1068-25 operating with dual 5V power supplies. The
clock-to-fCUTOFF ratio is 50 to 1 (fCUTOFF is the –3dB clock-to-center frequency ratio is 25 to 1. Figure 189
frequency). Figure 187 shows the gain and group delay shows the gain response of Figure 188’s bandpass filter.
response. The flat group delay response in the filter’s The passband of this filter extends from 0.95 • fCENTER to
passband implies a linear phase. A linear-phase filter has 1.05 • fCENTER. The stopband attenuation is greater than
a transient response with very small overshoot that settles 40dB at 0.8 • fCENTER and 1.15 • fCENTER. The center
very rapidly. A linear-phase lowpass filter is useful for frequency can be clock tuned to 80kHz with dual 5V
processing communication signals with minimum supplies and to 40kHz with a single 5V supply. With
intersymbol interference in digital communications trans- FilterCAD, the LTC1068-25 can be used to realize band-
mitters or receivers. The maximum clock frequency for pass filters less selective than that shown in Figure 188,
this filter is 1MHz with a single 3.3V supply and 2MHz with which can be clock tuned up to 160kHz with dual 5V
a single 5V supply. Typical power supply current is 3mA supplies.
with a single 3.3V supply and 4.5mA with a single 5V
supply.
RA1 56.2k RL2 9.09k
RB1 13.3k RH2 34k
LTC1068-50
1 28
INV B INV C 10 150
R21 20.5k 2 27 R22 43.2k
HPB/NB HPC/NC 0 140
R11 22.6k R31 10k 3 26
VIN BPC GAIN
BPB –10 130
4 25 R32 43.2k
LPB LPC
GROUP DELAY (µs)

R41 22.6k 5 24 R42 196k –20 120
SB SC
GAIN (dB)
6 23 –30 110
NC V–
7 22 –40 GROUP 100
AGND NC DELAY
8 21 90
3.3V V+ CLK 500kHz –50
9 20
0.1µF NC NC –60 90
10 19
1µF SA SD –70 70
R43 48.7k 11 18 R44 34.8k
LPA LPD
R33 12.7k 12 –80 60
17
BPA BPD
R34 14.3k 1k 10k 100k
13 16
HPA/NA HPD/ND FREQUENCY (Hz)
R23 10.7k 14 15 R24 16.9k
INV A INV D
VOUT
RB3 24.9k
Figure 187. Gain and Group Delay
Response of Figure 186’s Filter
RL3 26.7k
Figure 186. Low Power, Single 3.3V Supply,

10kHz, 8th Order, Linear-Phase Lowpass Filter
AN87-107
Application Note 87
RL2 23.2k
RH1 28k 10
RH2 11.3k 0
LTC1068-25
1 28 –10
INV B INV C
R11 R21 4.99k 2 27 R22 4.99k –20
HPB/NB HPC/NC
29.4k R31 24.9k R32 107k
3 26 –30
GAIN (dB)
VIN BPB BPC
4 25 –40
LPB LPC
R41 20.5k R51 4.99k 5 24 R52 4.99k R62 56.2k
SC –50
SB
R61 11.3k 6 – 23 –60
NC V –5V
7 22 0.1µF
AGND NC 1.75MHz –70
8 + 21
5V V CLK –80
0.1µF 9 20 R64 10k
NC NC –90
10 19 R54
SA SD 20 30 40 50 60 70 80 90 100
4.99k
R43 42.3k 11 18 FREQUENCY (kHz)
LPA LPD
R33 59k 12 17 R44 17.4k
BPA BPD
13 16 R34 63.4k
HPA/NA HPD/ND
R23 4.99k 14 15 R24 7.5k
Figure 189. Gain Response
INV A INV D of Figure 188’s Filter
VOUT
RH3 15.4k
RL3 45.3k
Figure 188. 70kHz, 8th order, Bandpass Filter
LTC1068 Square-Wave-to-Quadrature Oscillator Filter
Figure 190 shows the schematic of a LTC1068 based filter cycle less or more than 50% and will also have even
that is specifically designed to produce a low harmonic harmonics (2nd, 4th, 6th and so on). The filter of Figure
distortion sine and cosine oscillator from a CMOS-level 190 has a stopband notch at the 2nd and 3rd harmonics for
square wave input. The reference sine wave output of a square wave input with a frequency equal to the filter’s
Figure 190’s circuit is on pin 15 (BPD on the 24-pin clock frequency divided by 128. The filter’s sine wave
LTC1068 package) and the cosine output is on pin 16 output (pin 15) is 1VRMS for a ±2.5V square wave input and
(LPD on the 24-pin LTC1068 package). The output fre- has less than 0.025% THD (total harmonic distortion) for
quency of this quadrature oscillator is the filter’s clock input frequencies up to 16kHz and less than 0.1% THD for
frequency divided by 128. The output of a CMOS CD4520 frequencies up to 20kHz. The cosine output (on pin 16,
divide-by-128 counter is coupled with a 0.47µF capacitor referenced to pin 15’s sine wave output) is 1.25VRMS for
to the input to the LTC1068 filter operating with dual 5V a ±2.5V square wave input and has less than 0.07% THD
power supplies. The filter’s clock frequency is the input to for frequencies up to 20kHz.
the CD4520 counter. The LTC1068 filter is designed to
pass the fundamental frequency component of a square The 20kHz frequency limit is due to the CD4520; with a
wave and attenuate any harmonic components higher 74HC type divide-by-128 counter, sine and cosine waves
than the fundamental. An ideal square wave (50% duty up to 40kHz can be generated with the LTC1068-based
cycle) will have only odd harmonics (3rd, 5th, 7th and so filter of Figure 190.
on), whereas a typical practical square wave has a duty
AN87-108
Application Note 87
RL2 12.4k
RL1 12.4k
RH2 55.2k
LTC1068
1 24
INV B INV C
R21 10k 2 23 R22 10k
HPB/NB HPC/NC
R11 22.4k R31 12.4k 3 22
BPB BPC
4 21 R32 12.4k
0.47µF LPB LPC –5V
5 20
SB SC 0.1µF
6 19
AGND V–
7 18
5V V+ CLK
8 17
0.1µF SA SD *COSINE WAVE OUT f
9 16 fOUT = CLK
LPA LPD *SINE WAVE OUT 128
R33 12.4k 10 15 R34 10k
BPA BPD
R23 10k 11 14
HPA/NA HPD
12 13 R24 10k
INV A INV D
RH3 38.4k
RL3 16.5k
fCLK = 1 3 ÷2 * PIN 16'S COSINE WAVE OUTPUT IS REFERENCED TO

CLK 1Q0
128 × fOUT 2 4 ÷4
PIN 15'S SINE WAVE OUTPUT
1Q1
16 5 ÷8
5V 1Q2
10 6 ÷16
0.1µF CD4520 1Q3
7 11 ÷32
GND 2Q0
8 12 ÷64
2Q1
9 13 ÷128
2Q2
15 14 ÷256
2Q3
Figure 190. Square-Wave-to-Quadrature Oscillator Converter
AN87-109
Application Note 87
Miscelleaneous
is monitored by an LTC1440 ultralow power comparator,
BIASED DETECTOR YIELDS HIGH SENSITIVITY WITH and by a second diode, which serves as a reference.
ULTRALOW POWER CONSUMPTION
by Mitchell Lee When a signal at the resonant frequency of the antenna is
received, Schottky diode D1 rectifies the incoming carrier
RF ID tags, circuits that detect a “wake-up” call and return and creates a negative-going DC bias shift at the nonin-
a burst of data, must operate on very low quiescent current verting input of the comparator. Note that the bias shift is
for weeks or months, yet have enough battery power in sensed at the base of the antenna where the impedance is
reserve to answer an incoming call. For smallest size, most low, rather than at the Schottky where the impedance is
operate in the ultrahigh frequency range, where the design high. This introduces less disturbance into the tuned
of a micropower receiver circuit is problematic. Familiar antenna and transmission-line system. The falling edge of
techniques, such as direct conversion, super regeneration the comparator triggers a one-shot, which temporarily
or superheterodyne, consume far too much supply cur- enables answer-back and other pulsed functions.
rent for long battery life. A better method involves a
technique borrowed from simple field-strength meters: a Total current consumption is approximately 5µA. Mono-
tuned circuit and a diode detector. lithic one-shots draw significant load current, but the
venerable ‘4047 is about the best in this respect. Alterna-
Figure 191 shows the complete circuit, which was tested at tively, a discrete one-shot constructed from a quad NAND
470MHz. It contains a couple of improvements over the gate draws negligible power.
standard L/C-with-whip field-strength meter. Tuned circuits
aren’t easily constructed or controlled at UHF, so a trans- Sensitivity is excellent. The finished circuit can detect
mission line is used to match the detector diode (1N5711) 200mW radiated from a reference dipole at 100'. Range,
to a 6" whip antenna. The 0.22-wavelength section pre- of course, depends on operating frequency, antenna ori-
sents an efficient, low impedance match to the base of the entation and surrounding obstacles; in the clear, a more
quarter-wave whip, but transforms the received energy to reasonable distance, such as 10', can be covered at
a relatively high voltage at the diode for good sensitivity. 470MHz with only a few milliwatts.
Biasing the detector diode improves the sensitivity by an All selectivity is provided by the antenna itself. Add a
additional 10dB. The forward threshold is reduced to quarter-wave stub (shorted with a capacitor) to the base
essentially zero, so a very small voltage can generate a of the antenna for better selectivity and improved rejection
meaningful output change. The detector diode’s bias point of low frequency signals.
9VDC
λ /4
D1 2X9.1MΩ
1N5711 λ /0.22 FB 27kΩ
+ CMOS Q
Z0 = 50Ω LTC1440 ONE-SHOT
100pF (CD4047)
DETECTOR Q
–
27kΩ
100pF
D2
REFERENCE 1N5711
DI1440_01.EPS
Figure 191. Micropower Field Detector for Use at 470MHz
AN87-110
Application Note 87
ZERO-BIAS DETECTOR YIELDS HIGH the origin reveals that it follows the ideal diode equation,
SENSITIVITY WITH NANOPOWER CONSUMPTION with scales of millivolts and nanoamperes. To use a zero-
by Mitchell Lee bias diode at the origin, the external comparator circuitry
must not load the rectified output.
RF ID tags, circuits that detect a “wake-up” call and return
a burst of data, must operate on very low quiescent
The LTC1540 nanopower comparator and reference is a
current for months or years, yet have enough battery
good choice for this application because it not only pre-
power in reserve to answer an incoming call. For smallest
sents no load to the diode, but also draws only 300nA from
size, most operate in the ultrahigh frequency range, where
the battery. This represents a 10-times improvement in
the design of a micropower receiver circuit is problematic.
battery life over biased detector schemes.2 The input is
Familiar techniques, such as direct conversion, super CMOS, and input bias current consists of leakage in a
regeneration or superhetrodyne, consume far too much small ESD-protection cell connected between the input
supply current for long battery life. A better method and ground. The input leakage measures in the picoampere
involves a technique borrowed from simple field-strength range, whereas the 1N5712 leaks hundreds of picoamperes.
meters: a tuned circuit and a diode detector. Any rectified output from the diode is loaded by the diode
itself, not by the LTC1540, and the sensitivity can match
Figure 192 shows the complete circuit, which was tested that of a loaded, biased detector.
for proof-of-concept at 445MHz. This circuit contains a
couple of improvements over the standard L/C-with-whip The rectified output is monitored by the LTC1540 com-
field-strength meter. Tuned circuits aren’t easily con- parator. The LTC1540’s internal reference is used to set up
structed or controlled at UHF, so a transmission line is a threshold of about 18mV at the inverting input. A rising
used to match the detector diode (1N5712) to a quarter- edge at the comparator output triggers a one-shot, which
wave whip antenna. The 0.23λ transmission-line section temporarily enables answer-back and any other pulsed
transforms the 1pF (350Ω) diode junction capacitance to functions.
a virtual short at the base of the antenna. At the same time,
it converts the received antenna current to a voltage loop Total supply current is 400nA, consuming just 7mAH
at the diode, giving excellent sensitivity. battery life over a period of five years. Monolithic one-
shots draw significant load current, but the ’4047 is about
Biasing the detector diode can improve sensitivity,1 but the best in this respect. A one-shot constructed from
only when the diode is loaded by an external DC resis- discrete NAND gates draws negligible power.
tance. Careful curve-tracer examination of the 1N5712 at
2V–11V
λ/4
12M
FB 10k 5
3 6
+ 7 Q
8 CMOS ONE-SHOT
LTC1540
(CD4047)
4 1 Q
– 2
10nF 10nF
O.23λ
180k
1N5712
Figure 192. Nanopower Field Detector
AN87-111
Application Note 87
Sensitivity is excellent, and the circuit can detect about measure the line, a 1pF capacitor can be substituted for the
200mW from a reference dipole at 100 feet. Range, of diode to avoid large signal effects in the diode itself.
course, depends on operating frequency, antenna orienta- Consult the manufacturer’s data sheet for accurate charac-
tion and surrounding obstacles. Sensitivity is independent terization of diode impedance at the frequency of interest.
of supply voltage; this receiver will work just as well with
a 9V battery as with a single lithium cell. Notes:
1. Eccles, W.H. Wireless Telegraphy and Telephony, Second Edition. Ben

The length of the transmission line does not scale with Brothers Limited, London, 1918, page 272.
frequency. Owing to a decrease in diode reactance, the
electrical length will shorten as frequency increases. Adjust 2. Lee, Mitchell. “Biased Detector Yields High Sensitivity with Ultralow Power
Consumption.” Page 110 of this application note.
the line length for minimum feed-point impedance at the
operating frequency. If an impedance analyzer is used to
TRANSPARENT CLASS-D AMPLIFIERS The Electric Heater—a Simple Class-D Amplifier

FEATURING THE LT1336
by Dale Eagar Class-D amplifiers can be simple or complex, depending
on what is required by the application. A simple class-D
Introduction amplifier is the thermostatic switch in an electric heater.
The thermostat controls the heater by turning it on or off.
Efficiency in the field of power conversion is like transpar- The switch is essentially lossless, dissipating practically
ency in the field of light transmission. It is no wonder, no power. This class-D amplifier is remarkably efficient,
then, that Class-D amplifiers are often called transparent, since even the energy lost in the switch, power cord and
since they have no significant power losses. In contrast to house wiring contributes to the desired result. The duty
class-D amplifiers’ nearly lossless switching, class-A factor, and hence the average amount of power delivered
through class-C amplifiers are throttling devices that to the heater, can assume an infinite number of values.
waste significant energy. Amplifiers of the “lower classes” This is true even though a constant amount of heat is
(A–C) are modeled as rheostats (variable resistors), delivered when the heater is on.
whereas class-D amplifiers are modeled as variacs (vari-
able transformers). The ideal resistor dissipates power, Quadrants of Energy Transfer
whereas the ideal transformer does not. Like transformers
(variacs), many class-D amplifiers can transfer energy in Class-D amplifiers have a property that requires new
both directions—input to output and output to input. terminology, a property that generally isn’t considered in
lower-class amplifiers. This property, quadrants of energy
Class-D amplifiers also have a way of ignoring reactive transfer, describes the output characteristics of the class-
loads that can be uncanny. A class-D amplifier operating D amplifier. The output characteristics are plotted on a
with an AC output will draw very little additional input imaginary X-Y plot (I’ve yet to see someone actually do
power when a sizable capacitive or inductive load is placed one on paper), one axis representing output voltage and
at its output. This is because the reactive load has AC the other axis representing output current, with the inter-
voltage across it and AC current flowing through it, but the section of the axes representing zero volts and zero amps.
phase angle of the voltage and current is such that no real A simple switcher that can only provide a positive output
power is dissipated. The class-D amplifier ends up shut- current into a positive output voltage can be described as
tling power back and forth between its input and its output, a 1-quadrant device. This 1-quadrant device could be a
doing both with minimal loss. An ideal class-D amplifier computer power supply, a battery charger or any supply
can be thought of as having no place to dissipate power, that delivers a positive voltage into a device that can only
since all of its components are lossless; that is, it contains consume power.
no resistors.
AN87-112
Application Note 87
The 2-quadrant converter can be one of two different Introducing the LT1336 Half-bridge Driver
things: 1) A positive output voltage that can both source
and sink current, or 2) A positive current that can comply Taking a side step from our main discussion, we will
both positive and negative output voltage. Finally, the 4- introduce a component, the half-bridge power amplifier.
quadrant converter can both source and sink current into Figure 194 details the LT1336 driving power MOSFETs
both positive and negitive output voltages. and shows the symbolic representation of this subcircuit
that will appear in subsequent figures. Table 1 shows the
1-Quadrant Class-D Converter logical states of this half-bridge power driver.
To illustrate the 1-quadrant class-D amplifier, we will 4-Quadrant Class-D Amplifier

focus on the boost mode converter detailed in Figure 193
This circuit removes power from the source (12V automo- Class-D amplifiers are commonly used in subwoofer driv-
tive battery) and delivers it to the load (some as-yet- ers. This is because subwoofers require a great deal of
unknown 55V device) This circuit is classified as “1 power. A class AB amplifier driving a subwoofer will put
quadrant” because it can only regulate output voltage in about half of its input power into its heat sink. Driving the
one polarity (positive) and it can output current in only one same subwoofer at the same volume with the same music,
polarity (positive). a class-D amplifier will put about five percent of its input
+
PRi 20T 2x#14
HEFTY + + + + R1 SEC 4T #26
WIRES C1 C2 C3 C4
1Ω MICROMETALS T150-52
FROM CAR
BATTERY C5 D3
9V-15V 1200µF, 16V ×4 22µF MUR110
– 20V
SEC D4 12V
+
MUR110
T1
PRi + C11 + C13
36µH 20 4 33µF 2200µF
5 8 30A
C6
+ 16V 25V
R2 7 U2A 7
1500pF + C12
100k 1 VIN LT1215
6 33µF
COMP – 16V
4
D2 55V, 3.3A
R4
R3 MBR1060
2.49k 2
51k FB
R16
8 6 20Ω Q2 Q3
+ + +
VREF U1 GTDR C14 C15 C19
IRFZ44 IRFZ44
C7 LT1243
R5 D1 R17
0.1µF
15k 1N5819 20Ω
4 1000µF, 63V ×6
Q1
R/C
2N3904
C8 R12 R13 R14 R15
C9 1µF
R6 0.01Ω 0.01Ω 0.01Ω 0.01Ω
0.15
2.4k 1W 1W 1W 1W
3
ISEN
GND R11
R7 5 1k
1k R8 3
+
1k 1 C10
U2B
LT1215 220pF
2
–
R9 R10
1k 100Ω
Figure 193. 200W, 12V to 55V Front End for Automotive Applications
AN87-113
Application Note 87
power into the heat sink. The difference is ten to one on the Table 7. Half-Bridge Power Driver Truth Table
heatsink size and two to one on the input power supply.
In Top In Bottom Output
Figure 195 is the 200W class-D subwoofer driver. This
L L Floating
circuit uses the 200W front end developed in Figure 193 as
its power source. The circuit in Figure 195 performs as L H Ground
follows: U1a, R1–R4 and C7 implement a 75kHz H L 55V
pseudosawtooth oscillator. U1d is the input amplifier/ H H Floating
filter, with a gain of 6.1 and 200Hz Butterworth lowpass
response. U1b and U1c are comparators that compare the energy ends up on the 55V bus, where the bus voltage
sawtooth and the amplified/filtered input signal to form climbs during these periods of “negative energy deliv-
two complimentary, pulse-width modulated square waves. ered to the load.” Fortunately, C14–C19 of Figure 193 can
X1 and X2 are two half-bridge power drivers and M1 is the store this energy; otherwise the 55V bus would subject to
subwoofer driver. excessive voltage until someplace was found for the
energy to go.
One of the properties of Class-D, 4-quadrant amplification
is the ability to transfer power both to and from the load. Class-D for Motor Drives
In our subwoofer driver, this happens when the driver
reaches the end of any given excursion and the combina- Substituting a motor and an inductor for the subwoofer in
tion of the driver spring and the acoustic spring drive the Figure 195 and simplifying the control, we arrive at the
cone back to center. During this time, energy is trans- circuit shown in Figure 196. Connecting this circuit to the
ferred from the driver back to the input of the class-D front end shown in Figure 193 and then getting the motor
amplifier stage. In the case shown in Figure 195, the up to speed is no problem, but when one wants to slow the
T1
COILTRONICS
CTX100-P 12V 55V
D3
1N4148 IN
TOP
C1 OUT
1µF IN
BOTTOM
R1 12V D5
6.2k C2 0.1µF 1N4148
C3 (SYMBOLIC REPRESENTATION)
D4
1N4148 1µF
R2 2Ω
R3, 10Ω 55V
2 10 14
V+ V+ BOOST 13 R4, 10Ω
1 TGD
ISEN 12 Q1 Q2
16 TGF IRFZ44 IRFZ44
SW
11
D1 TSOU OUT
1A R5, 10Ω
60V U1
LT1336 R6, 10Ω
9 Q3 Q4
3 BGD
IN TOP IN TOP D2 IRFZ44 IRFZ44
4 1A
IN BOTTOM IN BOTTOM
60V
8
SW S BGF
GND GND PGND
15 6 7
Figure 194. Half-Bridge Driver Subcircuit and Symbolic Representation
AN87-114
Application Note 87
12V
R1
15k
12V 18" SUBWOOFER
R3 C8 DRIVER
R2
1.8k 0.1µF 1mH, 6.5Ω
15k
12V 55V 55V 12V
10 5 4
+ +
8 U1A U1B 7 F1
LT1365 LT1365 M1 10A
9 6
R4
– –
15k
C7
220pF
R5
15k 75kHz
3
+
U1C 1
LT1365
2
– 11
C4
0.015 R8
100Ω
C1
2.2µF R6 R7 R9
1.8k 18k 18k 3
+
INPUT +
C2 C5 U1D 1
C3
0.47µF 0.022µF LT1365
0.1µF
2
–
C6
2.2µF R11 R10
10k 51k
+
Figure 195. 200W-Powered Subwoofer

12V
15k
12V
1.8k 15k 0.1µF

LOAD
12V 55V 55V 12V
10 4
+ +
L1
8 U1A U1B
1mH
LT1365 LT1365
9
– – X1 M X2
220pF
15k
3
+
U1C 1
LT1365 3
2 –
12V – 11 U1D 1
MOTOR LT1365
2
SPEED +
AND POT 1
DIRECTION
Figure 196. Class-D Motor Drive
AN87-115
Application Note 87
+
+ + + + PRi 20T 2x#14
12V BATTERY R1 SEC 4T #26
C1 C2 C3 C4
1Ω MICROMETALS T150-52
–
D1
1200µF, 16V ×4 MUR110
+ C5
SEC D2 12V
22µF 5 8
+ MUR110
20V
U2A T1
6
LT1215 + C11 + C13
– 20 4 33µF 2200µF
4 2k 16V 25V
C6
R2 7
1.5µF + C12
100k 1 VIN
COMP VN2222 33µF
55V
+
16V
R4
R3 2.49k
51k 2 + + +
FB
C14 C15 C19
8 6
VREF U1 GTDR
C7 LT1243
R5 1000µF, 63V ×6
0.1µF
15k
Q1 4
R/C
2N3904
C8
C9 1µF R12 R13 R14 R15
0.15µF R6 0.01Ω 0.01Ω 0.01Ω 0.01Ω
2.4k 3 1W 1W 1W 1W
ISEN
GND R11
R7 5 1k
1k R8 3
+
1k 1 C10
U2B
LT1215 220pF
2
–
R9 R10
1k 200Ω
R16
49.9k
Figure 197. 200W, 2-Quadrant Front End for Automotive Applications
motor down by turning pot 1 back toward its center, across the 55V bus and bolted to a massive heat sink. One
disaster strikes. Rotational energy stored in the inertia of could easily imagine the heat sink as the brake shoes
the motor is converted back into electrical energy by the heating up as the electric vehicle winds down the mountain
motor and is presented to the output of the class-D road. Another place to put the energy is back into the 12V
amplifier. L1, X1 and X2 do their job by transferring the battery. This will require upgrading the 12V to 55V front-
energy back into the 55V bus. The energy goes into C14– end power converter from 1 quadrant to 2 quadrants.
C19 of Figure 193, charging them to some voltage
significantly above 55V, and something breaks. The prob- The 2-Quadrant Class-D Converter
lem here is that the circuit in Figure 193 is only a 1-quadrant
class-D amplifier. Converting Figure 193 to two quadrants involves replacing
D2 with a switch and activating the switch out of phase with
Managing the Negative Energy Flow the switch formed by Q2 and Q3. The half-bridge power
driver shown in Figure 195 is just such a switch. Refer to
Sound like a course in management? The negative energy Figure 197. The ISENSE signal (U1, pin 3) needs to be offset
transferred through the class-D amplifier needs a home. to accommodate negative current (add R16, Figure 197)
One simple home is a 62V power Zener diode strapped The ISENSE signal needs to be scaled for twice the range
AN87-116
Application Note 87
(–30A to 30A rather than 0A to 30A); this is done by find some way to fail. We need to stop and drain off some
changing R10. charge, trade batteries with someone climbing the other
side or put a power Zener on our battery. Figure 198 details
Now we are happily winding down the mountain road, the active Zener circuit. Using the reference in U1 of Figure
watching the scenery unfold before us. We are happy in 197 and the unused half of U2 we are able to make a
knowing that we are recycling the energy released from hysteretic clamp that puts all of the heat into a resistor, R5.
the descent by charging our batteries, while watching the This circuit will save the battery from destruction and drop
mountain bikers burn their descent energy off in brake our level of smugness back to that of the mountain bikers.
linings. Once again technology wins over sweat and brawn.
Conclusion
A Trip Over the Great Divide
Class-D has been around for a long time: the venerable
Climbing the great divide in an electric vehicle requires electric heater with its bang-bang controller is a remark-
some planning. Stops to recharge are necessary. Once on ably efficient and reliable class-D amplifier. Class-D drives
top, the whole scheme changes: descending the hill, have been used for decades in golf carts, fork lifts, cranes
charging our battery, all goes well until the battery is fully and industry. The advent of the half-bridge driver greatly
charged; then we have to stop. Further descent would simplifies the Class-D Amplifier. Here at Linear Technol-
overcharge our battery, boiling out the electrolyte. Not ogy we have a family of half/full bridge MOSFET drivers.
only would this ruin our battery, in the end we would have For further information, contact us at the factory or refer to
no place to put the energy and our class-D amplifier would the LT1158, LT1160, LT1162 or LT1336 data sheets.
VIN
R1 R2 R3
49.9k 95k 5M R5
1Ω
200W
8 R4
+
7 100Ω
U2A
IRFZ40
U1 LT1215
VREF 6
FIG 5
5.00V –
PIN 8
14A
0A
14.3V 14.6V
Figure 198. Wolf Creek Pass Adapter
AN87-117
Application Note 87
SINGLE-SUPPLY RANDOM CODE GENERATOR receives the noise at its positive input. A threshold is set
by Richard Markell at the negative comparator input and the output is ad-
justed via the 2k potentiometer for an equal number of
Presented here is a truly random code generator that
ones and zeroes. The 5k resistor and the 10µF capacitor
operates from a single supply. The circuit allows operation
provide limited hysteresis so that the adjustment of the
from a single 5V supply with a minimum of adjustments.
potentiometer is not as critical. Latch U4, a 74HC373,
ensures that the output remains latched throughout one
The circuit produces random ones and zeroes by compar- clock period. The circuit’s output is taken from U4’s Q0
ing a stream of random noise generated in a Zener diode output.
to a reference voltage level. If the threshold is correctly set
and the time period is long enough, the noise will consist Some Thoughts on Automatic Threshold Adjustment
of a random but equal number of samples above and
below threshold. Several circuit designers have asked about threshold
adjustment without manual knobs or potentiometers. One
That Fuzz is Noise way to implement this would be to have the microproces-
sor count the number of ones and zeroes over a given time
The circuit shown in Figure 199 is the random noise period and adjust the threshold (perhaps via a digital pot)
generator. Optimum noise performance is obtained from to produce the required density of ones.
a 1N753A Zener diode, which has a 6.2 volt Zener “knee.”
The diode is used to generate random noise. We have A more “analog” method of adjusting threshold might be
found that optimum noise output for this diode occurs at to implement an integrator with reset. This circuit inte-
the “knee” of the I-V curve, where the Zener just starts to grates the number of ones and zeroes over time to
limit voltage to 6.2 volts. produce a zero result for an adjustment that produces
equal numbers of ones and zeroes. Again, a digital pot
Operating a 6.2V Zener from a 5V supply required some could be used to adjust threshold, with the threshold being
thought. Obviously, some type of voltage boosting scheme decreased for the case of “not enough ones” and in-
was needed to provide the diode with the 8V or more that creased for the case of “too many ones.”
it requires in this circuit. U1, an LTC1340 low noise,
voltage-boosted varactor driver, provides 9.2V at 20µA After many more conversations with the “cyber illumi-
from an input of 5V. This Zener current is the optimal for nati,” the circuit in Figure 200 was devised. This circuit can
noise output from the diode (at 20µA the output is about be used to replace the pot shown in the dashed box in
20mVP-P). Figure 199. In operation, an LT1004-2.5 is used as a
reference at the front end of a precision voltage divider
The 1M and 249k resistors bias the input to operational string. A series of voltages is generated along the divider
amplifier U2 to 1.25V to match the input common mode string and a jumper is used to connect this voltage to a
range of comparator U3. The 1µF capacitor provides an AC buffer and then to the negative input of the LT1116
path for the noise. Note: be careful where you place any comparator. As was the case with the 2k pot, the voltage
additional capacitors in this part of the circuit or the noise at pin 2 (the negative input of the comparator) sets the
may be unintentionally rolled off. This is one circuit where threshold for the comparator. The selection of voltage
noise is desirable. taps on the resistor string is arbitrary; they were selected
to allow a good adjustment range (defined as allowing
U2 is an LT1215 23MHz, 50V/µs, dual operational amplifier jumper adjustment to 50% ones and 50% zeros) for a
that can operate from a single supply. It is used as a sample of ten 1N753A Zener diodes used to produce
wideband, gain-of-eleven amplifier to amplify the noise noise. The jumper could (and probably should) be re-
from the Zener diode; the second op amp in U2 is unused. placed with analog switches controlled by a microprocessor
U3, an LT1116 high speed, ground-sensing comparator, in medium- to high-volume applications.
AN87-118
Application Note 87
5V U1
LTC1340
1 8
CP AVCC
0.1µF
2 7
VCC OUT 9.2V
3 6
SHDN AGND 10pF
0.1µF
4 5
PGND IN 5V
5V 5V
1000pF
+ 1µF 0.1µF 1µF +

0.1µF
~20mVP-P 1µF 1µF +
20
NOISE 3 8
+ 1 VCC
1k
+
U2 1 3
1N753A 1M LT1215
+ 8 3
DO QO
2 2-LEVEL
6.2V 2 U3 OUTPUT
– 4 470k
1µF LT1116 7 U4
1.25V TANT 2 5 LE 74HC373
249k – 6
+ 4 11 LE
GND OE 5k
47k 10 1
+
10µF CLOCK IN +
10µF
5V
2k
10 TURN
Figure 199. Single-Supply Random Code Generator
5V
12k 499 499 499 499 5V

15k 1% 1% 1% 1% 1% 11k
(1.30V) (1.25V) (1.20V) (1.15V) (1.10V) 1% +
1µF
+ 1µF 0.01µF 3 8
LT1004 +
-2.5 1 TO LT1116
JUMPER SELECTS LT1490
PIN 2 (FIGURE 1)
THRESHOLD VOLTAGE 2
– 4
GROUND PINS 5 AND 6
Figure 200. Jumper Selects Threshold for Figure 199’s Circuit
AN87-119
Application Note 87
APPENDIX A: COMPONENT VENDOR CONTACTS
The tables on this and the following pages list contact components from other vendors may also be suitable. For
information for vendors of non-LTC parts used in the information on component selection, consult the text of
application circuits in this publication. In some cases, the respective articles and the appropriate LTC data sheets.
Capacitors
Vendor Product Phone URL
AVX Chip Capacitors (843) 946-0362
www.avxcorp.com/products/capacitors
AVX Tantalum Capacitors (207) 282-5111
Electronic Concepts 400V Film Capacitors (908) 542-7880 www.eci-capacitors.com
Kemet Tantalum Capacitors (408) 986-0424 www.kemet.com
Marcon High C/V Capacitors (847) 696-2000 www.chemi-con.com/main/company/marcon.html
Murata Electronics Capacitors (770) 436-1300 www.iijnet.or.jp/murata/products/english
Nichicon Electrolytic Capacitors (847) 843-7500 www.nichicon-us.com
www.panasonic.com/industrial_oem/electronic_components/
Panasonic Poly Capacitors (714) 373-7334
electronic_components_capacitors_home.htm
Sanyo Oscon Capacitors (619) 661-6835 www.sanyovideo.com
Sprague Capacitors (207) 324-4140 www.comsprague.com
Taiyo Yuden Chip Capacitors (408) 573-4150 www.t-yuden.com
Tokin Capacitors (408) 432-8020 www.tokin.com
United Chemicon Electrolytic Capacitors (847) 696-2000 www.chemi-con.com/main
Vitramon Ceramic Chip Capacitors (203) 268-6261 www.vishay.com
Wima Paper/Film Capacitors (914) 347-2474 www.wimausa.com
Diodes
Vendor Product Phone Number URL
Agilent (formerly Hewlett
IR LEDs (800) 235-0312 www.semiconductor.agilent.com/ir
Packard)
Central Semiconductor Small Signal Discretes (516) 435-1110 www.centralsemi.com
Chicago Miniature Lamp LEDs (201) 489-8989 www.sli-lighting.com/cml
Data Display Products LEDs (800) 421-6815 www.ddp-leds.com
Fuji Schottky Diodes (201) 712-0555 www.fujielectric/co/jp/eng/index-e.html
General Semiconductor Diodes (516) 847-3000 www.gensemi.com

Motorola* Discretes (800) 441-2447 www.mot-sps.com/products/index.html
ON Semiconductor* Discretes (602) 244-6600 www.onsemi.com/home
www.panasonic.com/industrial_oem/semiconductors/
Panasonic LEDs (201) 348-5217
semiconductor_home.htm
Temic IR Photo Diodes (408) 970-5700 www.temic.com
Zener/Small Signal
Vishay (408) 241-4588 www.vishay.com
Diodes
www.zetex.com
Zetex Small Signal Discretes (516) 543-7100
*Discretes formerly manufactured by Motorola are now manufactured by ON Semiconductor. Part numbers have not been chanaged as of January 2000
AN87-120
Application Note 87
Inductors and Transformers
API Delevan Inductors (716) 652-3600 www.delevan.com
BH Electronics Inductors (612) 894-9590 www.bhelectronics.com
BI Technologies Transformers (714) 447-2656 www.bitechnologies.com
Coilcraft Inductors (847) 639-6400 www.coilcraft.com
Cooper Inductors/ Transformers (561) 752-5000 www.coiltronics.com
Dale Inductors/ Transformers (605) 665-1627 www.vishay.com/fp/fp.html#inductors

Gowanda Inductors (716) 532-2234 www.gowanda.com
(605) 886-4385/
Midcom Inductors/ Transformers www.midcom-inc.com
(800) 643-2661
Murata Electronics Inductors (814) 237-1431 www.murata.com
www.panasonic.com/industrial_oem/electronic_components/
Panasonic Inductors/Transformers (714) 373-7334
electronic_components_inductors_coils_and_transformers.htm
Philips Inductors (914) 246-2811 www.acm.components.philips.com
Philips Planar Inductors (914) 247-2036 www.acm.components.philips.com
Pulse Inductors (619) 674-8100 www.pulseeng.com
Sumida Inductors (847) 956-0667 www.japanlink.com/sumida
Tokin Inductors (408) 432-8020 www.tokin.com
Logic
Fairchild Logic (207) 775-4502 www.fairchildsemi.com
Intersil (formerly Harris) Logic (800) 442-7747 www.intersil.com
*Motorola Logic (800) 441-2447 www.mot-sps.com/products/index.html
*ON Semiconductor Logic (602) 244-6600 www.onsemi.com/home
Logic (949) 455-2000/
Toshiba www.toshiba.com/taec
Single Gate Logic (714) 455-2000
*Logic Devices formerly manufactured by by Motorola are now manufactured by ON Semiconductor; there have been no changes in part numbers as of January 2000
Resistors
Allen Bradley Carbon Resistors (800) 592-4888 www.ab.com
AVX Chip Resistors (843) 946-0524 www.avxcorp.com/products/resistors/chiprstr.htm
Resistors/Resistor
BI Technologies (714) 447-2345 www.bitechnologies.com
Networks
Bourns Potentiometers, SIPs (801) 750-7253 www.bourns.com
www.vishayfoil.com
Dale Sense Resistors (605) 665-9301
or www.vishay.com
IRC Sense Resistors (361) 992-7900 www.irctt.com
RG Allen Metal Oxide Resistors (818) 765-8300 www.rgaco.com
TAD Chip Resistors (800) 508-1521 www.tadcom.com
Taiyo Yuden Chip Resistors (408) 573-4150 www.t-yuden.com
Thin Film Technology Thin Film Chip Resistors (507) 625-8445 www.thin-film.com
Tocos SMD Potentiometers (847) 884-6664 www.tocos.com
AN87-121
Application Note 87
Transistors
Central Semiconductor Small Signal Discretes (516) 435-1110 www.centralsemi.com
Fairchild MOSFETs (408) 822-2126 www.fairchildsemi.com
IR MOSFETs (310) 322-3331 www.irf.com
Motorola* Discretes (800) 441-2447 www.mot-sps.com/products/index.html
ON Semiconductor* Discretes (602) 244-6600 www.onsemi.com/home
Philips Discretes (401) 767-4427 www-us.semiconductors.philips.com
Siliconix MOSFETs (800) 554-5565 www.siliconix.com
Zetex Small Signal Discretes (631) 543-7100 www.zetex.com
*Discretes formerly manufacured by Motorola are now manufactured by ON Semiconductor; There are no changes in part numbers as of January 2000.
Miscellaneous
Aavid Heat Sinks (714) 556-2665 www.aavid.com
Epson Crystals (310) 787-6300 www.eea.epson.com
Infineon
(formerly Siemens Optoelectronics (108) 257-7910 www.infineon.com/us/opto/content.htm
Semiconductor)
Magnetics, Inc. Toroid Cores, etc. (800) 245-3984 www.mag-inc.com
MF Electronics Crystal Oscillators (914) 576-6570 www.mfelec.com
Murata Electronics RF Devices (770) 433-5789 www.murata.com
QT Optoelectronics RF Switches (408) 720-1440 www.qtopto.com
Raychem Fuses (800) 227-4856 www.raychem.com
RF Micro Devices RF Semiconductors (336) 664-1233 www.rfmd.com
RTI/Ketema Surge Suppressors (714) 630-0081 www.rtie.rti-corp.com
Schurter Fuses and Holders (707) 778-6311 www.schurterinc.com
Thermalloy Heat Sinks (972) 243-4321 www.thermalloy.com
Toko RF Products (847) 699-3430 www.tokoam.com
Linear Technology Corporation

Product Phone Number URL
High Performance Analog ICs (408) 432-1900 www.linear-tech.com
AN87-122
Application Note 87
Index
A Differential Timing Skew 82
ADC. See Data Converters: D/A Fast Waveform Sampler 82–83, 84
Amplifiers 46–72 Isolated 94–95
16-Bit Accurate 71, 71–72 Overtemperature Detector 94
ADC Buffer 72 Thermistor Temperature Controller 94
Battery Current Monitor 46, 63, 65 Voltage Detector 95
Bridge 49 Low-Battery Warning, Shutdown and Reset for Li-Ion
C-Load 54–56 Supply 81
Cable Driver 48 Pulse Stretcher 83–85, 85
CCD Clock Driver 50–53 Window Detector 81
Chopped 92–93 Converter
Class-D 112–117 RMS/DC 51
2-Quadrant Automotive Front End 116–117 Converters, Data. See Data Converters
200W, 12V to 55V Front End for Automotive Current Meter
Applications 113 0nA–200nA 62
200W-Powered Subwoofer 115 Current Source
Active Zener Circuit 117 Precision 69
Half-Bridge 113–114 D
Motor Drive 115 DAC. See Data Converters: D/A,
Current Feedback 47–49, 50–53, 70–71 Data Converters 3–19
Differential to Single-Ended ADC Driver 68 A/D, 12-Bit 7–10
High Power 56–59 4-Channel 10–12
Instrumentation 67–69. See also Instrumentation Circuits 8-Channel 10–12
Medical ECG Monitor 69 Data Acquisition System 10
Precision Current Source 69 Differential 12
Pressure Monitor 67 Differential to Single-Ended Conversion 68
Single-Supply 67 Micropower 10–12
JFET 54–56 Multichannel 4
Multiplexer 60 Programmable Attenuator 14
"Over-The-Top" 46, 65–66 Programmable Gain Amplifier 11, 12, 14
Peak Detector 54 A/D, 14-Bit 13
Photodiode, Logging 55 8-Channel 13
Power Driver 57, 58 Multiplexer 13
Pressure Sensor 90 A/D, 16-Bit
Programmable Gain 11–12 Buffer 72
Rail-to-Rail 59–60, 62–63, 65–67 D/A, 10-Bit 19
Telescoping 56 D/A, 12-Bit 3–4, 5, 7–10
Track and Hold 54 4-Quadrant Multiplying 6
Twisted Pair Driver 47 Autoranging, with Shutdown 3
Video 61–62, 64–65, 70–71 Dual 14–15
DC-Restore Subcircuit 71 for Digital Control Loop 18
Level Shifter 70 Data Converters
Signal and Power Share Coax Cable 64–65 D/A, 12-Bit (continued)
Voltage Controlled Limiter 61 Micropower 5–6, 18
XDSL 47, 79–80 Quad 5–6
C Wide Swing, Bipolar Output, with Digitally Controlled
C Language Offset 4
Code to Configure PC Analog Interface 7–10 with Programmable Full Scale and Offset 6
Comparators 80–85 with Wide Output Swing 18
1MHz to 10MHz Crystal Oscillator 82 D/A, 16-Bit 16–18
Coincedence Detector 83, 85 2-Quadrant Multiplying 17
AN87-123
Application Note 87
4-Quadrant Multiplying 17 Transmitter 34
I/V Converter with 1.6µs Settling Time 72 Multiprotocol 22–29, 36–37
Digitally Controlled LCD Bias Generator 19 Cable-Selectable DTE/DCE Port 32, 33, 42
F Controller-Selectable DCE Port 39, 45
Controller-Selectable DCE Port with Ring-Indicate 31
Field Detector
Controller-Selectable DTE Port 40
Biased
Controller-Selectable DTE/DCE Port 30, 41
Micropower 110
Controller-Selectable DTE/DCE Port with RLL, LL, TM 43
Zero-Bias
Mode Selection 26
Nanopower 111
Net1 and Net2 Compliant 37–38, 44
Filters 96–109
Resistive Surge Protection for 20–22
Antialiasing 4
LT1137A 21
Bandpass
Testing Line Driver Output Waveform 21
Low Voltage, Narrow 100–101
RS485 36, 37
Selective, Clock-Tunable to 80kHz 107
Standards 23–25
Continuous-Time
Surge-Test Circuit 20
Universal 102–103
V.10 (RS423) 23–24
Highpass
V.11 (RS422) 24, 36
1kHz 8th Order Butterworth 104–105
V.28 (RS232) 24, 36, 37
8th Order 30kHz Chebyshev 102
V.35 25–29
Highpass-Lowpass 96
Lowpass L
1MHz/500kHz Continuous-Time, Low Noise, Elliptic 96–97 LCD Bias Generator
4th Order Butterworth 59 Digitally Controlled 19
50kHz, 100dB Elliptic 103 M
6th Order Elliptic 63
Miscelleaneous 110–119
Butterworth, with Track and Hold 98–99
Multiplexer 4, 10–12, 60
Delay-Equalized Elliptic 96
Multiplexing
Digitally Controlled 16
Softwareless
Dual 4th Order 100kHz Butterworth 102
for 14-Bit A/D 13
Elliptic, 25kHz 99
Mux. See Multiplexer
Quad 3rd Order 100kHz Butterworth 103
Single 3.3V Low Power Linear Phase 107 O
Single-Supply 4th Order Butterworth 66 Operational Filter Blocks 102–103
Ultrlow Frequency, Linear-Phase 106 Oscillator
Notch Crystal
Narrow-Band 101 1MHz to 10MHz 82
Square-Wave-to-Quadrature Oscillator 108 with Complementary Outputs and 50% Duty Cycle 93
Switched Capacitor Sequencer for Ring-Tone Generator 74
Universal 98–101, 106–108 Square-Wave-to-Quadrature 108
I P
Instrumentation Circuits 86–95. See also Amplifiers: PC Analog Interface 7–10
Instrumentation PGA. See Amplifiers: Programmable Gain
Bridge Power Supply
High Performance Capacitance 87–89 60V and –180V, for Ring-Tone Generator 73
with Increased Sensitivity 89 Li-Ion with Low-Battery Warning, Shutdown and Reset 81
Chopped Amplifier 92–93 R
Pressure Sensor
Water Tank 89–92 Random Code Generator
Voltage-to-Frequency Converter 86, 90 Single-Supply 118
Interface Circuits 20–45 T
1488 Line Driver with TVS Surge Protection 20 Telecommunications Circuits 73–79
IrDA 34–35 HDSL Driver 79
Receiver 34 Ring-Tone Generator 73–78
an87f LT/LCG 1100 4K • PRINTED IN USA

Linear Technology Corporation
AN87-124 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
● ●  LINEAR TECHNOLOGY CORPORATION 2000

Linear Technology: Application Note 87 November 2000

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Application Note 87

Linear Technology Magazine Circuit Collection, Volume V

Richard Markell, Editor

Figure 1. An Autoranging 8-Channel ADC with Shutdown

Figure 2. A Wide-Swing, Bipolar Output DAC with Digitally Controlled Offset

MULTICHANNEL A/D USES

VREF VCC DATA IN

0.1µF COM DOUT CLOCK

GND CS DATA OUT

Figure 3. Simple Data Acquisition System Takes Advantage of the LTC1594’s

DIN CLR CLK CLK REFHI B VIN B: 1.22V ± 1.22V

500Ω REFLOD REFLOA DOUT REFHI A VIN A: 1.22V ± 1.22V

REFHI D REFHIA 1.22V

LTC1298 1/2 74HC74 4 C4

Listing 1. C Code to Configure the Analog Interface

#define port 0x3FC /* Control register, RS232 */

THE LTC1594 AND LTC1598: MICROPOWER

Figure 7. Simple Data Acquisition System Takes Advantage of the LTC1598’s

and the LTC1391 as inverting input multiplexer. The R 3 CH7 NC

LTC1598’s MUXOUT drives the ADCIN directly. The 8 COM NC

After the counter is cleared, the multiplexer’s channel –80

increments the counter from 000 to 111, each multiplexer 0 10 20 30 40 50

n Using this effective resistance, the cutoff frequency is

Precision 0V–10V Outputs with One Op Amp 8 1 2 33pF

The full-scale accuracy of the circuit is very precise

LTC1659, LTC1448: SMALLEST RAIL-TO-RAIL

primary concerns of most designers. The LTC1659 and µP VOUT

that address both of these concerns. The LTC1659 is a CS/LD GND

single DAC in an MSOP-8 package that draws only 250µA

Figure 19 shows a convenient way to use the LTC1659 in

*VOUT = 12.7V–24V IN 11mV STEPS

L1 = 10µH (SUMIDA CD43

Figure 21. Digitally Controlled LCD Bias Generator

Many interface circuits must survive surge voltages such Tf

large currents, causing irreversible damage to the IC. TF CONTROLLED BY R2 × COUT

expected in their environments. They can quantify the

Figure 22. LTC Surge-Test Circuit: TF Controlled by R2 • COUT; T1/2

flowing into the IC to a safe level. Resistive protection 3 26

THE LTC1343 AND LTC1344 FORM A SOFTWARE-

Introduction A typical application is shown in Figure 29. Two LTC1343s

Figure 29. LTC1343/LTC1344 Typical Application

A typical V.10 unbalanced interface is shown in Figure 30.

V.36 V.11 V.11 V.11 V.11 V.11 V.11 ———

In V.10 mode, switches S1 and S2 inside the LTC1344 and

A A' 50Ω 50Ω

C' GND C' GND

In V.35 mode, both switches S1 and S2 inside the LTC1344 A

are on, connecting the T-network impedance, as shown in LTC1344 51.5Ω

Figure 39. Mode Selection by Cable

The pull-up resistors R1–R4 ensure a binary 1 when a pin

The mode selection pins M0, M1, M2 and DCE/DTE can be

The mode selection may also be accomplished by using

The interface protocol is selected using the mode select Loop-Back

TXD D2 TXD TXD 103Ω R3 TXD

SCTE D3 SCTE SCTE 103Ω R2 SCTE

TXC R1 103Ω TXC TXC D4 TXC

RXC R2 103Ω RXC RXC D3 RXC

RXD R3 103Ω RXD RXD D2 RXD

RTS D2 RTS RTS R3 RTS

DTR D3 DTR DTR R2 DTR

DCD R1 DCD DCD D4 DCD

DSR R2 DSR DSR D3 DSR

CTS R3 CTS CTS D2 CTS