66
1, JANUARY 2014
A Control Method for Voltage Balancing in Modular
Multilevel Converters
Fujin Deng, Member, IEEE, and Zhe Chen, Senior Member, IEEE
Abstract—The modular multilevel converter (MMC) is attrac-
tive for medium- or high-power applications because of the
advantages of its high modularity, availability, and high power
quality. The voltage balancing of the floating capacitors in the cas-
caded submodules of the MMC is a key issue. In this paper, a
voltage-balancing control method is proposed. This method uses
the phase-shifted carrier-based pulsewidth modulation scheme to
control high-frequency current components for capacitor voltage
balancing in the MMC without measuring the arm currents. Sim-
ulations and experimental studies of the MMC were conducted,
and the results confirm the effectiveness of the proposed capacitor
voltage-balancing control method.
Index Terms—Capacitor voltage balancing, control method,
modular multilevel converter (MMC).
I. INTRODUCTION
ODULAR multilevel converters (MMCs) are an emerg-
M ing and highly attractive converter topology for use
with medium- or high-voltage and high-power applications. The
MMC was developed in the early 2000 s, and it is based on cas-
caded modular cells [1], [2]. The MMC consist of a number
of submodules (SMs), which are composed of half-bridge con-
verter cells fed by floating dc capacitors. There is no need for
high-voltage dc-link capacitors (or series-connected capacitors)
because the intrinsic capacitors of the cells perform these tasks,
which reduces the costs of the converter and increases its relia-
bility. Moreover, the high number of levels enables a significant
reduction in the device’s average switching frequency without
compromising the power quality [3]. Furthermore, the inductors
are included within each leg to protect the system during short
circuits. Due to the features of this topology, such as modular-
ity and scalability, the MMC is attractive for medium-voltage
drives, high-voltage direct current (HVDC) transmission, and
flexible ac transmission systems (FACTS) [4]–[7].
To date, the MMC has been presented in a few studies pub-
lished in the literature. The capacitor voltage-balancing control
is introduced in [8], where the pulsewidth modulation (PWM)
scheme is applied to MMCs based on the combination of aver-
aging and balancing control without any external circuit, and the
Manuscript received August 25, 2012; revised December 10, 2012; accepted
February 25, 2013. Date of current version July 18, 2013. This work was sup-
ported by the Department of Energy Technology, Aalborg University, Aalborg,
Denmark, and by the China Scholarship Council. Recommended for publication
by Associate Editor A. Mertens.
The authors are with the Department of Energy Technology, Aalborg Univer-
sity, Aalborg, 9220 Denmark (e-mail: fde@et.aau.dk; zch@et.aau.dk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2251426
0885-8993/$31.00 © 2013 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.
results are verified by simulation and experiment. The dynamic
performance of an MMC-based back-to-back HVDC system
under balanced and unbalanced grid conditions is investigated
in [9], where a phase disposition (PD) sinusoidal PWM (SPWM)
strategy, including a voltage-balancing method, for the opera-
tion of an MMC is also presented. A new PWM modulation
scheme is introduced for MMCs, and the semiconductor losses
and loss distribution are investigated in [10]. An efficient model-
ing method for MMCs in electromagnetic transient simulation
is proposed in [11]. A reduced switching-frequency voltage-
balancing algorithm is developed for MMCs, and a circulating
current-suppressing controller is proposed for the three-phase
MMC in [12]. The impact of sampling frequency on harmonic
distortion for MMCs is investigated in [13]. The inner energy
control of the MMC is discussed in [14]. The performance of
MMCs operated with various multicarrier SPWM techniques is
evaluated in [15].
In this paper, a capacitor voltage-balancing control method is
proposed for the MMC. The phase-shifted carrier-based PWM
(PSC-PWM) scheme, which has been introduced in several stud-
ies [16], [17], is used for the MMC and generates the high-
frequency component in the arm current. The capacitor voltage
balancing in the MMC can be achieved by assigning suitable
PWM pulses to the corresponding SMs. In the proposed voltage-
balancing control method, it is not necessary to measure the arm
current, which not only effectively reduces the number of the
sensors and decreases the costs but also simplifies the algorithm
for capacitor voltage-balancing control.
The paper is organized as follows. In Section II, the ba-
sic structure of the MMC is presented. Section III proposes
the capacitor voltage-balancing control method for the MMC.
Sections IV and V describe the system simulations and ex-
perimental tests, respectively, to show the effectiveness of the
proposed control method. Finally, Section VI presents the con-
clusions.
II. STRUCTURE OF THE MMC
Fig. 1(a) shows the diagram of the three-phase MMC, which is
composed of six arms. Each arm consists of n series-connected
SMs and an arm inductor Ls . The upper arm and the lower
arm in the same phase comprise a phase unit. Fig. 1(b) depicts
a scheme representation of the SM, which contains an insu-
lated gate bipolar transistor (IGBT) half-bridge that serves as a
switching element and a dc storage capacitor with a correspond-
ing voltage of Vc . The two switches (S1 and S2 ) in each SM are
controlled with complementary signals and produce two active
switching states that can connect or bypass the respective capac-
itor to the converter leg. Consequently, the output voltage Vsm of
DENG AND CHEN: CONTROL METHOD FOR VOLTAGE BALANCING IN MODULAR MULTILEVEL CONVERTERS 67

Fig. 1. (a) Block diagram of the three-phase MMC. (b) SM unit.

TABLE I
SM STATE

the SM can be determined based on the switching states, which

is shown in Table I. The SM state is defined as switched-on if S1
is switched ON and S2 is switched OFF. Here, the voltage Vsm
equals Vc . In contrast, the SM state is defined as switched-off
if S1 is switched OFF and S2 is switched ON. In this situation,
the Vsm is zero [9].
According to [12], the arm current in the MMC can be de-
scribed as
⎧ ij
⎪
⎨ iu j = + idiff j
2
, j = a, b, c (1)
⎪
⎩ i = − ij + i
lj diff j
2
Fig. 2. Block diagram of the PSC-PWM scheme for phase A.
where iu j and ilj are the upper arm current and the lower arm
current of phase j (j = a, b, c), respectively, ij the ac current of
phase j (j = a, b, c), and idiff j is the inner difference current
of phase j (j = a, b, c), which contains two parts and can be where Vdc is the dc-bus voltage. uu j and ulj are the total output
expressed as (2) [12], [18]. One part is the dc component, which voltage of the series-connected SMs in the upper and the lower
is one-third of the dc-link current idc /3. The other part is the arms of phase j (j = a, b, c), respectively.
circulating current i2f j of phase j (j = a, b, c)
iu j + ilj idc III. PROPOSED VOLTAGE-BALANCING CONTROL METHOD
idiff j = = + i2f j , j = a, b, c. (2)
2 3 A. Modulation Description
According to [19] and [20], the voltage relationship of the The PSC-PWM scheme is applied here [16], [17]. Each arm
MMC can be described as with n SMs requires n triangular carrier waves with a frequency
Vdc uu j + ulj didiff j
of fs , and each carrier wave is phase shifted by an angle of Δθ.
= + Ls , j = a, b, c (3) The Δθ lies between 0 and 2π/n. The phase-shifted angles θi
2 2 dt
68 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 1, JANUARY 2014

TABLE II
CAPACITOR STATE

Fig. 3. Block diagram of the proposed voltage-balancing control for each arm
of the MMC.

for the ith carrier wave War i can be defined as

θi = (i − 1) × Δθ, 1 ≤ i ≤ n. (4)
The reference signals for the SMs in the upper arm and in
the lower arm are −yx ref (t) and yx ref (t), respectively (x =
a, b, c). The n pulses S1 −Sn for the SMs in each arm can
be generated by comparing the corresponding reference signal
with the n phase-shifted carrier waves War 1 −War n . Due to
the PSC-PWM scheme for the MMC, a high-frequency current
component with the frequency of fs may be caused in each
arm, which will be discussed and used for the voltage-balancing Fig. 4. Simulated waveforms of the MMC with the proposed voltage-
control later. balancing control. (a) Line-to-line voltage V a b , V b c , and V c a . (b) Grid current
Fig. 2 shows the simulation waveforms for phase A (n = ia , ib , and ic . (c) Phase A arm current iu a , il a , and (iu a + il a )/2. (d) Capacitor
voltage of phase A.
3) under the PSC-PWM scheme with the assumption that the
frequency fs of the carrier wave is far higher than that of the
reference signal, and the capacitor voltages in each arm are the upper switches of SMla 1 –SMla 3 in the lower arm, whose
the same. The three triangular carrier waves War 1 , War 2 , and summation is Sl sum . Ssum is the sum of Su sum and Sl sum .
War 3 are considered for each arm, and each is shifted by an iu a and ila are the current in the upper armand the lower arm,
angle Δθ. ωs = 2πfs is the angle frequency of the carrier respectively. Combining (3) and Ssum , a high-frequency com-
wave. Su 11 , Su 21 , and Su 31 are, respectively, the pulses for ponent with the frequency fs in the arm current may be caused,
the upper switches of SMu a 1 –SMu a 3 in the upper arm, whose as shown in Fig. 2, which is used for the proposed voltage-
summation is Su sum . Sl 11 , Sl 21 , and Sl 31 are the pulses for balancing control.
DENG AND CHEN: CONTROL METHOD FOR VOLTAGE BALANCING IN MODULAR MULTILEVEL CONVERTERS 69

Fig. 5. (a) Arm current iu a under a phase-shifted angle of 2π/15. (b) Capacitor voltage in phase A under a phase-shifted angle of 2π/15.

Fig. 6. (a) Arm current iu a under a phase-shifted angle of 2π/12. (b) Capacitor voltage in phase A under a phase-shifted angle of 2π/12.

Fig. 7. (a) Arm current iu a under a phase-shifted angle of 2π/10. (b) Capacitor voltage in phase A under a phase-shifted angle of 2π/10.

B. High-Frequency Current Analysis Si can be analyzed in each period of 2π from (n – 1)Δθ/2+

To analyze the high-frequency component with the frequency (j – 1)2π to (n – 1)Δθ/2+ j2π (j = 1, 2, . . .), as shown in
of fs in each arm current, some assumptions are given as Fig. 2, which can be expressed as a Fourier series expansion as
follows: follows:
1) The carrier wave frequency fs is far higher than that of the ∞  
Vc Δθu 2Vc  m 1 mΔθu
reference wave. The widths of the n pulses for the upper vsmu i (t) = + (−1) sin
2π π m =1 m 2
arm SMs are assumed to be the same in each period of 2π,
and the phase-shifted angles between these pulses are the · cos[m(ωs t − (i − 1)Δθ)] (5)
same as Δθ, as shown in Fig. 2. Moreover, the widths of
the n pulses for the lower arm SMs are assumed to be the where Δθu is the pulsewidth in the upper arm, as shown in Fig. 2.
same in each period of 2π, and the phase-shifted angles The high-frequency voltage component with the frequency of
between these pulses are also the same as Δθ, as shown fs in (5) can be obtained as
in Fig. 2.  
2) The capacitor voltages in each arm are the same. 2Vc Δθu
vsmu fs i (t) = − sin cos[ωs t − (i − 1)Δθ)].
According to the aforementioned assumption, the output volt- π 2
age vsmu i (t) of the SM in the upper arm with the ith pulse (6)
70 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 1, JANUARY 2014

Fig. 8. THD of the upper arm current iu a . Fig. 9. Ratio of the high-frequency current with the frequency of fs to the
50 Hz fundamental current in the upper arm of phase A.

Expression vsmu fs sum (t), which is the summation of the

high-frequency voltage components with the frequency of fs in
the upper arm, can be presented as

n
Vsmu fs sum (t) = Vsmu fs i (ωs t)
i=1

2Vc Δθu sin((nΔθ)/2)

=− sin
π 2 sin Δθ/2
 
n−1
× cos ωs t − Δθ (7)
2
With the same method, the summation vsm l fs sum (t) of the
high-frequency voltage components with the frequency of fs in
the lower arm can be obtained as
2Vc Δθl sin((nΔθ)/2)
vsm l fs sum (t) =− sin
π 2 sin Δθ/2
 
n−1
cos ωs t − Δθ (8)
2
where Δθl is the pulsewidth in the lower arm, as shown in Fig. 2.
The voltage vfs sum (t) with the frequency of fs can be obtained
with the addition of vsmu fs sum (t) and vsm l fs sum (t)
 
4Vc sin((nΔθ)/2) Δθu − Δθl
vfs sum (t) = − cos
π sin Δθ/2 4
  Fig. 10. Block diagram of the experimental circuit.
n−1
· cos ωs t − Δθ . (9)
2

According to (9), the voltage vfs sum (t) may be caused in

The high-frequency current ifs sum (t) leads the vfs sum (t) by
the MMC under the PSC-PWM scheme. The peak value of the
π/2, as shown in Fig. 2. This means that the zero-crossing point
vfs sum (t) appears at the phase angle of (n – 1)Δθ/2 + (2j –
of the caused high-frequency current with the frequency of fs
1)π (j = 1, 2, . . .), which is the middle point of each period,
occurs at the phase angle of (n – 1)Δθ/2 + (2j – 1)π (j = 1, 2,
as shown in Fig. 2. According to (3) and (9), a high-frequency
. . .), which is the middle point of each period. The peak value
current ifs sum (t) with a frequency of fs may also be caused,
of the high-frequency current with the frequency of fs appears
which can be expressed as follows:
  at approximately π/2 in each period, as shown in Fig. 2.
2Vc sin((nΔθ)/2) Δθu − Δθl
ifs sum (t) = cos
πωs Ls sin Δθ/2 4 C. Capacitor Voltage Analysis
 
n−1 π The capacitor voltage in each SM is related to its switching
· cos ωs t − Δθ − . (10)
2 2 stage and the direction of the arm current, as shown in Table II.
DENG AND CHEN: CONTROL METHOD FOR VOLTAGE BALANCING IN MODULAR MULTILEVEL CONVERTERS
Fig. 11. Measured experimental waveforms, including voltage u a b
(100 V/div) and current ia b (5 A/div). (a) Δθ = 2π/6. (b) Δθ = 2π/4.2.
The time base is 4 ms/div.
In principle, if the arm current iu (or il ) is positive, as shown in
Fig. 1, and the SM is switched on, the corresponding capacitor
would be charged and its voltage increased. On the contrary,
the capacitor would be discharged and its voltage reduced if the
arm current iu (or il ) is negative and the SM is switched ON. In
contrast, if the SM is switched OFF, which means the capacitor
is bypassed, the capacitor voltage remains unchanged.
Under the PSC-PWM scheme, the capacitor state including
charge and discharge can be analyzed within each period of 2π,
as shown in Fig. 2. Due to the aforementioned assumption that
the widths of the n pulses for the SMs in the upper arm are the
same in each period, the capacitor voltage will be decided by
the arm current during the different on-times of the pulse.
1) Positive arm current (iu > 0): The capacitors in the upper
arm may absorb power and be charged when the arm cur-
rent iu > 0. Because the peak value of the high-frequency
current with a frequency of fs appears at π/2 in each pe-
riod, in terms of the n pulses S1 −Sn , it can be observed
that the pulse with its middle point close to π/2 may make
the SM absorb more power and cause the capacitor volt-
71
age to be higher than the pulse with its middle point far
from π/2.
2) Negative arm current (iu < 0): The capacitors in the upper
arm may emit power and be discharged if the arm current
iu < 0. Because the peak value of the high-frequency
current with the frequency of fs appears at π/2 in each
period, in terms of the n pulses S1 −Sn , it can be observed
that the pulse with its middle point close to π/2 may make
the SM emit less power and cause the capacitor voltage
to be higher than the pulse with its middle point far from
π/2.
Based on the aforementioned analysis, regardless of the di-
rection of the arm current, the SM with the pulse whose middle
point is close to π/2 may absorb more power or emit less power,
and its corresponding voltage tends to be higher in comparison
with the SM with the pulse whose middle point is far away from
π/2. The analysis for the lower arm SM capacitor voltage is the
same as that for the upper arm SM capacitor voltage, which is
not repeated here.
D. Proposed Voltage-Balancing Control
According to the previous analysis, a voltage-balancing con-
trol method is proposed, as shown in Fig. 3, which is imple-
mented in each arm. With the PSC-PWM scheme, the n carrier
waves War 1 −War n with the phase-shifted angle Δθ are com-
pared with the reference signal and used to generate n phase-
shifted pulses S1 −Sn .
To achieve the capacitor voltage-balancing task of the SMs
in each arm, the capacitor voltage uc1 −ucn in each arm is
monitored in real time and sampled at the control frequency
fs and then sorted in ascending order. The proposed voltage-
balancing control is implemented in each period of 2π from
(n – 1)Δθ/2 + (j – 1)2π to (n – 1)Δθ/2 + j2π (j = 1, 2, . . .),
as shown in Fig. 2.
Based on the previous capacitor voltage analysis, if the capac-
itor voltage is low, the pulse with its middle point close to π/2
may be assigned to the SM. Consequently, the corresponding
SM capacitor will absorb more power when the arm current is
positive and the capacitor voltage increases more or emit less
power when the arm current is negative and the capacitor volt-
age decreases less. In contrast, if the capacitor voltage is high,
the pulse with its middle point far from π/2 may be assigned
to the SM. Consequently, the corresponding SM capacitor will
absorb less power when the arm current is positive and the ca-
pacitor voltage increases less or emit more power when the arm
current is negative and the capacitor voltage decreases more. As
a consequence, the pulses S1 −Sn are sequenced in ascending
order according to the distances between the middle point of
the pulses and π/2. Actually, the middle point of the pulse is
also the time point of the minimum value of the carrier wave,
as shown in Fig. 2. Finally, the pulses Sd1 −Sdn are obtained as
shown in Fig. 3, in which the distance between the middle point
of Sd1 and π/2 is minimum and the distance between the middle
point of Sdn and π/2 is maximum. The SMs in the arm are also
ordered according to the capacitor voltage in ascending order
72
Fig. 12. Measured experimental waveforms, including current iu a (5 A/div), current il a (5 A/div), and current ia b (5 A/div). (a) Δθ = 2π/7. (b) Δθ = 2π/6.
(c) Δθ = 2π/5. (d) Δθ = 2π/4.2. The time base is 4 ms/div.
and driven with the pulses in a sequence from Sd1 to Sdn , which
can effectively ensure capacitor voltage balancing in each arm.
IV. SIMULATION STUDIES
To verify the proposed voltage-balancing control method, a
three-phase MMC system is modeled with the professional tool
PSCAD/EMTDC, as shown in Fig. 1. The system parameters
are shown in the Appendix.
A. Verification of the Proposed Voltage-Balancing Control
The performance of the three-phase MMC under the pro-
posed voltage-balancing control method is shown in Fig. 4, in
which the phase-shifted angle Δθ is set as 2π/10.5. The three-
phase voltage and current waveforms of the MMC are shown in
Fig. 4(a) and (b). Here, the system active power is 20 MW and
the reactive power is 0. The upper arm current iu a , the lower
arm current ila , and the (iu a + ila )/2 are shown in Fig. 4(c), in
which the total harmonic distortion (THD) of the arm current is
approximate 0.55% and the ratio of the high-frequency current
with the frequency of fs to the 50 Hz fundamental current is
0.45%. The circulating current suppression method introduced
in [12] is used in the MMC. Hence, the (iu a + ila )/2 only con-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 1, JANUARY 2014
tains a dc component. Fig. 4(d) shows the upper arm capacitor
voltage ucau 1 −ucau 10 and the lower arm capacitor voltage
ucal 1 −ucal 10 . The capacitor voltages of the MMC are kept
balanced with the proposed control method.
B. High-Frequency Current and Stability Evaluation
The high-frequency component of the arm current and the
stability of the capacitor voltage are investigated with the differ-
ent phase-shifted angles. Figs. 5–7 show the upper arm current
iu a and the capacitor voltage in phase A under the phase-shifted
angles Δθ as 2π/15, 2π/12, and 2π/10, respectively. The high-
frequency current with the frequency of fs appears in the iu a
when Δθ is 2π/15 and 2π/12, which accounts for 3.85% and
1.79% in the 50 Hz fundamental current, respectively. Under
the proposed voltage-balancing control, the capacitor voltage
balancing can be effectively maintained when Δθ is 2π/15 and
2π/12, as shown in Figs. 5(b) and 6(b). When Δθ is 2π/10,
the high-frequency current with the frequency of fs accounts
for 0.01% in the 50 Hz fundamental current iu a , which is quite
small and can be nearly neglected, as shown in Fig. 7(a). As a
consequence, the capacitor voltage balancing cannot be main-
tained, as shown in Fig. 7(b).
DENG AND CHEN: CONTROL METHOD FOR VOLTAGE BALANCING IN MODULAR MULTILEVEL CONVERTERS 73

Fig. 13. Measured experimental waveforms, including current iu a (2 A/div), current il a (2 A/div), and voltage u m n (100 V/div). (a) Δθ = 2π/7.
(b) Δθ = 2π/6. (c) Δθ = 2π/5. (d) Δθ = 2π/4.2. The time base is 40 μs/div.

The performances of the MMC under the different phase-
shifted angles, including 2π/60, 2π/30, 2π/20, 2π/15, 2π/12,
and 2π/10, are studied, and the THD of the arm current under
the different phase-shifted angles is shown in Fig. 8; the larger
the phase-shifted angle, the smaller the THD of the arm cur-
rent. Moreover, the ratio of the high-frequency current with the
frequency of fs to the 50 Hz fundamental current is shown in
Fig. 9. Along with the increase in the phase-shifted angle, the
current component with the frequency of fs in the arm current
will be decreased and will be nearly zero when the phase-shifted
angle is 2π/10.
V. EXPERIMENTAL STUDY
To confirm the proposed control method, an experiment study
was conducted. Fig. 10 shows the experimental circuit, in which
each arm contains four SMs. Two dc power supplies (SM
400-AR-8) in parallel with the resistor load Rr are connected in
series to support the dc-link voltage. The switches and diodes
in each cell are the standard IXFK48N60P power MOSFETs.
The carrier wave frequency fs is set as 5 kHz. The experimental
system parameters are shown in the Appendix.
The proposed control method is tested with a few phase-
shifted angles Δθ, including 2π/7, 2π/6, 2π/5, and 2π/4.2.
Fig. 11 shows the voltage uab and the current iab . The cur-
rents iu a , ila , and iab are shown in Fig. 12. Along with the
increase of the phase-shifted angle Δθ, the fluctuation of the
high-frequency components in the arm current—iu a and ila —
will be reduced. A high-frequency 5 kHz current is caused in
each arm, as shown in Fig. 13. With the proposed control, the
capacitor voltages in the MMC are kept balanced, as shown in
Figs. 14 and 15.
Figs. 16 and 17 show experimental waveforms when the out-
put voltage uab was stepped up and stepped down with Δθ equal
to 2π/6 and 2π/4.2, respectively, where the capacitor voltages
were kept balanced.
Fig. 18 shows experimental waveforms with and without the
proposed control. During the period without the proposed con-
trol, cell11, cell12, cell13, and cell14 are driven with the pulses
Sd1 , Sd2 , Sd3 , and Sd4 , respectively, as shown in Fig. 3. As
a consequence, the capacitor voltages ucu 1 and ucu 2 will be
increased gradually, and the voltages ucu 3 and ucu 4 will be re-
duced gradually, as shown in Fig. 18. After the proposed control
is enabled again, the capacitor voltage is kept balanced again,
as shown in Fig. 18.
74 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 1, JANUARY 2014

Fig. 14. Measured experimental waveforms under Δθ = 2π/6. (a) Voltage u c a u 1 (10 V/div), u c a u 2 (10 V/div), u c a l 1 (10 V/div), and u c a l 2 (10 V/div). (b)
Voltage u c a u 1 −4 (10 V/div). (c) Voltage u c a l 1 −4 (10 V/div). (d) Voltage u c a u 1 (10 V/div), u c b u 1 (10 V/div), u c a l 1 (10 V/div), and u c b l 1 (10 V/div). The time
base is 4 ms/div.

Fig. 15. Measured experimental waveforms under Δθ = 2π/4.2. (a) Voltage u c a u 1 (10 V/div), u c a u 2 (10 V/div), u c a l 1 (10 V/div), and u c a l 2 (10 V/div).
(b) Voltage u c a u 1 −4 (10 V/div). (c) Voltage u c a l 1 −4 (10 V/div). (d) Voltage u c a u 1 (10 V/div), u c b u 1 (10 V/div), u c a l 1 (10 V/div), and u c b l 1 (10 V/div). The
time base is 4 ms/div.
DENG AND CHEN: CONTROL METHOD FOR VOLTAGE BALANCING IN MODULAR MULTILEVEL CONVERTERS 75

Fig. 16. Measured experimental waveforms under Δθ = 2π/6, including voltage u c a u 1 (10 V/div), u c a l 1 (10 V/div), u a b (250 V/div), and current ia b (5 A/div).
(a) The output voltage u a b was stepped up. (b) The output voltage u a b was stepped down. The time base is 10 ms/div.

Fig. 17. Measured experimental waveforms under Δθ = 2π/4.2, including voltage u c a u 1 (10 V/div), u c a l 1 (10 V/div), u a b (250 V/div), and current ia b
(5 A/div). (a) Output voltage u a b was stepped up. (b) Output voltage u a b was stepped down. The time base is 10 ms/div.

VI. CONCLUSION

In this paper, a voltage-balancing control method is proposed

Fig. 18. Measured experimental waveforms, including voltage u c a u 1
(10 V/div), u c a u 2 (10 V/div), u c a u 3 (10 V/div), and u c a u 4 (10 V/div) un-
der Δθ = 2π/6. The time base is 400 ms/div.
for the MMC. The PSC-PWM scheme is applied for the MMC,
and a high-frequency component in the arm current is gener-
ated for the voltage-balancing control. It is not necessary to
measure the current in each arm with the proposed voltage-
balancing control, which omits the current sensors, reduces the
costs, and simplifies the voltage-balancing control algorithm.
The high-frequency component in the arm current is analyzed.
Based on the analysis, a voltage-balancing control method is
presented that can be achieved by assigning suitable pulses to
the different SMs of the MMC. An MMC system is modeled
and simulated with PSCAD/EMTDC, and a small-scale MMC
prototype was built and tested in the laboratory. The results show
the effectiveness of the proposed voltage-balancing control
method.
76
APPENDIX
See Tables III and IV.
TABLE III
PARAMETERS OF THE THREE-PHASE MMC SYSTEM
TABLE IV
EXPERIMENTAL CIRCUIT PARAMETERS
REFERENCES
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Fujin Deng (S’10–M’13) received the B.Eng. degree
in electrical engineering from China University of
Mining and Technology, Jiangsu, China, in 2005, the
M.Sc. degree in electrical engineering from Shanghai
Jiao Tong University, Shanghai, China, in 2008, and
the Ph.D. degree in energy technology from the De-
partment of Energy Technology, Aalborg University,
Aalborg, Denmark, in 2012.
Currently, he is a Postdoctoral Researcher in the
Department of Energy Technology, Aalborg Univer-
sity, Aalborg, Denmark. His main research interests
include wind power generation, multilevel converter, DC grid, control of per-
manent magnet synchronous generator, high-voltage direct-current (HVDC)
technology, and offshore wind farm-power systems dynamics.
Zhe Chen (M’95–SM’98) received the B.Eng. and
M.Sc. degrees from the Northeast China Institute of
Electric Power Engineering, Jilin City, China, and
the Ph.D. degree from the University of Durham,
Durham, U.K.
He is currently a Full Professor with the Depart-
ment of Energy Technology, Aalborg University, Aal-
borg, Denmark, where he is the Leader of the Wind
Power System Research program. He is the Danish
Principal Investigator of Wind Energy of Sino-Danish
Centre for Education and Research. His current re-
search interests include power systems, power electronics, electric machines,
wind energy, and modern power systems. He has authored or coauthored more
than 320 publications in his technical field.
Dr. Chen is an Associate Editor (Renewable Energy) of the IEEE TRANSAC-
TIONS ON POWER ELECTRONICS, a Fellow of the Institution of Engineering and
Technology (London, U.K.), and a Chartered Engineer in the U.K.