Advanced Digital System Design

Question Bank for Sessional Exam

(2017-18)
 Questions in BOLD only are meant for Sessional Exam preparation. Other questions are important for
University Exam. Also prepare section contains questions not asked in university exam, but may be asked
this year. Remember that Question Bank is for the weaklings. Challenges are for the Tough Ones.

UNIT – 1

1. Explain VHDL Development flow with suitable flow chart (7)

2. Explain the Development tasks pertaining to design of digital systems. (7)
3. Discuss various levels of abstraction in VHDL (7)
4. Give brief history of VHDL and list its advantages / What are the advantages of VHDL over other
conventional programming languages? (7)
5. What do you mean by Modeling Styles? What are different modeling styles used in VHDL? Explain each in
detail. / Describe with syntax the different architectures used in VHDL (7)
6. Explain the different design units used in VHDL with their syntax in brief (7)
7. Explain concurrency in VHDL with suitable example (3)
8. Explain different approaches in VHDL (5)

Also prepare for University Exam:

9. Explain the device technologies in brief
10. Explain the system representation (views) of a digital system with diagram

UNIT - 2
11. Explain different data objects in VHDL with suitable examples (7)
12. Create a physical data type, Capacitance ranging from µF (Microfarad) to MF (Megafarad) (7)
13. Write short notes on: (i) Entity (ii) Architecture (iii) Package (iv) Configuration (12)
14. Explain various data types in VHDL. / How are scalar data types classified? Explain real and integer data
type in brief (8)
15. Differentiate between conditional and selected signal assignment statements / Explain the
difference between selected signal assignment and conditional signal assignment statement with
example of 4 to 1 MUX (7)
16. All codes pertaining to simple, conditional (when-else) and selected (with-select) signal assignment
statement (Dataflow), case statement, if-then-else statement (Behavioral) from ADSD CODE BANK

UNIT - 3
17. What is subprogram? Explain 'Function' and 'Procedure' with their syntax. (7)
18. What do you mean by Port mapping? What are the types? Explain each with syntax (6)
19. Explain Predefined Attributes with examples (7)
20. All the codes pertaining to Test-Bench from ADSD CODE BANK (8)
21. All the codes pertaining to Generate statement from ADSD CODE BANK (8)
22. All the codes pertaining to Component Declaration & Component Instantiation (Structural) from
ADSD CODE BANK (8)

Also Prepare for University Exam:

23. Explain Generic with suitable example
24. Explain IEEE standard logic library
25. Explain File I/O
 UNIT - 4
26. Write the differences between Moore and Mealy circuits. (3)
27. Design a sequence detector for 0101 with mealy state machine and implement it with D flip-flop
and write a VHDL code for the same. (15)
28. Design and Write a VHDL code for 1010 sequence using Moore state machine. (Use overlapping)
Also write Test-bench for the same (15)
29. Design a sequence detector to detect the sequence '111' using Moore machine. Use flip flop. Also
write the VHDL code for it. (15)
30. Design a sequence detector to detect the sequence of '1010' using Mealy machine. Use JK Flip-Flop.
Also write the VHDL code for it. (15)

Also prepare for University Exam

31. All design problems on Mealy and Moore FSM for D-Flip Flop and JK Flip-Flop

UNIT – 5
32. Define synthesis in VHDL? What are the steps of synthesis / What is Synthesis in VHDL? Explain synthesis
design flow in VHDL (7)
33. Write short note on pipelining in VHDL (7)
34. Write a short note on "Partitioning for synthesis" (6)
35. Explain power analysis of FPGA based system (8)
36. Explain efficient coding style used for HDL synthesis (6)
37. Write short note on Optimizing Arithmetic Expression (7)
38. Explain timing analysis of logic circuits (4)
39. Explain the term Resource Sharing (5)

UNIT – 6
40. A combinational circuit is defined by the function.
F1 (A, B, C) = (3, 5, 6, 7)
F2 (A, B, C) = (0, 2, 4, 7)
Implement the circuit with a PLA having three inputs, four product terms and two outputs (8)
41. Implement the following function using PLA :
F1 (A, B, C, D) = ∑m (0, 1, 4, 5, 9, 10, 11)
F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 5, 8, 9, 10, 11)
F3 (A, B, C, D) = ∑m (4, 5, 6, 7, 8, 9) (8)
42. Design and Write VHDL code for 4-bit Barrel shifter (7)
43. Write a short note on XC4000 series FPGA / Explain with suitable block diagram Xilinx 4000 series FPGA
(7)
44. Explain place, map and route process in FPGA based system (6)
45. Write a VHDL code for 3x3 binary multiplier using structural style (7)
46. Write a VHDL code for 4-bit ALU (7)
47. Explain the architecture of FPGA with neat diagram (6)
48. Design a 4 x 4 Keyboard Scanner and write a VHDL code for the same (7)

Also prepare for University Exam:

49. Write short notes on FPGA, CPLD, PLA and PAL
50. Explain structure and operation of Xilinx CPLD

NOTE: All Codes given in ADSD CODE BANK must be thoroughly practiced.