EMBEDDED SYSTEM FOR

DISASTER MANAGEMENT

K.S.JANANI
R.AATHILAKSHMI
ABSTRACT:

This paper describes design of a critical satellite receiver

for real time satellite-based voice and data messaging system
suitable for Disaster Management Solutions. The receiver is
used for indicating the cyclone warning message in local
languages to remote coastal villages from regional weather
office using satellite backbone. Cyclone warning messages are
meant for some specific remote location and broadcast warning
message contains coded headers followed by voice or data
files. The satellite receiver has been designed to demodulate L-
band signal and decode the packetized data from the
demodulated output. The receiver will play the audio only if its
embedded algorithm matches the decoded data with its own
identification no.

INTRODUCTION
Information about the cyclone, such as its intensity, direction of
movement, areas likely to be affected, time of reaching the coast etc. are
prepared at the Area Cyclone Warning Centre (ACWC). Based on this the
warning messages are announced at regular intervals from regional weather
office called ACWC and these messages are transmitted in broadcast mode in S-
band by satellite. Digital Cyclone Warning Dissemination Receivers (DCWDS) are
installed at cyclone-prone coastal villages which would receive the broadcast
message and play the audio in respective local languages.

DCWDS Receiver is an integrated satellite receiver providing a digital

system to capture L-band data (950-1450 MHz) and demodulate Cyclone
Warning Messages meant for it.

The receiver also generates acknowledgement messages and sends the

same to Network Management System (NMS) of ACWC through reporting
terminal attached to the system. The receiver also keeps the warning reception
history for the messages received by the DCWDS receiver.

DESCRIPTION OF THE RECIEVER

The receiver is responsible for Demodulation, Header Detection and
Processing from the bit-stream received, Message Reformation and
Acknowledgement Packet Formation and Transmission. Brief descriptions of all
the modules are given below.

HARDWARE DESCRIPTION
 Fig.1: Block diagram of DCWDS Receiver

DEMODULATOR
For demodulation of the receiver we have used an imported L-band, PCI
format, SPL make and SBR 8192 demodulator card. The wide range of L band
input (950 to 2050 MHz) minimizes the number of LNBCs required for full
satellite coverage. The function of Low Noise Block Converter (LNBC) is to
amplify the low level satellite downlink transmission to such a level so that it can
be demodulated. Demodulator card receives the L-Band RF signal from Low
Noise Block Converter (LNBC). With power on, default parameters are
downloaded from micro-controller to demodulator for demodulation.
Demodulator extracts Digital data and clock from RF signal and communicates
the same to micro-controller.
The basic functional operation of SBR 8192 is that the demodulator is
configured, controlled and operated via its serial interface’s CONTROL and
STATUS signal lines. μC sends serial commands to set RF carrier frequency,
modulation type, data rate etc. Other serial commands permit enabling /
disabling the descrambler and differential decoder functions. Once configured by
serial commands, the demodulator itself manages the entire signal acquisition
process by its own processor.
 Demodulator receives L band input at RF down converter, which down
converts the signal to a 80 MHz IF. IF signal is amplified by a VGA, and the
amplified signal passes through a wideband SAW for further reduction of its BW
to less than the sampling frequency. The IF is amplified and sampled by an ADC.

The digitized IF is routed through digital down converter and demodulator

ASIC to process 8-bit digital words. The data and the clock outputs of ASIC are
fed to VITERBI decoder to provide the decoded bit stream. The decoder performs
selectable descrambling and differential decoding to provide the resulting data
and clock. The standard receiver can operate either with 1/2, 3/4 and 7/8 rate
DVB Viterbi error correction.

MICROCONTROLLER
Microcontroller PCB is the master control for the DCWDS Receiver like a
motherboard in a Personal Computer. ATMEL 89C52 eight bit micro-controller
has been used in our development.

Microcontroller PCB has been shown in Fig

The following block diagram of the microcontroller describes in detailed
version of our aim of this paper. This illustrates the role of microprocessor in the
disaster management. Its software description and its way of use are as follows.
The diagram shows the parts (i.e.) detection data storage, main unit for
processing and finally (i.e.) in the right hand side is placed with an output
feeder. The left hand side functions as a input acceptor (initial disasters warning
message acceptor) and at middle it do’s some procession and finally at right
hand side it gives as message (action to be done at the time of disaster).
SOFTWARE DESCRIPTION
SOFTWARE DESCRIPTION
The finite state machine diagram for unique word detection and its
explanation are given as follows below in Fig.
 Fig. 3: The Finite State Machine Diagram for UW Detection

HEADER PROCESSING

Described below in short various functional modules of the software.

It is a very important function of the receiver. The NMS at ACWC generates
unique headers for individual locations for which the warning message is meant.
Each header is of 36 Bytes length and consists of various information, viz.,
Station Identification, Cyclone Number Identification, Type of Message (Voice or
Text) Identification, Date, Time etc. For group selection of target receivers by
the NMS, multiple headers are concatenated before the warning message. All
these headers begin with a Unique Word pattern of 4 Bytes length. This Unique
Word pattern is repeated three times in each header and thereafter rest of data
is packetized. The embedded software developed for DCWDS Receiver scans the
incoming data stream in real time and looks for two consecutive Unique Words.
If detected, the software checks up various identification codes within the header
and if found matching with its embedded preset values, if the message is audio,
MPEG audio decoder, which is on-board, is enabled and the decoded voice
message is played on ampli-receiver. If data is not voice, it is routed to RS 422 port for
display

ACKNOWLEDGEMENT PACKET FORMATION AND

TRANSMISSION
It is another feature of the DCWDS Receiver which enables Dynamic
Status Monitoring and Remote Diagnosis by NMS at ACWC. As soon as a
message is received and played by the receiver, an eleven bytes long
Acknowledgement Data Packet is formed by the Microcontroller with various
information, viz., Time, Date etc. with various identification references for the
receiver. This acknowledgement data is transmitted to the NMS at ACWC by a
short messaging terminal attached to the DCWDS Receiver. The Microcontroller
PCB communicates to the short messaging terminal serially at 600 bps.

WARNING RECEPTION HISTORY

It is logged by the Microcontroller in Cyclic Memory. This information may
be referred by administrators for investigation and records.

The entire software development has been done through assembly

language. The HEX code generated by assembler has been embedded in the chip
through suitable EPROM programmer equipment. The entire software has been
tested and validated through soft simulation before embedding into the chip.

M peg DECODER
A single-chip MPEG layer 3 audio decoder (MICRONAS 3507D) has been
used for playback applications. The MAS 3507D decoding block accepts
compressed digital data stream as serial bit streams and provide serial output of
decompressed audio. The chip uses a DSP engine with flexible digital interfaces
for serial audio data input and output. In addition to the signal processing
function the IC incorporates a high-performance on chip stereo D/A converter,
headphone amplifiers and two DC/DC converters. The IC provides a true ‘ALL-
IN-ONE’ solution that is ideally suited for high optimized memory based portable
music players with integrated speech decoding function. The chip is driven by a
single crystal –controlled clock with a frequency of 18.432 MHz and has been
designed for minimal power dissipation.
In MPEG 1, three hierarchical layers of compression have been
standardized. The most sophisticated and complex, layer 3, allows compression
rates of approximately 12:1 for mono and stereo signals while still maintaining
CD audio quality. An MPEG audio file is built up from smaller parts called frames.
Generally frames are independent items. Each frame has its own header and
audio information. There is no file header. The frame header is constituted by
first 32 bits in frame.

TESTING METHODOLOGY
The developed receiver has been tested with the help of Test Set-up as
shown in Fig. The header appended by MPEG audio file is generated by the
simulator software developed for this purpose and the same is sent to satellite
modem through synchronous serial PCB fixed onto the ISA slot of the computer.
The satellite modem receives carrier frequency input from the Microwave Signal
Generator as shown in the figure. The output of the Modem is directly connected
to the RF Input port of the DCWDS Receiver. As soon as data is sent to the
Modem, depending on the content of the header selected, audio is played by the
receiver. Audio port is not enabled if there is a mismatch of specific byte location
content within header data stream.

All the modules of the receiver have been tested individually for checking
its proper functionality. Methodology followed for testing of the modules and the
systems are given below.
MICROCONTROLLER CARD TESTING

Appropriate data stream is being fed to the board from the simulator
software developed for this purpose. The microcontroller PCB processes the
incoming data as per the software strategy and process the header and other
data elements packetized therein. Output bit patterns are monitored using logic
analyzers and digital storage oscilloscopes for checking propriety of operations.
Also the output of the microcontroller may be connected to MPEG decoder for
testing audio output.

MPEG Decoder Testing

The MPEG decoder circuit made of Micronas chip

may be tested by pumping the data from simulation software to the decoder
which will shed off the header portion and play the MPEG voice through the
speaker.

Environmental Test Cycles for Receiver

 The DCWDS receiver developed by us is tested in different environmental
conditions, viz., cold condition (0 0 C), at high temperature (50 0 C) and at 95%
RH non-condensing humid condition. For carrying out testing of the system 2.0
GHz signal source of pulse type (because the modulation is of BPSK type) is
used in addition to satellite modem, RF cable and other accessories.
In all environmental conditions as described above, the system performs
perfectly.

CONCLUSION
 The DCWDS Receiver has been specifically developed for nation-wide
Cyclone Warning System. Similar system may be used for warning and
mitigation of other natural calamities, viz., Flood, Earthquake etc.