AE-1/AE/EDC Prof.

FAIZ RANGARI Exam Questions [EQ]

-8976530729

Module 1: Diodes and its Applications

June
2015

1. Compare Clipper and Clamper Circuits. 05

Dec 2014

1. Write down current equation of Diode and explain significance of 04

each parameters.
2. Draw a required diode clamper circuit to generate the output V o
to from the input V1 as shown in the figure, If
i. Vϒ= 0V
ii. Vϒ=0.7V where Vϒ is cutin voltage of diode.

10

3. Write short note on construction and operation of photodiode. 05

June
2014

1. Explain effect of temperature on characteristics of PN junction 04

diode.
2. Write short note on series and shunt clippers. 07

3. Write short on construction and operation of varactor diode. 07

Dec 2013

1. Draw switching characteristics of a diode and explain reverse 04

recovery time. Faiz Rangari - 8976530729
2.

04

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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Obtain output for the clipper shown in the figure. If a sine wave
of 15sinwt is applied as an input. Assume practical diode with
suitable cutin voltage.

3. Write short note on small signal model of diode. 05

4. Write short note on Construction and operation of schottkey 05

diode.

Module 2: Field Effect Transistors

June Faiz Rangari - 8976530729
2015

1. Compare Depletion and Enhancement type MOSFET. 05

2. Explain the basic operation and characteristics of n-channel 10

enhancement type MOSFET.
3. Write short note on Energy Band diagram of MOS capacitor. 05

Dec
2014

1. Explain the working of n-channel EMOSFET with the help of

output characteristics, showing clearly effect of channel length 10
modulation. Give equation of drain current in linear and
saturation region along with conditions.
2. Write short note on MOS capacitor. 05

June
2014

1. Draw and explain energy band diagram of MOS capacitor in 10

accumulation, depletion and inversion region.
2. Write short note in MOSFET operation. 07

Dec
2013

1. Draw energy band diagram of MOS capacitor in accumulation, 04

depletion and inversion region for p-substrate.
2. Write short note on regions of operation of FET. 05

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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June
2013

1. Explain EMOSFET. 05

2. Explain with the help of neat diagram the structure of a N-

Channel FET, and its volt-ampere characteristics. In what way it 10
is different from BJT.
Dec
2012

1. Explain graphical determination of FET parameters. 05

2. Explain transfer characteristics of JFET. 05

Module 3: DC Analysis of Transistor Circuits

June 2015

1. Transistor is current controlled device while FET is voltage 05

controlled device. Justify.
2. Define Stability factor. Derive the equation for Stability factor.
State which biasing technique is more suitable. Justify your 10
answer.
3. For a NPN transistor in CE mode voltage divider configuration
determine Vc and Vb. Given Vcc= +20V, VEE= -20V, R1= 8.2KΩ,R2= 10
2.2 KΩ, Rc= 2.7 KΩ, RE= 1.8 KΩ, C1=C2= 10F and β= 120.
4. Write short note on Biasing of JFET for Zero Temperature Drift. 05

5. Write short note on DC load line and significance of Q point. 05

6. Determine IDQ, VGSQ, VD and VS for the network shown below.

10

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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Dec 2014

1. The PNP transistor shown on figure has β= 50. Find the value of
Rc to obtain Vc= +5V. What happen when transistor is replaced
with another transistor having β= 100.

04

Faiz Rangari - 8976530729

2. Why Common Collector amplifier is used as buffer? Why Buffers 04

are required.
3. For the circuit shown on figure. Find IDS and VDS if VRS= 1.5V.

04

4. Design JFET circuit with voltage divider biasing as shown in

figure with JFET parameters IDSS= 12mA, VP= -3.5V and λ= 0. Let
R1+R2= 100K, IDSQ= 5mA and VDSQ= 5V.

10

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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5. For the circuit shown in figure, assume β=100. 10

i. Find thevenin’s equivalent voltage Vth and resistance
Rth for base circuit.
ii. Determine ICQ and VCEQ

6. What are different biasing techniques used to bias D-MOSFET

and E-MOSFET. Explain with the help of appropriate circuit 10
diagrams.
June 2014

1. Find RB and Rc for the circuit shown to obtain VCE= 5V and Ic= 04
2mA
2. In n-channel MOSFET VDS= 5V, VGS= 5V, VBS= 0, W=10m,
04
L=5m, k’n= 100mA/V2 and VTO= 1V. Calculate its drain current
for channel length modulation factor λ of 0 and 0.25V-1.
3. Differentiate between BJT and MOSFET. 04

4. Find ICQ and VCEQ for the circuit shown in figure if β=100.

10

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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5. The JFET shown in the figure has parameters IDSS= 8mA and Vp=
-4V. Determine VG, IDSQ, VDSQ and VGSQ.

10

Dec 2013

1.

04

Faiz Rangari - 8976530729

Draw the DC load line for the above circuit.

2. Obtain IDQ , VDSQ, VGSQ graphically.

08

3. Derive the expression for Threshold voltage foe Enhancement 10

type N-channel MOSFET.
4.

10

Determine IB, Ic, VCE, and VBE and also SICO for the biasing circuit

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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shown in figure.

5. Explain graphical method to obtain parameters of CE 10

configuration.
6. Calculate IDQ , VDSQ, VGSQ

05

June
2013

1.

10
For the circuit shown in the figure the JFET parameters are I DSS=
5mA, Vp= -4V

Determine the following with ID= 2mA and VDS= 6V

i. RD
ii. Rs
iii. VD
iv. Vs
v. VRD

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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2. A CE BJT amplifier is shown in the figure with VCE= 12V, Ic=

2mA, Stability factor 5.1, Vcc= 24V, VBE= 0.7V, β= 50 and Rc=
4.7KΩ.
Determine the value of resistors RE, R1 and R2 (Hint: R2= 0.1βRE)

10

3.

10

For the network of figure with RD= 2KΩ, RG= 10MΩ and
VDD=12V.

Determine the following

i. IDQ
ii. VDSQ

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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Dec 2012

1. Explain BJT as a switch. 05

2. Discuss using the concept of load line superimposed on the

transistor characteristics. How a simple CE circuit can amplify a 10
time varying signal.

3. The following parameters are obtained from certain JFET

datasheet: VGSoff= -8V and IDSS= 5mA. Determine the values of ID,
10
for each value of VGS ranging from 0 to -8 Vin 1V steps. Plot the
transfer characteristics curve for the same data.

4. Explain output characteristics of CE BJT voltage amplifier. 05

Module 4: Small Signal Analysis of BJT Amplifiers

June
2015

1. Derive the equations for Av, Ai, Ri and Ro for a NPN transistor in 10
CE mode voltage divider bias configuration with RE unbypassed.
2. For the network given below determine Zi, Zo and Av.

10

3. Determine Zi, Zo and Av for the circuit shown below.

10

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4. Write short note on Small signal equivalent circuit of CC 05

amplifier.
Dec 2014

1. Draw circuit diagram of CE amplifier with voltage divider bias

with bypassed emitter resistance and derive expression for
voltage gain, current gain, input resistance and output resistance 10
using Hybrid-π model which includes early effect.

2. Write short note on Hybrid-π model of BJT. 05

3. Write short note on AC and DC load line. 05

June
2014

1. Draw and explain small signal hybrid-Pi model of BJT including

04
early effect.

2. The parameters of the transistors in the circuit shown in the

figure are β= 100 and VA= 100V.
i. Determine the DC voltage at base and emitter terminals
ii. Find Rc such that VCEQ= 3.5V and
iii. Assuming Cc and CE as short circuit, determine small
signal voltage gain Av=Vo/Vs.

10

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3. For the common base amplifier shown in the figure, derive the
expression for voltage gain, current gain, input resistance and
output resistance using hybrid-π model.

10

Dec 2013

1. Compare CB, CC and CE configuration. 04

2. Determine Ri, Ro, Av and gm for the amplifier circuit shown in

figure.

10

3. Determine Hybrid-π parameters.

05

4. Write short note on Hybrid-π model of BJT. 05

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AE-1/AE/EDC Prof. FAIZ RANGARI Exam Questions [EQ]
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June
2013

1. Design a single stage RC coupled CE audio frequency amplifier

employing BC147B BJT to satisfy the following conditions.
, SICO 10, Load resistor RL= 10KΩ and output 15
voltage Vo= 3V.

2. For the designed amplifier in above question determine,

expected voltage gain, input impedance, output impedance and 05
current supplied by source voltage VCC.
Dec 2012

1. Design for supply voltage Vcc, collector resistor Rc,emitter

resistor RE, voltage divider biasing resistor R1 and R2 of a single
stage RC coupled CE audio amplifier with following conditions. 10
, SICO 10, Load resistor RL= 5KΩ and output
voltage Vo= 3V.

2. For the circuit shown below, determine the following with

and β= 100
i. ICQ and IEQ
ii. Input and output impedance
iii. Voltage gain
iv. Current gain
v. List advantages of circuit shown

10

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Module 5: Small Signal Analysis of FET Amplifiers

Dec 2014

1. Draw small signal model of JFET and Explain significance of each 04

parameters.
2. In n-channel EMOSFET
i. Substrate Doping NA=1016cm-3
ii. Polysilicon Gate doping ND=1020cm-3
iii. Gate oxide thickness tox= 0.5m
iv. Oxide positive charge interface density= 4x1010cm-2
10
v. Charge of electron= 1.6x10-19 col
vi. Permittivity of free space= 8.85x10-14 F/cm
vii. Dielectric constant of Si= 11.9
viii. Dielectric constant of SiO2= 3.9
Find zero bias threshold voltage(VT0)

June
2014

1. For the common gate circuit shown in figure, the NMOS

transistors parameters are VTN= 1V, kn= 3mA/V2 and λ= 0.
i. Determine IDSQ and VDSQ
ii. Calculate gm and ro
iii. Find the small- signal gain Av= Vo/Vi. Assume Cc1 and Cc2
acts as short circuit for small signal analysis.
10

2. Derive expression for voltage gain of NMOS source follower 08

circuit.

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Dec 2013

1.

04

Obtain gm, ro and Av for the amplifier circuit shown in figure. In

which region the device is operating? Justify.

2.

10

VTN= 1V, Kn= 0.5mA/V2, λ=0.01V-1

Determine VGSQ and VDSQ

Also calculate voltage gain, input and output resistance

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June 2013

1. Design single stage RC coupled CS audio frequency amplifier

employing JFET BFW-11 to satisfy the following requirements
IDQ= 0.5IDSS, RL= 120KΩ, VDD=20V and output peak 10
voltage Vo=4.5V.

2. For the above designed circuit with source resistor R S

unbypassed, determine voltage gain, input impedance, output 10
impedance and output voltage for input voltage of 20VPP.
Dec 2012

1. Design single stage RC coupled CS audio frequency amplifier

employing JFET BFW-11 to satisfy the following requirements
IDQ= 3mA, RL= 120KΩ, VDD=20V and output peak 10
voltage Vo=4.5V.

2. For the above designed circuit with source resistor R S

unbypassed, determine voltage gain, input impedance, output 10
impedance and output voltage for input voltage of 20VPP.

3. Determine the small signal voltage gain of a MOSFET circuit

with VGSQ= 2.12V, VDD= 5V, Rd= 2.5KΩ, VTN= 1V, Kn= 0.8mA/V2
and λ= 0.02V-1. Assume transistor is biased in the saturation
region.

10

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Module 6: Oscillators
June
2015

1. Explain barkhausen criteria for sustained oscillations. 05

2. Draw a neat circuit diagram of Wien bridge oscillator and derive 10

an expression for its output frequency.
3. Write short note on crystal oscillator. 05

Dec
2014

1. Compare Collpit’s and Clapp’s Oscillator. 04

2. Explain the working of Wien Bridge Oscillator. Derive the

10
expression for frequency of oscillation and the value of gain
required for sustained oscillation.
3. Write short note on Twin-T oscillator. 05

June
2014

1. Why LC oscillators are preferred for high frequency 04

applications?
2. Draw and explain working of transistorized Wien bridge 10
oscillator.
3. Write short note on Twin-T oscillator. 07

Dec
2013

1. State and Explain barkhausen criteria for oscillations. 04

2. Derive the expression for frequency of oscillation for a 08

transistorized (BJT) RC phase shift oscillator.
3. Write short note on crystal oscillator. 05

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