Design of Control Module for ADC Based on FPGA

Xiu-ping Chen
Northwest University for nationalities
Lanzhou, Gansu, China
jscxp@xbmu.edu.cn

Abstract—In order to increase the flexibility of control for • You connect a cable from your computer to the
ADC, a new control method for ADC based on FPGA is proposed FPGA, and download the binary file to the FPGA.
in this paper. A state transition diagram can be drawn according FPGAs lose their functionality when the power goes
to the timing diagram of ADC, Which can be realized in FPGA away (like RAM in a computer that loses its content).
using Very High-speed Integrated Circuit Hardware Description
Language (VHDL). The simulate results show that logic in FPGA You have to re-download them when power goes
is consistent with the requirements. The module based on FPGA back up to restore the functionality[2].
can be modified just by modifying software, not the hardware.
III. ANALYSIS THE TIMING OF ADC
Index Terms—FPGA, Single Chip Microcomputer,
ADC,VHDL
The heart of this single chip data acquisition system is its
I. INTRODUCTION 8-bit analog-to-digital converter. The converter is designed to
ADC is widely used in industry control field. The give fast, accurate, and repeatable conversions over a wide
traditional control method for ADC is completed by single chip range of temperatures. The converter is partitioned into 3
machine. Advantages of this traditional method are simple major sections: the 256R ladder network, the successive
program and flexible control. Shortages of this traditional approximation register, and the comparator. The converter’s
method are long period and slow. The sampling rate of ADC is digital outputs are positive true[3].
limited by single chip machine, when the sampling rate of
ADC is very high. The paper is introduced a new method for The device contains an 8-channel single-ended analog
ADC based on FPGA. signal multiplexer. The device eliminates the need for external
zero and full-scale adjustments. Easy interfacing to
II. FEATURES OF FPGA microprocessors is provided by the latched and decoded
A. structure of FPGA multiplexer address inputs and latched TTL TRI-STATE
outputs. As shown in Fig 1.
FPGAs are programmable digital logic chips. What that
means is that you can program them to do almost any digital IN0
function. FPGAs are built from one basic "logic-cell", 8
START CLK
channels EOC
duplicated hundreds or thousands of time. A logic-cell is Analog
basically a small lookup table ("LUT"), a D-flip flop and a 2- Switches
to-1 multiplexer. The LUT is like a small RAM that can 8 bit Three-state D7
implement any logic function. Each logic-cell can be connected Analog/Digital output
IN7 Converter Latch
to other logic-cells through interconnect resources (wires/
multiplexers placed around the logic-cells). Each cell can do
little, but with lots of them connected together, complex logic D0
functions can be created. The interconnect wires also go to the ALE Address
boundary of the device where I/O cells are implemented and Latch
REF+ REF- OE
connected to the pins of the FPGAs[1]. and
A Decoder
B
B. The general workflow when working with FPGA
C

• You use a computer to describe a "logic function" Figure 1. Block Diagram

that you want. You might draw a schematic, or create
a text file describing the function, doesn't matter. A particular input channel is selected by using the address
• You compile the "logic function" on your computer, decoder. The address is latched into the decoder on the low-to-
using software provided by the FPGA vendor. That
creates a binary file that can be downloaded into the
FPGA.
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978-1-4244-8728-8/11/$26.00 ©2011 IEEE



START
ALE
ADD
IN0-IN7
EOC
OE
LOCK
D7-D0
Figure 2. Timing Diagram
high transition of the address latch enable signal.EOC start a
negative pulse after t he conversion starts; after the low-to-high
transition of EOC,TRI buffer is opened when out enable is high,
8 bits data of conversion output to the data bus. As shown in
Fig 2.
IV. REALIZATION OF CONTROL MODULE BASED ON FPGA
A schematic diagram based entry for the desired circuit
becomes very difficult to use this method for a large design
with hundreds of primitive gates. Hardware description
languages (HDLs) provide standard text based expressions of
the structure and behavior of digital circuits. Therefore HDL
languages are nowadays the preferred way to create FPGA
designs.
VHDL is a computer programming language designed to
illustrate the behavior of field-programmable gate arrays and
application-specific integrated circuits of digital systems in
electronic design. VHDL describes the performance of
electronic components in many areas. VHDL is used to
describe precise aspects of electrical circuit behavior in order to
create a VHDL simulation model. Incorporated with
schematics, block diagrams and system-level VHDL
descriptions, the VHDL simulation model can be used as the
foundation for building larger circuits[4].
A model consisting of a set of states, a start state, an input
alphabet, and a transition function that maps input symbols and
current states to a next state. Computation begins in the start
state with an input string. It changes to new states depending on
the transition function. Seven states are defined in this VHDL
program. As shown in Fig 3.
After the text edit has been completed, the paper is re
Figure 3. State transition diagram

A part of program is a process for state conversion:
process(clk)
begin
if (clk 'event and clk = '1') then
current_state <= next_state;
end if;
end process;
V. CONCLUSION
Quartus II software includes a simulator which can be used
to simulate the behavior and performance of circuits designed
for implementation in programmable logic devices. The
simulator allows the user to apply test vectors as inputs to the
designed circuit and to observe the outputs generated in
response. In addition to being able to observe the simulated
values on the I/O pins of the circuit, it is also possible to probe
the internal nodes in the circuit. The simulator makes use of the
Waveform Editor, which makes it easy to represent the desired
signals as waveforms. As shown in Fig 4.
Figure 4. Simulation results
According to the results of simulation, a new control
method for ADC is achieved in FPGA. Advantages of this new
method are simple programming method for FPGA/CPLD and
high Clock frequency. Modules based on FPGA can be
modified by just modify software, don’t modify the hardware.
Therefore, a new control method for ADC based on FPGA is
an effective method.
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