You are on page 1of 4

2010 International Symposium on Computer, Communication, Control and Automation

A Generalized Multi-channel PID Controller Module Design using FPGA


Chiu-Keng Lai, Cih-Ling Chen and Kun-Lin Ho
Department of Electrical Engineering, National Chin-Yi University of Technology
Taichung, Taiwan
e-mail: chiukl@ncut.edu.tw

Abstract—Proportional-Integral-Derivative (PID) controllers the work, to implement the PID control algorithm in
are universal control structure and have widely used in FPGA system, the control board used in [5] and shown in
automation systems, they are usually implemented either in Fig. 1 is adopted.
hardware using analog components or in software using The control board of Fig. 1 is mainly designed on an
computer-based systems. In this work, we focused our works
on building a multi-channel PID controller by Field
Altera Cyclone II FPGA with 208 pins. To fulfill the
Programmable Gate Arrays (FPGAs). Combining FPGA requirements of control system with analog signal input
with high speed multi-channel serial ADC and serial DAC, and analog signal output, 12-bit ADCs (AD7866) and 12-
the designed system has the effects of fast speed, high bit DACs (AD7564) both with serial interface are set.
accuracy, compact size and cost effectiveness. It is evaluated With those configurations, the control board can offer
by applying to a second-order system, and experimental eight channels for analog input and four channels for
results show that control performance is fulfilled the desired. analog output. To the work, the structure of the built
system is going to be designed to only include one
Keywords-PID Controller;FPGA hardware PID controller, and by switching the analog
I. INTRODUCTION input and output, the control board could realize four
generalized PID controllers to fulfill a variety control
The modern digital control systems require more and demands.
more strong and fastest calculation components. This type The block diagram to be configured in the FPGA to
of elements becomes indispensable with the utilization of realize the PID controller and its associated peripheral
some new control algorithms like the fuzzy control, the circuits are shown in Fig. 2.
adaptive control, the sliding mode control, and so on.
However, most of the above-mentioned control structures
need the system model, or some training data, to
determine the controller’s parameters. To consider the
industrial application, although PID controllers are the
oldest type, it is still the most important one to attain the
desired control performance for its simple control
structure and easily parameter tuning. Thus, regarding the
design of universal control structure, PID controller is the
most commonly used one. During the past years, FPGA
applications in mechatronics, control and signal
processing have been growing in relevance as an
economic and reliable option made to fulfill the
requirements of critical processes. As the implementation Figure 1. The FPGA-based control board.
of PID control algorithm, in [1], it shows the Distributed
Arithmetic (DA)-based scheme using Look-Up-Table
(LUT) mechanism inside the FPGA to efficiently realize
the proposed controller, and makes a comparison for DA-
based and IP-based implementation on a temperature
control system [2]. FPGA-based PID controller is also
presented on the control of magnetic bearing control
application, and comparisons are made for FPGA-based
and DSP-based system [3]. It shows that an FPGA-based
system has the advantage over a DSP-based system.
Adaptive system with fuzzy control realized by FPGA is
shown in [4], it is programmed on the platform of Altera
Quartus 7.0 system. In [5], a PCI interface control card
based on FPGA for motor control is shown. The functions
of encoder counter and pulse width modulation (PWM) Figure 2. The configurated block diagram of FPGA.
are set, and control algorithms are implemented by PC. In
978-1-4244-5567-6/10/$26.00 ©2010 IEEE 3CA 2010

II. FPGA HARDWARE IMPLEMENTATION FOR PID To build a generalized PID controller, the controller’s
CONTROLLER parameters are going to be arbitrarily assigned according
The structure of the proposed PID-based control to the system’s characters. Therefore, the controller’s
system can be as the one illustrated in the block diagram parameters are set in the range as Table I shows, where
of Fig. 3. Command input SP is the analog signal from the the corresponding sampling frequency is in the range [1
user, and PV is the process output, they both are Hz 100 kHz]. To attain the performance shown in Table I,
programmed in the range of [-5V +5V] to match the ADC we plan the controller’s parameters with the desired bit
input. The controller output u is also programmed to be number shown in Table II. To design a controller with
the range of [-5V +5V] by a shift and amplifier circuit wide applications for system with different bandwidth, the
although the range of the DAC’s output is [0V +5V]. sampling frequency is thus set from 1 Hz to 100 kHz, it
covers most of the application from chemical to electrical
TS K P Ki Kd field. As regarding the other parameters, to make sure the
controller’s performance has enough precision, we plan
SP + e PID u PV 19 bits for Ts , and 15 bits for K p , K i and K d . As Fig.
ADC DAC System
- Controller 3 shows, two analog inputs from 12-bit ADC are set to
convert the analog signals of command input and process
output to digital type, the ADCs are 12 bits width.
ADC Because the PID controller output is directly sent to the
DAC, the controller output u is also limited to be 12 bits.
Figure 3. The block diagram of PID-based control system.

TABLE I. THE PARAMETERS’ RANGE OF THE DESIGNED


A. PID Controller Design CONTROLLER
The PID control action in analog controllers is given
by (1), Range Unit

Ts [0.00001 1] sec
1 t d
u (t ) K p [e(t )  ³0 e(W )dW  Td e(t )] (1) Kp [0 2047.9375]
Ti dt
Ki [0 127.99609375]
where K p is the proportional gain, Ti is the integral time,
Kd [0 127.99609375]
Td is the derivative time, e(t ) is the error signal to the
controller input, and u (t ) is the output of the controller.
TABLE II. THE BIT NO. OF CONTROL PARAMETERS
Eq. (1) can also be represented as the form:
Bit no. of integer Bit no. of fraction
t d
u (t ) K p e(t )  Ki ³0 e(W )dW  K d e(t ) (2) Ts 0 19
dt
Kp 11 4

where Ki K p / Ti and K d K pTd , and are also the Ki 7 8

control parameters to be designed. To the work, we adopt Kd 7 8


the controller type (2) to be planed in the FPGA.
To realize the system (2) by FPGA, the backward e, u 12

difference equivalence,
Kp
1 - z -1 Ts
s
Ts K iTs

z -1
is chosen to convert the continuous-time system (2) into Kd Ts
discrete-time system,
z -1

U (z) Ts 1 - z -1
K p  Ki  Kd ( ) (3) Ts
E (z) -1 Ts
1- z Figure 4. The block diagram of z-domain control system.

where Ts is the sampling time.


Fig. 7 shows the results of command r4 V, and Fig. 8 is
the results with the command input r0.5 V.
Ki Kd Kp

(Ts )

Figure 6. The step response curve.

1
Ts

Figure 5. The architecture of the proposed PID controller.

B. The Implementation of PID Controller


The z-domain block diagram for digital PID controller
to be implemented is shown in Fig. 4, where Ts is
sampling time, it stands for the ADC on board, and ZOH
is realized by DAC. 16 different sampling frequencies are
previously set between 1 Hz to 100 kHz to be selected for
Figure 7. The simulated results with command = r4 V.
control implementation. The architecture used to realize
the PID controller shown in Fig. 4 is demonstrated in Fig.
5. To attain the performance of multiple inputs and
multiple outputs in one FPGA chip, 4x1 multiplexers are
used to select the desired input/output channel and
sampling time to implement the calculations.
The multiplier functions are mainly executed by the
embedded 9-bit multipliers of FPGA, and the usage of
multiplier to implement the designed PID controller is
50%.
III. SIMULATION AND EXPERIMENTAL RESULTS
The prototype second-order system used to evaluate
the performance of the designed PID controller has the
transfer function: Figure 8. The simulated results with command = r0.5 V.

36 .7309
H (s) (4)
2
s  7.51515 s  36 .7309

The step response of (4) shown in Fig. 6 is used to


determine the control parameters by the Ziegler-Nichols
method, and the designed control parameters are
respectively K p 9.6 , K i 4 and K d 0.25 .
First, the simulations by Matlab/Simulink are given.
The built block diagram to simulate the controller and
process is the same as Fig. 4. Two commands r4 V and
r0.5 V which respectively stand for large and small
command are used to check the controller performances. Figure 9. The experimental results with command = r4 V.


magnetic bearing,” American Control Conference, vol. 2,
pp. 1080-1085, June 2003.
[4] Ning Xiao, Kai Shuang, Deguo Wang and Guanmin Liu,
“Digital wide range electronic speed governor on FPGA,”
2008 10th International Conference on Control,
Automation, Robotics and Vision, pp. 313-316, Dec. 2008.
[5] Chiu-Keng Lai and Ching-Feng Chen, “Altera Cyclone II
FPGA-based PCI Control Card Design,” Proceedings of the
Third Intelligent Living Technology Conference, pp. 1431-
1436, Jun. 2008.

Figure 10. The experimental results with command = r0.5 V.

For both of the simulation results, command input,


process output and controller output to the process input
are shown. Command input is from a square wave with
period 9 sec, and controller output has limited to r5 V as
already shown.
To practically evaluate the hardware performance, the
system (4) is constructed by operational amplifier, and
system output is fedback to the ADC on the control board,
while the DAC output is sent to the second-order system.
The proposed PID controller is implemented using the
Altera Cyclone II FPGA as shown in Fig. 1, and
programmed in Quartus II 6.0.
The experimental results for command input r4 V
and r0.5 V are given in Figs. 9 and 10. For each of the
plot, three curves of command input SP, process output
PV, and controller output u are demonstrated for
comparison. In viewing those results, they show that the
hardware PID controller has attained the desired
performance.
IV. CONCLUSIONS
This paper has described an FPGA-based PID
controller design, and applied to a second-order system to
evaluate the system performance. To make sure the
desired accuracy and precision, and the system can be
applied to a variety application, the system reserves a lot
of bit no. for each of the controller’s parameters.
In the future, with the PCI interface IP, an interface
circuit to connect the PID controller command input and
the host computer could be planed, and the user is going
to easily modify the control parameters by manual or by
some adaptive algorithm to improve the flexibility of the
proposed hardware system.

REFERENCES
[1] Y.F. Chan, M. Moallem and W. Wang, ”Efficient
implementation of PID control algorithm using FPGA
technology,” 43rd IEEE Conference on Decision and
Control , vol. 5, pp. 14-17, Dec. 2004.
[2] Yuen Fong Chan, M. Moallem and Wei Wang, ”Design
and Implementation of Modular FPGA-Based PID
controllers,” IEEE transactions on industrial electronics,
vol. 54, no. 4, pp. 1898-1906, Aug. 2007.
[3] F. Krach, B. Frackelton, J. Carletta and R. Veillette,
“FPGA-based implementation of digital control for a