2012 Fifth International Conference on Intelligent Networks and Intelligent Systems
High-speed and portable data acquisition system based on FPGA
1st Cao XiaoQiang
School of Electronic Engineering
Tianjin University of Technology and Education
TIANJIN ,CHINA
E-mail: ganono@163.com
3rd Yao WeiTao
School of Electronic Engineering
Tianjin University of Technology and Education
TIANJIN ,CHINA
E-mail: ywt06034@163.com
Abstract—Based on the high speed and accuracy of ADC and
the advantages of USB, this paper is to design a high-speed and
portable data acquisition system based on FPGA and high-
speed USB interface device. The characteristics of AD9467and
CY7C68013A are introduced in the paper. And then we
introduced the design of hardware and the development of
software of this system. As the control core of data acquisition
processing and transmission controlling. The FPGA chip offers
high clock signal for ADC, controls other chips (FPGA and
USB interface device) to work harmoniously and Processes the
acquired signals. The designs of circuit diagram and FPGA
application software are described in detail. The results show
that reliable high-speed data transfer is achieved through the
USB interface.
Keywords- AD9467; ADC; FPGA; CY7C68013A; USB.
I. INTRODUCTION
In modern times, there are a lot of data acquisition
systems, some are high-accuracy but not high-speed; some
are high-speed but not high-accuracy. In this paper we try to
design a system to solve this problem. In addition, we apply
the concept of portable data acquisition to the system. and
use analog-to-digital converter AD9467 and high-speed USB
as high conversion rate and high sampled accuracy device.
ADC FPGA
Analog signal
Figure 1. The structure block diagram
B. System circuit connection diagram
In this high-speed data acquisition system, As the master
device, FPGA controls analog-to-digital converter AD9467
This work is supported by the National Science Foundation of China (grants 61071204) and the Development Foundation of
Tianjin University of Technology and Education (grants KJY11-3).
978-0-7695-4855-5/12 $26.00 © 2012 IEEE
DOI 10.1109/ICINIS.2012.26
2nd Zhang Jun
School of Electronic Engineering
Tianjin University of Technology and Education
TIANJIN ,CHINA
E-mail: studentandzhang@126.com
4th Ju MingYe
School of Electronic Engineering
Tianjin University of Technology and Education
TIANJIN ,CHINA
E-mail: doctor_tj@qq.com
The data acquisition system designed in the paper has
characters of high rate, high accuracy, pulling and playing in
any time at any place(if you carry a Personal Computer)
.This system has three core features:
a) High speed: 250 MSPS conversion rate.
b) High accuracy: 16-bit sampled accuracy.
c) Potable: Its power come from computer and it can
work in any time at any place.
II. HARDWARE
FPGA is the link of connecting DAC and USB interface
device in this system. So it plays an important role. It
receives the output digital signal of ADC , provides external
high-frequency clock signal for ADC and provides
synchronous clock signal for USB interface device.
A. System structure diagram
This system is based on FPGA, ADC and USB interface
devices. The master device that produces the high clock
signal that makes ADC and interface device synchronization
is FPGA. Under the control of FPGA, the digital signal
transformed from analog signal by ADC reaches principal
computer via high-speed USB Interface device. The
structure block diagram is shown in the figure 1.
USB PC
power
and USB Interface Device, Reflected in the input clock
signal and as the controller. We use the PLL of FPGA to
generate relevant input clock signal of AD9467, and use
Slave FIFO module for USB interface device. In order to
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make data transmission more efficientlyˈThe Slave FIFO bits. The circuit of the connection diagram is shown in the
of CY7C68013A is arranged synchronous way and the figure 2.
signal connection between FPGA and CY7C68013A is 16

AD9467 EP2C8Q208C8N CY7C68013A

IFCLK
CLKOUT

DCO CLKIN FIFO

I/O
VIN+ FD[15:0]

VIN- D+
D[15:0] I/O[15:0]
I/O FIFO[2:0] D-
PC
I/O PKTEND

CLK+ I/O
PLL
CLK- I/O SLRD
SLWR
I/O SLOE

Figure 2. The circuit of the connection diagram

out. “clk_out” is output pin, providing clock signal for ADC,

III. SOFTWARE
The software design of system mainly include: external
input clock signal design of AD9467 and the software
design of FPGA controlling USB interface Device.
A. AD9467 external input clock signal
In figure 2, we can see that FPGA chip’s input signals
include digital signal of 16 bits and one Synchronous clock
signal, meanwhile FPGA needs to provide a clock signal of
high frequency for ADC at the front. In order to provide
clock signal for ADC, use the PLLs (phase-locked loop) of
Quartus IIDŽ
The PLLs of Quartus II is also called The Flushbonading
PLLs, Only in the FPGAs of Cyclone and Stratix PLLs is
integrated. Altera Cyclone FPGAs except for EP1C3
integrate one PLL, others integrate two PLLs. This kind of
PLLs not only have superior performance, but also,
according to needs, set up the parameter, the phase shifting
and the duty cycle of fractional frequency and frequency
multiplication. There is an example of using PLL module to
provide high clock signal to ADC, it can change the value of
the input clock signal of ADC only by changing some
parameters, so it improves the flexibility of the system. The
RTL diagram of PLL is shown in figure 3.
CLK_PLL:inst
rst areset c0 clk_out
inclk inclk0 locked locked
its parameter is 250MHz due to multi plicate frequency. “rst”
is PLL reset signal active high, “Locked” is showing output
clock and is stable after PLL processing active high.
Functional simulation diagram is shown in the following
Figure 4.
Figure 4. The timing simulation of PLL.
B. LVDS transmitter Module
The MegaWizard Plug-In Manager tool of Quartus II
sofeware offers IP for processing LVDS signal. In AD9467
chip, some LVDS share a single pin, such as D0 and D1, D2
and D3, … , D14 and D15. So we only set 8*2 bits LVDS
input channels and 8 bits output signals. In order to separate
D0, D2, D4, … , from D1, D3, D5, … .Added
“REG_8”module. Its function is shown in TABLE 1. When
input clock signal “inclock” is up, putting d_in[7:0] to assign
d_out[7:0]. And when input clock signal “inclock” is down,
putting d_in[7:0] to assign d_out[15:8].
TABLE 1. FUNCTION OF “REG_8”MODULE
inclock Assigning

Up d_out[7:0]<=d_in[7:0]
Figure 3. The RTL diagram of PLL Down d_out[15:8]<=d_in[7:0]

The “inclk” is the clock signal of system, and its

frequency is 50MHz. PLL can set up the parameter of The RTL diagram of LVDS transmitter Module as shown
fractional frequency and multi plicate frequency and then put in the figure 5.

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 ALTLVDS_16:inst1 REG_8:inst2 Taking sine wave for example, the set of signal source
tx_inclock tx_inclock tx_outclock in_clock
parameter are shown in TABLE 2. When the sampling rate
d_out[15..0] d_out[15..0]
DATA_in[15..0] tx_in[15..0] tx_out[7..0] d_in[7..0] is 10 MHz, the spectrum analysis diagram of sampled
digital data is shown in figure 6 and the data acquisition
board is shown in figure 7.
Figure 5. The RTL diagram of LVDS transmitter Module

C. Software design of FPGA controlling USB interface TABLE2. SIGNAL SOURCE PARAMETER
Device
Parameter Value

In this paper, the CY7C68013A chip operates in slave output frequency (ˆୱ ) 1MHz
FIFO mode and operates clock (IFCLK) supplied by external high voltage (ୌ ) 2.5v
master.
The chip slave FIFO architecture has eight 512-byte low voltage (୐ ) -2.5v
blocks in the endpoint RAM that directly serve as FIFO
memories and are controlled by FIFO control signals (such
as IFCLK, SLRD, SLWR, SLOE, PKTEND). SLOE, SLWE,
SLRD, PKTEND signals are active low and controlled by
external master FPGA.
When write signals in the FIFO, we set SLOE=0 ǃ
SLWR=0 and the rising edge of IFCLK. When read out
signals from the FIFO, SLOE=0ǃPLTEND=0 and the rising
edge of IFCLK. The software is long, so it no giving in this
paper.
IV. TEST AND VERIFY
The FPGA whole project follow the top-down design
principles, gain configuration file of the SRAM through
Compiling, comprehensive analyzing, layout, wiring and
Figure 6. Spectrum analysis diagram
timing analyzing. This system can be debugged on line after
the configuration file being downloaded in target device
byway of JTAG.

Figure 7.Data acquisition board

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 V. CONCLUSION
This paper designed a portable and high-speed data
acquisition system based on FPGA. Without add another
power. We acquire electricity directly from USB interface.
Experiments show that the system can convert the digital
signal to the host computer. The entire system is designed to
be simple, stable. So it reaches the design requirements.
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