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2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME)

The Design of an ADC on a FPGA Used For the


Control of a Switched Mode Power Supply
C. Orian, T. Pătărău and D. Petreuş
Applied Electronics Department
Technical University of Cluj-Napoca
Cluj-Napoca, Romania

Abstract—The following paper describes the design and parameters. Likewise, its accuracy influences the performance
implementation of an analog-to-digital converter (ADC) using an of the overall power supply. The implementation of the ADC
FPGA circuit – Artix 7, manufactured by Xilinx inc. The ADC on the FPGA leads to a more compact design, lower
implemented is intended to be part of a digital control circuit for component count and lower costs. Also, it can be reproduced
a DC-DC inverter. All blocks of the control circuit will be part of on the FPGA if more ADCs are required. Designing a custom
the FPGA circuit. The method described requires two successive made ADC leads to flexibility in choosing the sampling rate
conversions, namely voltage-to-time and time-to-digital. Both and resolution, as opposed to using a separate ADC (already
conversions will be presented in terms of design, physical available on the FPGA or as an ASIC), which features a
implementation and experimental results. Various ways to
predefined sampling rate. Custom made ADCs can be designed
improve the accuracy of the resulting conversion will be
discussed.
as strings of diode connected mosfets and D flip-flops. Such a
method was proposed in [1].
Keywords— analog to digital converter, digital control, FPGA, The analog to digital conversion proposed in this paper is
dc-dc converter. divided into two processes: a voltage to time conversion and a
I. INTRODUCTION time to digital conversion. In order to complete the voltage to
time conversion, a test signal is required. This test signal must
The digital control of power supplies provides several be periodical and must follow monotonic variations both
benefits over its analog counterpart such as increased accuracy during its increase and during its decrease. Such solutions have
of the control transfer function, self-calibration capability, the been proposed in [2], [3]. The resulting test signal is compared
ability to communicate with other devices, the reduction in the to the input voltage in order to generate a periodic logic signal
overall component count. The benefits do, however, come at a whose duty factor varies with the input voltage. This is the
price: an analog-to-digital conversion is required; the voltage to time conversion
computation of the duty factor takes a longer amount of time;
generating the duty factor requires a higher frequency counter. The time to digital conversion can be accomplished by
These drawbacks may restrict some of the design parameters of using a counter circuit. The result of the count during a defined
the dc-dc converter, such as the switching frequency, which period of time produces a time to digital conversion, but in
may hinder the miniaturization of the overall system. For this order to increase the accuracy of this conversion the counter
reason a careful design of the control block is required. clock frequency must be high. If the available clock frequency
is not high enough for the desired conversion accuracy, an
One way to implement the digital control of a power supply alternative method which relies on propagation time delays can
is to use FPGA circuits. They work at high frequencies be employed. A constant logic level is propagated through a
(hundreds of MHz) and offer the possibility to synthesize a string of delay cells for a defined duration, the duration being
broad range of circuits. Some of the resources available on an the input signal. At the end of the duration the number of delay
FPGA circuit are logic blocks, such as look-up tables (LUT), cells through which the constant logic level propagated is the
flip-flops, multiplexers or summers featuring carry look-ahead output of the time to digital conversion. Such converters have
capability, interconnection blocks and phase-locked loops for been proposed in [4-10].
frequency synthesis. The circuits implemented on an FPGA
function simultaneously, which leads to a decrease in II. METHODS
processing delays. Also, after the thorough validation of the The block diagram of the ADC is given in Fig. 1. It consists
design, it can be translated into an ASIC digital controller for of two cascaded stages: a voltage-to-time converter (VTC) and
power supplies. a time-to-digital (TDC) converter.
The analog-to-digital converter (ADC) is used primarily in
the feedback loop. It can, however, be part of the self-
calibration process as the front-end of the data acquisition Vin time digital
system. Its sampling rate and resolution are both important
VTC TDC
Fig. 1. The two stages of the described ADC.

978-1-4799-6962-3/14/$31.00 ©2014 IEEE 111 23-26 Oct 2014, Bucharest, Romania


2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME)
A. Voltage-to-time conversion
The voltage-to-time conversion is based on the comparison
of the input voltage to a periodically varying test signal, as
presented in Fig. 2. It is not required that the test signal be a
sawtooth shaped voltage, but it must exhibit a
bijective waveform during its rise and/or decrease in order for
it to be possible to uniquely establish the inverse voltage-to-
time dependence.
The test signal is not readily available at the FPGA circuit,
which is why it must be generated separately. One way to
achieve that is to make use of the VGA port, which can output
Fig. 3. A: The ESD protection components present on Nexys4;
signals in the range of tens of MHz. Another way is to apply a B: Parasitic components and the resulting circuit diagram.
rectangular wave to a series RC circuit and collect the voltage
across the output capacitor, which meets the aforementioned
ªT º
requirement that its variation be of bijective nature. The «2 T »
1 « T
rectangular waveform can be generated by the FPGA circuit at  ˜ ³i (t )dt  ³ i (t  )dt » 0A   
the desired frequency and duty factor. A 50% duty cycle will T « 0 Ch arge T
Disch arge 2 »
« »
be considered throughout this paper. However, there are no RC ¬« 2 ¼»
circuits integrated in the FPGA. One solution is to make use of
the external components available on the Nexys 4 development ­T ª t º T ª t º ½
° «  » «  » °
board. All general purpose pins have been fitted with ESD 1 °2 « ( E  U ) ˜ e RC » dt  2 « HU ˜ e RC »dt °
 ˜® ³ «
L
» ³ « » ¾ 0A   
protection components, as shown in Fig. 3A. The reverse- T °0 R R
« » 0 « » °
biased Zener diodes exhibit a parasitic capacitance, which can ° «¬ »¼ «¬ »¼ °
¯ ¿
be used to form the desired RC circuit. Fig. 3B presents such a
circuit, which can be implemented by connecting two pins at T
t t
the Pmod connector. The value of the RC circuit is not known, E  U L 2  RC U H T  RC
however it can be inferred.  ˜ ³ e dt ˜ ³e dt Ÿ E  U L UH   
R 0 R T
During the charging of the capacitor, its voltage and current 2
vary as follows:
Revisiting (3) and considering a 50% duty factor yields
§ ·
§ t · ­
E UL UH ¨ T ¸
¨  ¸ °
°
¨  ¸
 u c (t ) ¨
(E  U L ) ˜ 1  e RC ¸ UL     °
®

T Ÿ U ˜ ¨¨1  e 2 RC
H
¸
¸ E   
¨ ¸ ° ¨ ¸
¨ ¸ °
°U L U H ˜ e 2 RC ¨
¨
¸
¸
© ¹ ¯ © ¹

t ­
E
 °
UH
E  u c t RC °
(E  U L ) ˜ e ° T
 ic (t )    §
¨ T ·
¸
° 
R R ¨  ¸
°
° 1  e 2 RC
 ¨
U H ˜ ¨1  e 2 RC
¸
¸ EŸ °
® T   
The discharge equations are ¨
¨
¸
¸
°
° E 
¨ ¸ °U ˜e 2 RC
© ¹ ° L T
°
° 
t ° 1  e 2 RC
 ¯
 u c (t ) UH ˜e RC   
Fixed values for the E, R, C and the rectangular signal
t period T can control the high and low thresholds, UL, UH.

u R (t ) u c (t ) U H ˜ e RC The input voltage and the test signal are applied at the
 ic (t )     
R R R inputs of a comparator. Assuming the frequency of the test
The average capacitor current is 0A in steady state. signal to be constant, the output signal of the comparator will
be a rectangular signal whose duty factor will vary as the input
 I
avg
0 A Ÿ 'i
charge
'i
discharge    voltage varies. The resulting high or low times at the output of
the comparator can be correlated with the input voltage. The
1 T test signal can be expressed as
 ˜ ³ i (t )dt 0A   
T 0c  u s (t ) U L  ¦U i ˜ sin Zi t  Mi   
Vin and this leads to the fact that the threshold voltage at the
comparator input is located at a unique and well defined
time moment during each test signal period, the threshold voltage
Vtest being the test signal value for which the output of the
Fig. 2. The VTC.
comparator changes state. As a consequence, if the high time

978-1-4799-6962-3/14/$31.00 ©2014 IEEE 112 23-26 Oct 2014, Bucharest, Romania


2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME)
th of the comparator output is known, then the corresponding buffers to our advantage. The method requires a string of
input voltage is (considering the input voltage to be applied at cascaded transmission gates, all of which are enabled by the
the non-inverting comparator input) high state of the time signal. An input signal, which is different
from the enable signal and is always in a high state, is applied
 uin u s (t h ) U L  ¦U i ˜ sin Zi ˜ t h  Mi    at the input of the first transmission gate. After the falling edge
of the enable signal, a logic circuit determines the number of
The comparator can be an external ASIC or the internal transmission gates the input propagated across. Considering a
comparator at the FPGA pins. The benefit of using the latter is constant delay through each gate in the string, the time-to-
the fact that it reduces component count. It does, however, digital conversion is achieved. This method does come at a
require a minimum differential voltage of at least 100mV, price: the time delays through the gates in the string are not the
which reduces accuracy. Moreover, the 100mV threshold is same, as shown in Fig. 5. The downwards arrows at the top of
not fixed, but a process and temperature dependent variable. the figure represent the fixed value for the delay which is
This further reduces accuracy and requires calibration or self- considered when correlating the input time and the output
calibration features. number. In addition to the propagation times not being equal,
The FPGA internal comparator can be configured to they may vary with temperature. This is why it is required to
conform to the DIFF_HSUL_18 standard. The common and calibrate this conversion.
differential mode input voltage specifications are listed below,
An increase in accuracy can be achieved by using a string
in Tab. I. of delay cells and a counter running on a high accuracy clock
The 100mV minimum differential input voltage will lead frequency together, as shown in Fig. 6. Again, the downwards
to a decrease in measurement accuracy. Moreover, its possible arrows at the top of the figure represent the fixed value for the
variation with external factors may lead to an error which is delay which is considered when correlating the input time and
not deterministic and which cannot be eliminated using a the output number.
calibration procedure. A self-calibrating design may lead to
better results. The common mode input voltage is limited, The diagram comprising cascaded transmission gates
although the differential mode voltage is not. This is why enabled by the time signal is presented in Fig. 7. However,
transmission gates cannot be directly implemented in the
voltages as high as 2.2V can be applied at the comparator
FPGA circuit available. Instead, LUTs were implemented. In
inputs.
this case, the time signal no longer enables the circuit block
The propagation delay through the comparator is presented (LUT), but is one of its inputs. The propagation delays through
in Tab. II, speed grade 1. the LUTs are assumed equal and influence the number of
B. Time-to-digital conversion outputs asserted at the falling edge of the time signal.
The time-to-digital conversion is acquired by employing a
counter circuit. The counter is enabled by the time signal and
its output binary number is correlated with the input, thus
achieving the time-to-digital conversion. In order to increase
the resolution, a higher clock signal frequency is required. An
increased frequency can also lead to a decrease in quantization
error. Fig. 4 a, b highlights the quantization error for two
different clock frequencies.
The clock frequency in an FPGA circuit may not be high
enough for the desired ADC. An alternative counter can be
implemented by using the propagating time of signals through Fig. 4. Time to digital conversion and quantization error (pink) depending on
the counter clock frequency. a: Low clock frequency. b: High frequency.
TABLE I. DIFF_HSUL_18 standard

Fig.5. Unequal delays through a string of series cells.

TABLE II. I/O propagation time through the comparator.

Fig. 6. TDC with a low frequency and high frequency counter.

978-1-4799-6962-3/14/$31.00 ©2014 IEEE 113 23-26 Oct 2014, Bucharest, Romania


2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME)

TABLE III. VTC - experimental results.

Measured Measured Inferred Relative


voltage [V] time [s] time [s] error [%]
1.2 3.28∙10-9 3.6∙10-9 8.86
1.3 4.83∙10-9 4.8∙10-9 0.58
-9 -9
1.4 6.33∙10 6.4∙10 1.04
-9 -9
1.5 7.81∙10 8∙10 2.36
-9 -9
1.6 9.27∙10 9.2∙10 0.78
-9 -8
1.7 10.73∙10 1.06∙10 1.2
-9 -8
1.8 12.19∙10 1.2∙10 1.57
-9 -8
1.9 13.67∙10 1.36∙10 0.49
-9 -8
2 15.17∙10 1.52∙10 0.18
-9 -8
2.1 16.72∙10 1.6∙10 4.49
-9 -8
2.2 18.32∙10 1.72∙10 6.52
Fig. 7. The implemented TDC and its functionality.
In order to acquire the data presented in Tab. 4, the average
propagation delay per LUT was inferred. Its value was found to
III. RESULTS
be 0.456ns. In fact, this delay comprises both the LUT and the
In order to carry out the voltage-to-time conversion a path propagation times. Depending upon the placement of the
50MHz rectangular waveform was generated. Its duty factor LUT within the FPGA and the connections created, the overall
was 50% and the high and low voltage levels are 3.3V and 0V, TABLE IV. TDC - experimental results.
respectively. This rectangular waveform was applied to an RC
series circuit and the resulting capacitor voltage varied Measured Absolute Relative
between 1.2V and 2.2V. This is the test signal and it is applied Time
delay [no of error [no error
to one comparator input. The voltage which is intended to be [ns]
LUTs] of LUTs] [%]
measured is applied to the other comparator input. The
20 44 0.18 0.41
measured voltage can be no lower than 1.2V and not higher
than 2.2V. Equation (11) leads to the time constant of the RC 30 71 5.27 8.01
circuit. 40 93 5.36 6.11
T 20 ˜ 10 9 s
 W RC   12.68 ˜ 10  9 s    50 113 3.45 3.15
§U · § 1.2V ·
2 ˜ ln ¨ L ¸ 2 ˜ ln ¨ ¸ 60 142 10.54 8.02
¨U ¸ © 2.2V ¹
© H ¹ 70 155 1.63 1.06
Using (1), we find the inverse dependence 80 178 2.72 1.55
90 207 9.81 4.97
§ V UL ·
 t  RC ˜ ln ¨1  in ¸   100 227 7.9 3.6
¨ E UL ¸
© ¹
110 232 9.01 3.74
The result returned by (15) is the duration of the time 120 271 8.08 3.07
signal, the output of the voltage-to-time conversion. The same 130 303 18.17 6.38
duration was determined experimentally between the 50%
points on each signal edge. The results inferred by (15), as well 140 319 12.26 4
as the experimental results, are presented in Tab. III. 150 350 21.35 6.5
The subsequent time to number conversion was carried out 160 366 15.44 4.4
by generating a 5MHz signal of different duty cycles and using
170 384 11.53 3.1
it as the input time signal. This signal was applied to the string
of series LUTs, as described in section IIB. The experimental 180 392 2.38 0.6
results for the time to digital conversion are presented in Tab. 190 425 8.7 2.09
IV.

978-1-4799-6962-3/14/$31.00 ©2014 IEEE 114 23-26 Oct 2014, Bucharest, Romania


2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME)
delays may differ. The results presented above were acquired
after using a Xilinx Vivado feature to minimize time delays
through the created design. It is, however, possible to manually REFERENCES
set the circuit area where each delay LUT string will be placed. [1] J. Wu, J. Odeghe, S. Stackley and C. Zha, “Improving Single Slope
This can aim to reduce connection lengths and overall delays. ADC and an Example Implemented in FPGA with 16.7 GHz Equivalent
However, after running the implementation phase several times Counter Clock Frequency,” IEEE Nuclear Science Symposium
Conference Record, 2011.
on the given design, the results were not significantly
[2] J. Wu, S. Hansen and Z. Shi, “ADC and TDC Implemented Using
improved. The average propagation delay per LUT varied FPGA,” IEEE Nuclear Science Symposium Conference Record, 2007.
between 0.417ns and 0.445ns. Moreover, the average
[3] B. Patella, A. Prodić, A. Zirger and D. Maksimović, “High-frequency
conversion relative error increased, even though it did not digital PWM controller IC for DC/DC converters,” 2003, Vol. 18, 1.
differ by more than 1% from that in Tab. 4. [4] R. Chebli, Md. Hasanuzzaman, A. Haidar, M. Sawan, “Successive-
divider-line ADC dedicated to low-power medical devices,”
The two stages of the analog to digital conversion, namely Microelectronics Journal. 43, 2012.
the voltage to time and time to digital have been presented.
[5] D. Maksimovic, R. Zane, R. Erickson, “Impact of Digital Control in
Both of them yielded experimental results, which have been Power Electronics,” 2004.
presented and both of them are more prone to errors as their [6] G. Li, Y. M. Tousi, A. Hassibi, E. Afshari, “Delay-Line-Based Analog-
respective inputs vary towards the extremities of their allowed to-Digital Converters,” IEEE TRANSACTIONS ON CIRCUITS AND
ranges. An attempt to eliminate these errors can be made by SYSTEMS, Vol. 56, 2009.
means of calibration. If, however, the errors vary with external [7] A. Balla et al, “The characterization and application of a low resource
parameters, then a self calibration algorithm may be required. FPGA-based time to digital converter,” Nuclear Instruments and
Also, including the results in a feedback loop may reduce the Methods in Physics Research Section A: Accelerators, Spectrometers,
Detectors and Associated Equipment, 2014.
error as long as the loop gain is high at the frequency of the
[8] A.Warner, J. Wu, “Cryogenic Loss Monitors with FPGA TDC Signal
error signal, which is usually low enough such that it can be Processing,” Technology and Instrumentation in Particle Physics, 2011.
considered DC.
[9] C. Hervé, J. Cerrai, T. Le Caër, “High resolution time-to-digital
converter (TDC) implemented in field programmable gate array (FPGA)
ACKNOWLEDGMENTS with compensated process voltage and temperature (PVT) variations,”
This paper is supported by the Sectoral Operational Nuclear Instruments and Methods in Physics Research Section A:
Accelerators, Spectrometers, Detectors and Associated Equipment,
Programme Human Resources Development (SOP HRD), 2012.
ID/134378 financed from the European Social Fund and by the
[10] G. Bencivenni et. al, “A Time Domain Reflectometer with 100 ps
Romanian Government. precision implemented in a cost-effective FPGA for the test of the
KLOE-2 Inner Tracker readout anode,” Nuclear Instruments and
This paper is supported through the programme Methods in Physics Research Section A: Accelerators, Spectrometers,
"Parteneriate in domenii prioritare – PN II", by MEN – Detectors and Associated Equipment, 2013.
UEFISCDI, project no. 53/01.07.2014.

978-1-4799-6962-3/14/$31.00 ©2014 IEEE 115 23-26 Oct 2014, Bucharest, Romania

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