The 2014 7th International Congress on Image and Signal Processing
Cyclic Codes Error Correction System
Based on FPGA
Yao Li, Dongxia Shi
College of Computer and Information Technology
China Three Gorges University
YiChang China
Abstract—This paper designed and accomplished a codec
system of the cyclic code. The encoding system was based on the
principle of dividing circuit and the decoding system was based
on the principle of Meggitt decoder. There are three main steps
in the error correction system which designed for the cyclic code.
First, the three binary information codes can be encoded into a
group of seven binary codes by using the dividing circuit. Then,
the syndrome calculator and spontaneous calculator are used to
decode information. The spontaneous calculator can detect an
error code word and correct it. Finally, the three binary
information codes were successfully encoded and decoded into a
group of codes which contain seven binary information. The
result of the experiment shows that the cyclic code error
correction system can better correct the burst errors and single
random error code. It is easy to reach the goal of error-free
transmission.
Keywords-Cyclic code; Error detection and error correction;
Meggitt decoder; FPGA; Simulink
I. INTRODUCTION
Because the cyclic code is a code which has a clear
algebraic structure, better performance, and strong error
detection and correction ability, the success of the cyclic code
encoding and decoding has important significance for
telecommunication and error correction system in computer.
Although Parallel error trapping decoding method is suitable
for application in high speed networks (such as 10G Ethernet,
100 G Ethernet)in reference[1], the method is too complex and
costly. The cyclic codes error correction in the channel
encoding has solved the problem of decoding in reference[2],
but it does not describe in the aspects of the syndrome
calculator circuit and the combination logic circuit. The
reference[3] uses Meggitt decoding principle to solve the
difficulty of the cyclic codes decoding and to describe the
problems existing in the decoding (error detection and
correction) process in detail, which solves the decoding
problems fundamentally, but there is no specific description of
the designing in encoding and decoding. In addition to Meggitt,
decoding method of cyclic code decoder consists of error
trapping decoding[1], majority logic decoding and so on. Error
trapping decoding which is a variant of Meggitt decoding can
978-1-4799-5835-1/14/$31.00 ©2014 IEEE
Ping Xia
Institute of Intelligent Vision and Image Information
Three Gorges University
College of Computer and Information Technology
China Three Gorges University
YiChang China
be accomplished with the simple combination logic circuit. It is
especially suitable for the correction of burst error, a single
random error and the two error code words. The algorithm and
the hardware of majority logic decoding (threshold decoding)
are simple, so it is widely used in practice.
It can only be used for a few certain structure of majority
logical decoding, at the same time, the majority logic decoding
error correcting ability and coding efficiency are a bit poorer
than other cyclic code (BCH code) with the same parameters
under normal circumstances. On the basis of reference [3], this
paper implements the relationship between syndrome and error
pattern. That makes the principle of Meggitt decoder clearer
and easier to implement the decoding circuit, thus it achieved
the capability of error detection and correction in decode circuit
on hardware.
II. PRINCIPLE OF DESIGNING THE SYSTEM OF THE
ENCODING AND DECODING IN CYCLIC CODE
A. The Basic Principles of The Cyclic Code
A (n, k) cyclic code is a linear code whose code length is n
and information code is k, its greatest feature is the cyclical
characteristics. Circulation of cycle code means that anyone of
the codes group is still in this goup after cyclic shifting. The
linear block code is called cyclic codes with this feature of
cyclic shift invariance.
B. The Design of The Encoding System
According to the formula shown below, m(x) is the
information code polynomial, g(x) is the generator polynomial
of the cyclic codes, r(x) is the supervision code polynomial.
Encoding formula of cyclic codes:
x n − k • m( x ) r( x)
= Q( x) +
g ( x) g ( x) (1)
According to the formula (1), the core of the encoding is to
determine the remainder r(x), after r(x) being found, the code
can be directly added to the information code to finish the
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encoding. The division circuit can realize r(x). The figure 1 is The relationships between the supervised matrix of H and
the principle of (7,3) cyclic codes encoding circuit. the received matrix of R, the error pattern of E and the
syndrome of S are [4]:
S = R• HT = E • HT (4)
Obtained from the formula (2) and (4):
E (x) S(x)
= Q / (x) +
g(x) g(x) (5)
Let (7,3) generating polynomial of cyclic codes:
g(x)=x4+x2+x+1
Figure.1 the principle of (7,3) cyclic codes encoding circuit
and E=(0100000), which can be represented by E(x)=x5,
C. The Design of The Error Correction System then
The key is to calculate the syndrome in the progress of E( x) x5 x3 + x 2 + x
realizing the decoding circuit. If the syndrome is 0, then the = 4 2
=x+ 4
g( x) x + x + x + 1 x + x 2 + x + 1 (6)
receiver receives a correct code group. If not, it indicates that 3 2
S(x)=x +x +x, S=(1110).
error code occurs in the receiving code group. Like the
formula of encoding circuit, the calculation formula of Similarly, it can obtain the relationships of the (7,3) cyclic
syndrome in decoding circuit is: code between the alternative syndrome and the error pattern
which has one error bit. Seeing in the table.
R( x ) S ( x)
= Q( x) +
g( x) g ( x) (2)
TABLE the relationships of (7,3) cyclic code between the alternative
syndrome and the error pattern which has one error bit
Error pattern E Syndrome S
R(x) represents the received code group of polynomial, Error bit E(x) S(x)
e6e5e4e3e2e1e0 s0s1s2s3
g(x) is a cyclic code generator polynomial, S(x) is the e6 1000000 x6 x3+x+1 1011
syndrome. Therefore, cyclic code decoding (error detection, e5 0100000 x5 x3+x2+x 1110
error correction) circuit has the following three steps: e4 0010000 x4 x2+x+1 0111
e3 0001000 x3 x3 1000
1) Computing the corresponding of the syndrome e2 0000100 x2 x2 0100
polynomial according to the received code group of e1 0000010 x1 x 0010
polynomial R(x); e0 0000001 1 1 0001
2) Finding out the error pattern E(x);
3) Using the error pattern for error correction:
C(x)=R(x)+E(x) (3) The decoding circuit of Meggitt decoder consists of three
The decoder based on error pattern recognition is called parts:
Meggitt decoder, as shown in Figure 2, the error pattern 1) Syndrome calculator (division circuit): calculate the
recognizer is a logic circuits with n inputs. It can find out the syndrome S(x);
error pattern in principle by looking up the table according to
the syndrome. The characteristics of cyclic codes can simplify 2) Spontaneous calculator: find out the corresponding error
the identification circuit. pattern E(x) according to the syndrome; Adder:
C(x)=R(x)+E(x) (7)
The operational principle of the Meggitt decoder: In Figure 3) The error correcting code circuit of (7,3)cyclic code
2, k buffer shift registers are used for storing the cyclic codes whose Generating polynomial is g(x)=x4+x2+x+1 which
information codes, Modulo 2 adder circuit is used to correct is shown in figure 3.
the error. When the syndrome is 0, the input of the modulo 2
adder, which is from the error pattern recognition circuit, is 0
and then output the contents of the buffer shift registers. If not,
its output is 1 in part i, it can take complements of its output,
then correct the error. Meggitt decoder is particularly suitable
for correcting random independent error less than 2.

Figure.3 the decoding circuit of the cyclic code

The internal structure of syndrome calculator and

Figure.2 The operational principle of the Meggitt decoder

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spontaneous calculator is shown in figure 4.
A. Syndrome calculator
B. Spontaneous calculator
Figure.4 syndrome calculator and spontaneous calculator
In figure 4, the received code R is entered into the
syndrome calculator and the registers respectively at the same
time. When all R have been entered into the register, the code
word in the syndrome calculator is the syndrome S. If
S = (0000) , it suggests that the received code word is correct.
If S ≠ (0000) , this state is set as the initial state of the
spontaneous calculator through control gate, detecting the
position of the error codes.
When the error pattern is (e6e5e4e3e2e1e0)=(0100000), it
means “r5” is wrong. The front has been calculated that,
starting from this state, the syndrome calculator changes its
state once as the register shift one time, at the same time, the
register shift out one bit from the code words. The state of the
syndrome has changed (1110) → (0111) , after once shift,
“r6”which is in the register shifts out, “r5” shifts as the output
bit of the buffer shift register, at the same time, the state of
spontaneous calculator changes: (0111) → (1101) , so the output
of the adder is s0 s1s2 s3 = 11 0 1 = 1 , when “r5”is being removed,
it can be corrected, using the formula: r5 ⊕ 1 = C 5 . Due to that
the initial state of the spontaneous calculator corresponds to an
error pattern, when the error bit of the code word in the
register has shifted to the end of it, the state of the spontaneous
calculator is S0S1S2S3=(1101) and the output of the adder is
always 1, so we can correct one bit of error.
It can be known that, when analyzing the operational
principle of the shift register in syndrome calculator circuit
and the spontaneous calculator circuit, the data sent into the
shift register in the first pulse will be outputted in the second
pulse. It can be viewed as a problem of delay. Therefore, the n
buffer shift register must be added another class of register to
form the n+1 buffer shift register and to ensure that no
correcting error caused by delay problems.
III. THE REALIZE OF THE (7,3) CYCLIC CODE’S
ENCODING AND ERROR CORRECTION SYSTEM
BASED ON SIMULINK
A. The Realize of The Encoding System
According to the coding circuit of (7,3) cyclic code, the
cyclic code simulation can be accomplished with Simulink. It
is showed in figure 5.
Figure.5 the encoding system of (7,3) cyclic code
The “scope” in the figure 5 is oscilloscope, it is used to
display the time-dependent waveform.
In figure 5, the “Step” block provides step between two
custom level within the specified time. If the simulating time
is less than the time parameters set in the “step time”, the
output of “step” block is the parameters of initial value. When
the simulating time is greater than or equal to “step time”, the
output is the parameters of the final value. The parameters
which are set in the “step” block in the encoding system are as
follows: “step time” is set to 3, the “Initial value” is set to 1,
the “Final value” is set to -1. When the simulating time is less
than 3, the output of the Step value is 1. When the simulating
time is greater than or equal to 3, the output of the “step”
block is -1. The output waveform of “Step” block is shown in
the following figure 6.1:
Figure.6.1 the output of the “step”
“Repeating Sequence Stair” block is used to generate a
step sequence. It outputs the vector of parameter which has
specified value. “Repeating Sequence Stair” block in figure 5
is used for generating the information code which is set to (1 0
1). And the output waveform of it is shown below in figure
6.2:
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 1/z 1/z 1/z 1/z 1/z 1/z 1/z 1/z
Unit Unit Unit Unit Unit Unit Unit Unit
Delay Delay Delay Delay Delay Delay Delay Delay

XOR XOR
XOR 1/z 1/z 1/z 1/z
Logical Logical Unit
Reapting Logical Unit Unit Unit
operater operater Delay
Sequence operater Delay Delay Delay
Stair1

step1 switch3
switch5
switch6

1/z XOR 1/z 1/z

switch4
XOR
Figure.6.2 the step sequence 1/z Unit
Logical Unit Unit
Logical operater Delay Delay
Delay
Unit operater
Delay
The “Switch” block in figure 5 is a switch whose output
consists of the first input value(it will be called upper branch ADD XOR
NOT
in the later) and the third input value(it will be expressed by Logical Logical
Logical
operater
lower branch in the later). Its output is mainly determined by operater operater

the second input value. In Switch1, “Criteria for passing first Scope2

input” is set to “u2>=threshold” and “threshold” is set to 0. In

figure 5, when the simulating value is less than 3, the output of Figure.7 the decoding part of the (7,3) cyclic code
the “Step” value is 1 namely “u2=1” in “Switch1”.At present,
The code sequence generated in the “Repeating Sequence
because “u2>threshold”, the output is the upper branch of the
Stair” of figure 7 exists one bit of error: (1010100). The
input value namely the information code in the “sequence”.
sequence that this block has generated is used to imitate the
When the simulating value is greater than or equal to 3, the
received code group which comes from the receiver, where the
output value of“Step”block is -1 namely “u2=-1” in
sequence generated in the encoder transmits through the
“Switch1”. At present, because “u2<threshold”, the output is
communication channel. As shown in figure 7.1.
the lower branch of the input value namely the supervised
code calculated in the division circuit. Through the switch
selector, “switch” can make the whole sequence output in
order.

Figure.7.1 the simulate output sequence of the encoding

The 8 buffer shift register in figure 8 is a n buffer shift

Figure.6.3 the output wave of the encoder
Figure 6.3 shows the whole code group which is the
consequence of the information code outputted after passing
the encoder. The information code in this paper is set to (101),
then the output code group after passing the encoder is
(1011100), indicating that the supervised code of the input
code is (1100).
B. The Realize of The Error Correction System
The picture of the simulating circuit is shown as follows
(figure 7). It reflects the error detection and correction system
of cyclic code by using Simulink.
register in the principle figure 2. The class of the register is 8,
because there is delay time of a code period when the
receiving code group passes the syndrome calculator and
spontaneous calculator.
According to the principle of cyclic code decoding circuit
in Figure 7, S0S1S2S3 in the syndrome S is set as the initial
values of spontaneous calculator through the control gate. The
value of the syndrome calculator is sent one by one to the
spontaneous calculator through “step time”. The first data that
the syndrome calculator sends to spontaneous calculator is its
initial value 0000. From the second code period, the status
value that each code has been inputted into the syndrome
calculator is sent to the received code group. So, the value of
the “step time” in the“step” block should be set to 8. At the
end of the 8 code periods, switch selector is set to the lower
branch namely the spontaneous calculator starts a circulated
calculation in its internal from the 9th code periods. The
output code waveform corrected by the decoding system, as it
is shown in Figure 8.1 (obtained by “scope1” block), it is the
checked code group that the receiver received.

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 Figure.8.1 the output code group through the decoding system (1011100)
Figure 8.2 (obtained by “scope2” block) suggests that the
error code in the received code group detected by this
decoding circuit is the 4th code (this bit is high level), the
error pattern is expressed as (0001000).
Figure. 8.2 error pattern (0001000)
In order to observe and research how the error pattern
corrects the received error code group easily, the figure 8.1
and 8.2 are shown in one oscilloscope to display it clearly. It is
shown in figure 9. Putting the error code of high level 1 and
the received code group into a calculation of XOR to obtain
the correct input code group.
Figure.9 the combination of 8.1 and 8.2
IV. CONCLUSION
Cyclic code error correcting system (error detection and
correction) is designed by using the simulating environment of
Simulink in this paper. Through setting the various simulating
device parameters, it has reached the function of cyclic codes
system in encoding and decoding, so as to achieve the purpose
of error free transmission. Compared with the block codes,
cyclic codes decoding circuit using shift registers is much
simpler, so it is widely used.
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