International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
Effective Implementation of Edge Detection
Algorithm on FPGA and Beagle Board
D.Bindu Tushara
Department of ECE, V.I.T.S,
Hyderabad, Telangana , India
tushara.dewdrops@gmail.com
Abstract— Image processing is a major aspect in
transmission of data in compact fashion without loss of
information. There are several algorithms defined for image
compression, edge detection and noise reduction which form
image transformation techniques. The proposed paper focuses on
edge detection of given image using kernel matrix using sliding
window algorithm. The interface system includes FPGA and
beagle board which are connected through I2C.
Keywords— FPGA, beagle board, I2C, edge detection, kernel
matrix, sliding window algorithm, image transformation
techniques, image processing
I. INTRODUCTION
Image processing has opened the gateway for efficient
transmission of images through several different modules.
Implementation of such techniques is a major task for
successful output. This paper brings the two emerging
modules into one platform for performing edge detection on
the given image. There are already few existing working
models for edge detection using beagle board and A field-
programmable gate array separately. The paper mainly focuses
on the connectivity between the beagle board, FPGA through
I2C; algorithm for edge detection and process for the
transmission of the transformed image.
Edges are boundaries between different textures. Edge also
can be defined as discontinuities in image intensity from one
pixel to another. The edges for an image are always the
important characteristics that offer an indication for a higher
frequency. Detection of edges for an image may help for
image segmentation, data compression, and also help for well
matching, such as image reconstruction [4].
Field-programmable gate array are programmable digital
logic chips. A field-programmable gate array (FPGA) is
an integrated circuit designed to be configured by a customer
or a designer after manufacturing. The FPGA configuration is
generally specified using a hardware description
language (HDL), similar to that used for an application-
specific integrated circuit (ASIC).
Section 2 in the present paper deals with the process,
Section 3 and 4 presents the hardware and software
implementation. Section 5 illustrates the results and section 5
concludes the work.
978-1-4673-9939-5/16/$31.00 ©2016 IEEE
Dr.P.A.Harsha Vardhini
Department of ECE, V.I.T.S,
Hyderabad, Telangana , India
pahv19@rediffmail.com
II. IMAGE TRANSFORMATION TECHNIQUE
A. Edge Detection
Edges are the boundaries of an image with the equivalent
pixel intensity values. These values range between high to
moderate and low. The high intensity value results in addition
of noise to the original image, leading to distortion in image
while transmission. Edge detection is a process where the
edges of the images are detected to control this occurrence of
noise. The intensity values are with respect to the image pixels
depending on the type of image considered. The added
advantages for the edge detection include other image
transformation techniques for image enhancement.
B. Algorithm for edge detection
The image is considered as a matrix of pixel intensity
values of size NxM, ‘N’ representing the number of rows and
‘M’ representing number of columns. Edges of the image are
detected using sliding kernel matrix horizontally and vertically
on the input image matrix. The sliding kernel matrix is defined
by horizontal and vertical as shown in Fig 1 and Fig 2.
-1 -2 -1
0 0 0
1 2 1
Fig. 1. Horizontal kernel matrix
-1 0 1
-2 0 2
-1 0 1
Fig. 2. Vertical kernel matrix
The sliding kernel matrix is considered of size 3x3 which
is slided over the 3x3 matrices of NxM image matrix. The
matrices of horizontal with image matrix are multiplied with
output1 and multiplication of vertical matrix with image
matrix resulting in output2. These two outputs are compared
and the maximum value is considered as the edge that is
detected and the minimum value is neglected in the output
image. This process is shown in the form of a flow diagram as
shown in Fig 3.
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 Read input
image

Take 3x3 matrices M3X3 of

pixels leaving the corner values

Horizontal kernel matrix Horizontal kernel matrix

HK3x3 is considered VK3x3 is considered
values

OH = M3X3 X HK3X3 OV = M3X3 X VK3X3

yes
no
OH > OV

OH is maximum, detected as OV is maximum, detected as

edge and OV is neglected edge and OH is neglected

Fig. 3. Flow chart

III. HARDWARE IMPLEMENTATION

The hardware includes beagle board- xM for reading the

input and output images, FPGA to perform edge detection,
connectivity between these boards and display for the output.

A. Beagle Board
Beagle board is an open source software development
system with OMAP3530 system-on-a-chip. The board has
several specifications and features which makes the board
more flexible and user-friendly [1]. It also has expansion
block for other peripheral devices to be connected. The board
with specifications is as shown in Fig 4. Fig. 4. Beagle board with specifications

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B. FPGA
FPGA is cost effective board using the specifications to
reduce the system complexity and power consumption. Its
compatibility with image processing is comparatively
effective compared to other boards. The data is transmitted in
bit stream downloaded through PC with supporting Xilinx
software run on PC.
I2C plays a major role in the interface between the beagle
board and FPGA. The bus is drawn with DS1307 interface and
a microcontroller for reading and writing the data onto the
device peripherally connected [2]. This interface section with
I2C bus is as shown in Fig 7.

C. I2C
I2C is a bus which works under a protocol for the
transmission of bits in synchronous or asynchronous format.
This bus is specified with two lines: SCL (serial clock) and
SDA (serial data). SCL provides the necessary clock for the
start and stop of the bit transmission and the bit transmission is
done using SDA signal [3]. The start and stop condition is as
shown in Fig 5 and Fig 6

SDA

Fig. 7. I2C – FPGA module

SCL
D. Connectivity Between Beagle Board And FPGA Through
I2C
Fig. 5. START condition
FPGA acts as I2C bus in generating SCL and SDA signals
which are given to I2C port of the beagle board. Display is
connected to the beagle board for displaying the output and
another PC to FPGA for reading the input image. The block
SDA diagram depicting the connectivity between the boards is as
shown in Fig 8.

SCL

Fig. 6. STOP condition

PC

xilinx

SDA
FPGA SCL Display
(I2C Bus Beagle board
Master) Bus interface

SDA SCL
OUT

Fig. 8. Block diagram

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 V. OUTPUT & SIMULATION RESULTS
IV. SOFTWARE IMPLEMENTATION

A. Software required
• The Xilinx – performing edge detection
algorithm on PC and dumping the bitstream on to
the FPGA
• Keil C – to run on the microcontroller interface
and bus interface.
• Linux – support beagle board in reading through
SCL, SDA signals by I2C port and writing on to
the display through the port.

B. Working methodology
The input image is taken from the PC connected to FPGA
and algorithm is run using Xilinx software. The bitstream is
downloaded on to FPGA and by the interface unit, it is
transmitted to beagle board though I2C. With the help of
microcontroller interface, FPGA acts as I2C bus which
generates SCL and SDA. At the start condition of SCL, the bit
stream is transmitted through SDA and at the stop condition of
SCL, transmission stops. This transformed image is then read
by beagle board and the resultant image is displayed on the
display. The connectivity between the devices is as shown in
Fig 9.

Fig. 10. Transmitter window

Fig. 9. FPGA and Beagle board

Fig. 11. Receiver window

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The transformed image on the display is depicted in Fig 12. VI. CONCLUSION
Though several systems exists performing the edge
detection using FPGA, the proposed work gives the module of
edge detection using FPGA with beagle board connected
through I2C protocol. This system is effective in terms of the
efficiency of transmission, size of image transmitted and rate
of transmission. It is also cost effective reducing the
complexity in hardware by replacing multiple interface units
used for other modules.

References

[1] beagle board-xm reference manual

[2] Prof. Jai Karan Singh et al “Design and Implementation of I2C master
controller on FPGA using VHDL,” IJET, Aug-Sep 2012.
[3] I2C Bus Specification, Philips Semiconductor, version 2.1, January
2000.
[4] Mrs. S. Allin Christe “An Efficient Fpga Implementation Of MRI Image
Filtering And Tumour Characterization Using Xilinx System Generator”
International Journal of VLSI design & Communication Systems
(VLSICS) Vol.2, No.4, December 2011.

Fig. 12. Output image with edge detection

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