2017 First New Generation of CAS
Interface circuits based on FPGA for tactile sensor
systems
Ali Ibrahim, Luigi Pinna, Maurizio Valle
Department of Electrical, Electronic and Telecommunications Engineering and Naval Architecture (DITEN)
University of Genova
Genoa, Italy
ali.ibrahim@edu.unige.it
Abstract—Development of tactile sensing systems is motivated
by the possibility of application in many domains such as
robotics, prosthetics, and industrial automation. This paper
provides a functionality assessment of an interface electronic
circuit prototype for tactile sensing systems. The circuits are
based on the DDC112U and an FPGA Xilinx Spartan-6. An
experimental setup is carried out to measure the signals
generated from a single tactile sensor. Experimental results
validate the correct functionality of the proposed interface when
the measured voltage and charge are analyzed in terms of the
input force. Moving to the new system may pave the way towards
the fully integrated SoC for the e-skin development.
Keywords—electronic skin; tactile sensors; interface circuits;
sensor measurements;
I. INTRODUCTION
Technological advances have motivated the development of
electronic skin (e-skin) since it can be applied in many domains
such as prosthetics, robotics, and industrial automation. The e-
skin is an arrangement of tactile sensing materials, signal
conditioning and acquisition (interface circuit), signal
processing and interpretation. Thus, sensing materials should
be fabricated together with an interface circuits able to acquire
the tactile signals at the first place, then to transmit the
acquired data in order to be decoded. The interface circuit is in
charge of signal conditioning required to adapt the output
signal extracted from the sensor into voltage to be converted by
an analog to digital conversion circuit.
A functional block diagram of the tactile sensing system is
shown in Fig. 1. The tactile sensors represent the main
component of the system since the chosen materials for e-skin
development should reflect certain sensing capabilities to fulfill
the application domains requirements [1]. The piezoelectric
polymer films of Polyvinylidene Fluoride (PVDF) [2] is used
because it meets the above mentioned requirements.
When mechanical stimuli are applied to the surface of
tactile sensors, the interface circuits should carefully collect the
generated signals to preserve meaningful information contained
in raw data. These signals are progressively elaborated to
extract structured information employing an embedded
electronic system for tactile data decoding. Our main objective
is to develop the tactile sensing system as presented in Fig. 1,
integrating tactile sensors with different components of the
system embedded on a single system on chip (SoC).
978-1-5090-6447-2/17 $31.00 © 2017 IEEE
DOI 10.1109/NGCAS.2017.60
Fig. 1. Tactile sensing system
The interface electronics accommodates the circuits for
converting the generated electrical signals to voltage. It uses
capacitance to voltage converter in the systems with capacitive
sensors [3], or charge amplifier/charge integrator circuits when
targeting piezoelectric transducers [4]. Sampling signals is
usually applied sequentially using a multiplexer that scans the
channels one by one [5]. However, addressing simultaneous
sampling which allows to acquire a sample from all the sensors
in parallel is required when fast stimuli are applied [6].
Many recent researchers have addressed the development
of interface circuits for tactile sensors. A charge amplifier
circuit for signal conditioning, together with a 16 bit NI USB
6341 board for data acquisition have been used in [7]. Acer et
al. [8] proposed a design using TLV 2772 operational amplifier
for the signal conditioning of silicone embedded distributed
piezoelectric sensors. Authors in [9] proposed an interface
electronics consisting of PCB charge amplifiers for signal
conditioning, 4 channels ADC, two NI DAQ boards and
LabVIEW tool for data acquisition. However, such systems are
considered bulky due to their hardware complexity and could
not meet the restrictions (e.g. small space, light weight, low
power consumption) imposed by the application domains [10].
This paper focuses on digital serial interface
implementation based on FPGA device for a new interface
circuits for tactile sensors. It presents the functional evaluation
and tactile signal analysis of the interface circuit prototype
using Components-of-the-Shelf (COTS) devices. The circuit
adopts an analog to digital converter DDC112U from Texas
Instruments Inc. [11] and an FPGA Xilinx Spartan®-6. The
goal is to replace bulky systems with software free, scalable,
and small size interface circuits. Moving to the new system
represents a critical step towards full SoC integration for the e-
skin development. Experimental results validate the
functionality of the proposed circuits when the measured
voltage and charge have been analyzed in terms of the input
force.
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 Fig. 2. Interface circuits prototype with 4×4 tactile sensor array
The rest of this paper is organized as follows: Section II
describes the interface circuit prototype. The digital serial
interface system dealing with the A/D control, data retrieving,
and UART interface with the FPGA implementation are
reported in Section III. In Section IV, the experimental setup
and the results of the measurements are presented and assessed.
At last conclusions are drawn in Section V.
II. INTERFACE CIRCUITS PROTOTYPE
Fig. 2. illustrates the prototype of the interface circuit with
4×4 tactile sensor array. The DDC112 is a dual inputs
converter consisting of two identical input channels where each
performs the function of current to voltage integration followed
by a multiplexed analog to digital (A/D) conversion. Each
input has two integrators so that the current to voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma (ΔΣ) converter via
a four input multiplexer. With the DDC112 in the continuous
integration mode, the output of the integrators from one side of
both of the inputs will be digitized while the other two
integrators are in the integration mode [11]. This integration
and A/D conversion process is controlled by the system clock,
CLK. With a 10 MHz system clock, the integrator combined
with the delta sigma converter accomplishes a single 20 bits
conversion in approximately 220μs. The results from first side
(side A) and second side (side B) of each signal input are
stored in a serial output shift register. The DVALID output
goes low when the shift register contains valid data. Hence, a
specific digital serial interface is required to control the
integration time and the conversion phase, and also to retrieve
the converted data when available. This has been done using
ATLYS development board containing the Spartan®-6 FPGA
device.
III. DIGITAL SERIAL INTERFACE
The DDC112U deals with a digital synchronous serial
interface to provide the digital results. The serial interface
consists of a data clock (DCLK), an enable transmit pin
(DXMIT), a data valid pin (DVALID), a serial data output pin
Fig. 3. Block diagram of the digital serial interface.
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Fig. 4. Time diagram of the signals control and data retrieval.
(DOUT). The conversion process is alternating between the
two inputs of the DDC112 since it contains only one A/D
converter. The integration and conversion process is done
independently of the data retrieval process.
A. A/D Control and Data Retrieving
Fig. 3 shows the block diagram of the digital serial
interface between the DDC112U and the ATLYS FPGA
development board. The maximum sampling rate for the
DDC112U is 2 KSPS: it is controlled by the CONV signal
which allows a maximum integration time of 500μs. Fig. 4
shows the time diagram of the signals control and data
retrieval. Using a counter on the clock cycles of the FPGA
device (100 MHz), the FPGA sets the CONV signal which
allows the DDC112U to start integration. With the falling edge
of DVALID, the data from the last conversion is available for
retrieval. The falling edge of DXMIT in combination with the
data clock (DCLK) will initiate the serial transmission of the
data from the DDC112U. Data is retrieved from the DDC112
when DVALID falls and completed before the occurrence of
the next CONV transition from high to low or low to high.
The DVALID output goes low when the shift register of the
DDC112U contains valid data. Taking into consideration that
the DDC112U is converting at the maximum sampling rate
(Tint = 500μs), the time during which one retrieving operation
must be done is:
Treceive = Tint – t1– t2 (1)
Where t1 = 421.2 μs and t2 =10 μs are two fixed times when
the DDC112U work with frequency of 10MHz.
For that, Treceive = 500 – 421.2 – 10 = 68.8μs. Then the 40
clock cycle of the DCLK (for 40 bits) must be done before this
deadline:
TDCLK ≤ 68.8 /40 = 1.72μs
FDCLK ≥ 582 KHz (2)
TABLE 1
DIGITAL SERIAL INTERFACE IMPLEMENTATION RESULTS
Resources Utilization
Slice registers 215
Slice LUTs 214
Operating frequency (MHz) 198.7
Power consumption (mW) 21
 Fig. 5. Setup Measurements
To this end, selecting FDCLK = 2 MHz data retrieval process
is guaranteed without any risk of reaching the next CONV
transition. On the other hand, one bit of DOUT will be
available on each falling edge of DCLK. For that, the digital
interface retrieves the data on the rising edge of DCLK to
ensure a bit retrieving each clock cycle. Data are stored in Data
register having the length of 40 bits.
B. UART to USB Interface
In order to assess the functionality of the interface circuit,
and to analyze on PC the retrieved data from sensor signals
when a mechanical stimuli is applied, an UART to USB
interface has been implemented. Two different “ping-pong”
registers have been used: data_reg and temp_reg. When
data_reg is filled with the all 40 bits, data is stored into
temp_reg in order to free up data_reg to the next retrieving
operation. The temporary register temp_reg is in charge of
sending the data to the ATLYS board while data_reg deals
with the A/D interface. To send data in real time and to avoid
memorizing in the FPGA, data contained in the temporary
register (40 bits) have to be sent before the next retrieving
operation, such that:
TTX < Tint – 40 × TDCLK = 480 μs
Where TTX is the transmission time. The followed procedure
respects the time constraints, and sending data before the
arrival of the next converted data is guaranteed for a TTX = 370
μs.
(a)
Fig. 6. (a) Mean measured voltage vs Force and (b) Charge vs Force the four capacitance values under study.
C. Hardware Implementation
The digital serial interface has been implemented in VHDL
using Xilinx ISE Design Suite 14.7. Design has been
synthesized, placed and routed, and programmed to the
Spartan-6 XC65SLX45 FGG484 FPGA device. "XPower
Analyser" provided by ISE tool has been used in order to
analyze the power consumption of the CORDIC circuit.
Implementation results are reported in Table 1; it presents a
good performance in terms of hardware resources and power
consumption.
IV. EXPERIMENTAL SETUP AND MEASURMENTS
The measurements of the response of two tactile sensors are
presented in this work. The array consists of 4×4 tactile
sensors, from which only two sensors were directly connected
to the input of the DDC112U.
Fig. 5 illustrates the different instruments used for this
setup. The frequency generator controls the oscillation
frequency of the shaker which has been fixed to 27 Hz for the
current setup. A force sensor is mounted on the shaker to read
out the corresponding force value using LabVIEW tool. On the
other hand, when the shaker applies a mechanical stimulus on
the surface of tactile sensor, the generated electrical signal is
connected to the DDC112U board to be converted. As
(3)
described above, the FPGA is used to perform two different
tasks: 1) A/D control and data retrieving, and 2) the UART to
USB interface to send the converted data to MATLAB in order
to be elaborated. The work aims to study the feedback
capacitors of the DDC112U to analyze the performance when
(b)
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Fig. 7. d33 piezoelectric coefficient for the four capacitance values
under study.
dealing with single piezoelectric tactile sensor.
The tests were performed using four different ranges
corresponding to four feedback capacitors values of the
DDC112U (i.e. C = 12.5 pF, 25 pF, 37.5 pF, and 87.5 pF) [11].
These tests were carried out at the generated frequency of 27
Hz while the force amplitude varied from 0.05 to 5.5 Newton;
The FPGA device was connected to the PC using the UART to
USB interface, and data was collected using MATLAB as
described above. The collected data was normalized using the
following equation to have the voltage value for each measured
force amplitude:
Vn × MSB= d × Vmax
where Vn represents the normalized output voltage signal
value, Vmax is the maximum supply voltage which equals
4.09V in our case, MSB equals 220-1, and d is the 20 bit
collected data. DDC112U has a sampling frequency of 2
kSamples/s, and the data have been extracted for a duration of
5s which is equivalent to a data rate of 2k samples/s (10k
samples/5s).
The mean measured voltage and the charge response have
been plotted as function of force magnitude in Fig. 6 (a) and (b)
respectively. The results show a high order of linearity
presented by the voltage response of the single sensor when
converted by the DDC112. Moreover, the correspondence of
the charge values when varying the input force validates the
correctness of the interface circuits’ functionality.
The piezoelectric coefficient d33 has been calculated as
reported in [9]. It is illustrated as function of force magnitude
in Fig. 7. According to the plot, d33 has sparse values with
respect to the very low force magnitudes (0.05 N), with a quasi
linear behavior when increasing the force magnitude. The
obtained results concerning the piezoelectric coefficient show
correlation with the theoretical value of the d33 modelled in [9]
which validates the followed approach.
V. CONCLUSION
This paper presented an interface circuit based on FPGA
implementation for tactile sensor systems. It provided the
functional evaluation and analyzed tactile sensor signals when
applying mechanical force on its surface. Tactile signal
analysis has been provided when the proposed interface based
on DDC112U and an FPGA Xilinx Spartan®-6 is used.
Experimental results demonstrate the correct functionality of
the proposed system when the measured voltage and charge in
terms of the input force have been assessed. Future work will
consist on the implementation of the interface electronics with
DDC232/264 allowing high number of input channels. Such
interfaces will be able to deal with arrays of sensors having up
to 64 channels with the possibility to cascade a number of
circuits if a large area e-skin is targeted.
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