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Introduction
Prof. Peng Li
pli@tamu.edu
Ci1
Ci2
Cs1
Vin
Cs2
clk1 clk2
y1 Comparator
clk2 clk1 clk1 clk2 y2
clk2 clk1 d
Cf1 Cf2
d1 d2
clk1 clk2 clk1 clk2
clk2 clk1 clk2 clk1
D flip-flop
Q
_
Q
CLK1
design flow?
System-level Design
RTL-level Design
Transistor/Circuit
Level
Electrical &
Thermal Properties,
Delays, Waveforms, Layout
Parasitics Effects,
Coupling Noise … Final Verification
Nonlinear DC analysis
AC analysis
v 2 i f(v) v1 R v4
l l l
v C
l v3
d ( v1 v3 ) ( v1 v4 )
C f ( v2 v1 ) 0
dt R
■ If we do this for all N nodes:
F ( x(t ), x(t ), u (t )) 0 x(0) X
x (t ) N dimensional vector of unknown
node voltages
u (t ) vector of independent sources
F nonlinear operator
P. Li ECEN 751 Texas A&M University 6
Selected Topics
Elmore delay
Timing analysis
Intend to evaluate the circuit timing quickly
Crucial for large VLSI circuit synthesis/optimization
Provide delay estimation or waveform approximation using
easy-to-compute metrics or (approximated) timing simulation
R4
R1 R2 R3
C4
C1 C2 C3
TD 4 R1C1 C 2 C 3 C 4
R 2 ( C 2 C 3 C 4 ) R 4C 4
Process
Characterization
Interconnect
Gate Models
Delay
Calculators
SSTA
Statistical Opt.
Full Macromodeling
System Model
1.02
without LDOs
1 with 16 LDOs 1
0.98
1
0.96
Voltage (V)
0.94
0.95 0.95
0.92
0.9
0.9
0.88 200
200
100 100 150
0.86 50 0.9
0 0
0 1 2 3 4 5 6 7
Time (s) x 10
-8
Charge Loop
PFD VCO
Pump Filter
System level
optimization
up Vcontrol
Fref Fout
Frequency Charge Loop
VCO
detector pump filter
down
Ffb Frequency
divider