CS 251, Fall 2018, Assignment 3.0.

0
3% of course mark

Due Monday, November 05th, 5:30 PM

Lates accepted until 5:30pm November 06 with a 15% penalty

1. (5 points)
Consider the single-cycle computer shown on page 5 of this assignment. Suppose the
circuit elements take the following times: Instr mem: 200ps, Register read: 30ps,
Register write: 30ps, ALU and all adders: 50ps, Data memory: 200ps, Main Control
Unit: 10ps, ALU Control Unit: 5ps, Shift Left Units: 5ps.
Assume that PC and MUXes don’t take any time.
Compute the minimum execution time for each instruction type below:
R-format: ps.

LW: ps.

SW: ps.

Branch: ps.

Jump: ps.

2. (8 points)
Consider the assembly language instruction at memory address 25116:

25116: add $3,$6,$4

In the figure on the next page, there are eight darks lines. On each line, write in
the value that travels along the corresponding wire(s) when executing this assembly
language instruction. Note: you should write a decimal number on each dark line, and
not an expression involving things like ‘PC’, etc. (Some numbers are more natural to
write in binary; for any binary numbers you use, you should subscript them with a ’2’
like 1012 .)
Assume that each register $i (with i > 0) contains the decimal value 40010 + i. Further
assume that the shamt field of this R-format instruction is 0.

1
 0
M
u
x
(Question 2, continued)

Add ALU 1
result
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite

2
ALUSrc
RegWrite

Instruction [25 21] Read

PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction
[31–0] 0 Registers Read ALU ALU
M Write data 2 0 Address Read
result 1
Instruction u register M data
u M
memory x u
Instruction [15 11] Write x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]
3. (5 pts)
Consider the following MIPS assembly language instructions:

addi $1, $2, 100: addi $rt, $rs, immediate # add immediate
swr $1, 0($2): swr $rt, immediate($rs) # store word write register

These instructions are I-format instructions similar to the load word and store word
instructions. The addi and swr instructions store a computed value to the destina-
tion register $rt. The instructions do not require any physical hardware changes to
the datapath. The effect of each instruction is given below. Fill in the table below
indicating the value of all existing control lines necessary to execute the addi and swr
instructions on the datapath. You must use don’t cares where appropriate.

The swr instruction stores to memory and writes to the register file. It stores to
memory at address [$rs+$rt] the value contained in $rt. Also, it takes the sum of
the $rs and $rt registers and writes the result to register $rt. The new value of $rt is
updated at the end of the clock cycle. The immediate value in the swr instruction is
unused. You may assume it is zero.

addi: $rt <= se immediate + $rs

swr: MEM[$rs+$rt] <= $rt, $rt <= $rs + $rt

Type Reg ALU Mem Reg Mem Mem Branch ALU ALU
Dst Src ToReg Write Read Write op1 op0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
addi
swr

3
4. (8 points) We want to modify the single-cycle computer to implement the jump-register-
link instruction in the datapath. The jrl instruction is an R-format instruction which
has a unique opcode value. Therefore, you may assume the control unit will generate
a unique control signal for the jrl instruction. The form of this MIPS instruction is

jrl $rs

This instruction causes register PC to be assigned the value in register $rs and it stores
into $r31 the value of PC+4. Recall that PC is not modified until the end of the clock
cycle, therefore, we avoid any race conditions.

$r31 <= PC+4

PC <= $rs

(a) (5 pts) Modify the Single Cycle datapath on the next page in order to implement
the jrl instruction. You may add multiplexors, control bits and additional com-
ponents as needed. Marks will also be awarded for the efficiency of the solution.
Be sure that all other MIPS instructions executing on the datapath will still work.
Summarize your changes to the datapath below, and make the modifications to
the datapath provided on the next page.

(b) (3 pts) In the table below, give the settings of the control bits to implement the
new jrl MIPS instruction. Use Don’t Cares where appropriate. If you
need an extra control line to implement this instruction or if you need to increase
the number of bits in a control line, add additional columns to the table for the
new control line, split a column to increase the number of bits in a control line,
and in either case include a note below explaining the effect of the new/increased
control line(s) on the datapath and what its setting should be for other instruc-
tions. Make sure you do not break any other instructions. You should be able to
determine the purpose and effects of each of the control signals from the Single
Cycle datapath on the next page.
Type Reg ALU Mem Reg Mem Mem Branch ALU ALU Jump
Dst Src ToReg Write Read Write op1 op0
jrl

State the value(s) of any new control signal(s) for other MIPS instructions:

4
 Instruction [25–0] Shift Jump address [31–0]
left 2
26 28 0 1

PC+4 [31–28] M M
u u
x x
Add ALU 1 0
result
Add Shift
RegDst
Jump left 2
4 Branch
MemRead
Instruction [31–26]
Control MemtoReg
ALUOp

5
MemWrite
ALUSrc
RegWrite

Instruction [25–21] Read

PC Read register 1
address Read
Instruction [20–16] Read data 1
register 2 Zero
Instruction
[31–0] 0 Registers Read ALU ALU
M Write data 2 0 Address Read
result 1
Instruction u register M data
u M
memory x u
Instruction [15–11] Write x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15–0] Sign
extend ALU
control

Instruction [5–0]
5. (10 pts)
We want to modify the single-cycle computer to implement a new instruction in the
datapath. The mimm or memory immediate instruction is an I-format instruction.
The form of this MIPS instruction is

mimm rt, offset(rs)

This instruction computes the sum of the signed extended offset and rs, and stores this
at the address stored in rt. You may assume that the mimm instruction has a unique
opcode value.

Mem[rt] <= se offset + rs

(a) (6 pts) Modify the Single Cycle datapath on the next page in order to implement
the mimm instruction. You may add multiplexors, control bits and additional com-
ponents as needed. Marks will also be awarded for the efficiency of the solution.
Be sure that all other MIPS instructions executing on the datapath will still work.
Summarize your changes to the datapath below, and make the modifications to
the datapath provided on the next page.

(b) (4 pts) In the table below, give the settings of the control bits to implement the
new mimm MIPS instruction. Use Don’t Cares where appropriate. If you need
an extra control line to implement this instruction or if you need to increase the
number of bits in a control line, add additional columns to the table for the new
control line, split a column to increase the number of bits in a control line, and in
either case include a note below explaining the effect of the new/increased con-
trol line(s) on the datapath and what its setting should be for other instructions.
Make sure you do not break any other instructions. You should be able to deter-
mine the purpose and effects of each of the control signals from the Single Cycle
datapath on the next page.
Type Reg ALU Mem Reg Mem Mem Branch ALU ALU Jump
Dst Src ToReg Write Read Write op1 op0
mimm

State the value(s) of any new control signal(s) for other MIPS instructions:

6
 Instruction [25–0] Shift Jump address [31–0]
left 2
26 28 0 1

PC+4 [31–28] M M
u u
x x
Add ALU 1 0
result
Add Shift
RegDst
Jump left 2
4 Branch
MemRead
Instruction [31–26]
Control MemtoReg
ALUOp
MemWrite
ALUSrc

7
RegWrite

Instruction [25–21] Read

PC Read register 1
address Read
Instruction [20–16] Read data 1
register 2 Zero
Instruction
[31–0] 0 Registers Read ALU ALU
M Write data 2 0 Address Read
result 1
Instruction u register M data
u M
memory x u
Instruction [15–11] Write x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15–0] Sign
extend ALU
control

Instruction [5–0]
 Additional exercises on single-cycle architecture: The rest of the course will focus
on improvements to the single-cycle architecture. Before proceeding, you may wish to do
some additional exercises from the textbook (unmarked, solutions not provided):

• Exercise 3.21

• Exercise 4.1

• Exercise 4.2

• Exercise 4.3