module dfw(

input [3:0]password,
input clk,reset,
input [1:0]state,
input sensor_1,sensor_2,
output reg gate
);
always@*
begin
case(state)
2'b00:
begin
gate=0;
end

2'b01:
if(sensor_1)
if(password==5'b0000)
begin
gate=1;
end
else
gate=0;

2'b10:

if(sensor_2)
begin
gate=1;
end
else
gate=0;

2'b11:
if(sensor_1)
begin
gate=1;
end
else if(sensor_2)
gate=0;
else if(password==5'b0001)
begin
gate=1;
end
else
gate=0;

endcase
end
endmodule