IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO.
1, JANUARY 2017 139
Efficient Designs of Multiported Memory on FPGA
Bo-Cheng Charles Lai, Member, IEEE, and Jiun-Liang Lin
Abstract— The utilization of block RAMs (BRAMs) is a critical
performance factor for multiported memory designs on field-
programmable gate arrays (FPGAs). Not only does the excessive
demand on BRAMs block the usage of BRAMs from other parts
of a design, but the complex routing between BRAMs and logic
also limits the operating frequency. This paper first introduces
a brand new perspective and a more efficient way of using a
conventional two reads one write (2R1W) memory as a 2R1W/4R
memory. By exploiting the 2R1W/4R as the building block, this
paper introduces a hierarchical design of 4R1W memory that
requires 25% fewer BRAMs than the previous approach of dupli-
cating the 2R1W module. Memories with more read/write ports
can be extended from the proposed 2R1W/4R memory and the
hierarchical 4R1W memory. Compared with previous xor-based
and live value table-based approaches, the proposed designs can,
respectively, reduce up to 53% and 69% of BRAM usage for
4R2W memory designs with 8K-depth. For complex multiported
designs, the proposed BRAM-efficient approaches can achieve
higher clock frequencies by alleviating the complex routing in an
FPGA. For 4R3W memory with 8K-depth, the proposed design
can save 53% of BRAMs and enhance the operating frequency
by 20%.
Index Terms— Block RAM (BRAM), field-programmable gate
array (FPGA), multiported memory, performance.
I. I NTRODUCTION
F IELD-PROGRAMMABLE gate arrays (FPGAs) have
been broadly used in fast prototyping of complex digital
systems. FPGAs contain programmable logic arrays, usually
referred to as slices [4]. Slices can be configured into different
logic functions. The flexible routing channels can support data
transferring between logic slices. In addition to implementing
logic operations, if needed, the slices can also be used as
storage elements, such as flip-flops, register files, or other
memory modules. Due to the increasing complexity of digital
systems, there is a growing demand for in-system memory
modules. Synthesizing a large number of memory modules
would consume a significant amount of slices, and would
therefore result in an inefficient design. The excessive usage
of slices could also pose a limiting factor to the maximum
size of a system that can be prototyped on an FPGA.
To more efficiently support the in-system memory, modern
FPGAs deploy block RAMs (BRAMs) that are hardcore
memory blocks integrated within an FPGA to support
Manuscript received September 26, 2015; revised January 21, 2016
and March 21, 2016; accepted April 26, 2016. Date of publication
June 8, 2016; date of current version December 26, 2016. This work
was supported by the Ministry of Science and Technology, Taiwan, under
Grant MOST 104-2622-8-009-001.
B.-C. C. Lai is with the Department of Electronics Engineer-
ing, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail:
bclai@mail.nctu.edu.tw).
J.-L. Lin is with MediaTek Inc., Hsinchu 30076, Taiwan (e-mail: qazhph-
phphp3@gmail.com).
Digital Object Identifier 10.1109/TVLSI.2016.2568579
1063-8210 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
efficient memory usage in a design. Compared with the
storage module synthesized by slices, BRAMs are more
area and power efficient while at the same time achiev-
ing higher operating frequencies. An FPGA usually deploys
multiple BRAMs with the same specification. For example,
Xilinx Virtex-7 XC7V585 FPGA contains 795 36-kb BRAMs,
and each BRAM can be configured as two port mode or
dual-port mode [4]. Designers can utilize these memory
blocks to implement the in-system storage module of a design.
Multiported memories, which allow multiple concurrent
reads and writes, are frequently used in various digital designs
on FPGAs to achieve high memory bandwidth. For exam-
ple, the register file of an FPGA-based scalar MIPS-like
soft processor [3] requires one write port and two read
ports. Processors that issue multiple instructions require even
more access ports. The shared cache system among multiple
soft processors on FPGA should support multiple concurrent
accesses. A routing table in a network switching function
would also need to enable multiple accesses in order to
support multiple requests from different ingress ports. Time-
multiplexing and task scheduling are alternative solutions to
support multiple accesses. However, these schemes would
usually cause more complex designs with many corner cases
and therefore requiring extra effort of verification. Having
a generic multiported memory module can greatly ease the
design when a system really needs to provide concurrent data
accesses. This concern becomes more important especially
when FPGAs are usually used for quick prototyping and
functional verification.
Although the current FPGA design tools can automatically
synthesize the multiported memory by configuring slices, this
approach has been demonstrated to be considerably ineffi-
cient in terms of the utilization of slices [1]. The increasing
logic depth also becomes a limiting factor to the maximum
operating frequency. Designs of multiported memories that
leverage BRAMs [1]–[3] have been proposed to attain better
utilization of FPGA resources as well as system perfor-
mance. BRAMs in an FPGA can support two access ports
that can be used as either a read or a write port. With
this basic specification, it requires extra effort if designers
would like to implement a storage module that supports
more concurrent access ports than the existing BRAMs.
Compared with the multiported memory designs that only
utilize slices, the previous approaches with BRAMs [1]–[3]
have demonstrated less total equivalent area while achieving
higher frequencies.
The limited quantity and capacity of BRAMs have posed
severe concerns to designers when implementing multiported
memories on an FPGA. Using an excessive amount of BRAMs
140 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
for multiported memory could seriously restrict the usage
of BRAMs for other parts of a design. Furthermore, the
insufficient BRAMs would force designers to synthesize the
storage modules with slices, and further consume a vast
amount of slices as well as limiting the maximum operat-
ing frequency of the design. For example, given BRAMs
with a size of 36 kb [5], design methodologies proposed
in [2] and [3] require a total of 80 BRAMs to implement
a 4R2W (four read ports and two write ports) memory with a
32-bit data width and 8K-depth. The same memory module
demands 64 BRAMs for the designs in [1] and [3]. Our
previous work [9] introduced a two reads one write (2R1W)
module based on XOR-encoded values and demonstrated bet-
ter performance with fewer BRAMs compared with [1]–[3].
However, these designs still occupy more than half of
the available BRAMs on some modern FPGAs, such as
Zynq-7015 and 7020 [5], [9]. The issue is aggravated when the
design requires huge internal storage capacity. Having a more
efficient design of multiported memories, therefore, remains
an imperative design concern for modern digital systems
on FPGAs.
This paper aims at efficient designs of multiported memory
on FPGAs. The main contributions of this paper are as follows.
This paper first introduces a brand new perspective of using a
2R1W module as either a 2R1W or a 4R module, denoted as a
2R1W/4R memory. Second, by exploiting the versatile usage
mode of the proposed 2R1W/4R memory, this paper proposes
a hierarchical design of 4R1W memory. This hierarchical
4R1W design requires 25% fewer BRAMs than the approach
of duplicating the 2R1W module used in [9]. Memories with
more read/write ports can be extended from the proposed
2R1W/4R memory and the hierarchical 4R1W memory. Third,
the experiments in this paper have extensively explored various
design parameters, including the numbers of read and write
ports, and different depths of multiported memory modules.
Compared with XOR-based and live value table (LVT)-based
designs from previous approaches, the proposed designs can,
respectively, reduce up to 53% and 69% of BRAM usage for
4R2W memory designs with 8K-depth. For complex multi-
ported designs, the proposed BRAM-efficient approaches can
achieve higher clock frequencies by alleviating the complex
routing in an FPGA. For 4R3W memory with 8K-depth, the
proposed design can save 53% of BRAMs while at the same
time enhance the operating frequency by 20%. This paper also
explores the impact of different bank organizations in a design.
This paper shows that, for a 4R3W memory with 32-bit data
width and 8K-depth, a proper bank organization could achieve
a 16% BRAM reduction, a 21% higher frequency, and a 27%
lower slice utilization. The results present great potential for
future design refinement that could be achieved by optimizing
the bank organizations.
This paper is organized as follows. Section II discusses the
previous design approaches of multiported memory on FPGAs.
Section III proposes the 2R1W/4R memory and the hierar-
chical 4R1W memory that achieve more efficient multiported
memories on FPGAs. Section IV shows the experimental
results and comparisons between different works. Section V
draws conclusions.
TABLE I
T ECHNIQUES OF M ULTIPORTED M EMORY ON FPGA
II. R ELATED W ORKS
To implement a multiported memory on an FPGA, two types
of design techniques are required, namely increasing read
ports and increasing write ports. Table I lists the techniques
proposed by previous works for multiported memories on
FPGAs. The approach of replication [1], [3] enables multiple
read ports by replicating the data on multiple BRAMs. This
technique uses low complexity of control logic, but requires
excessive usage of BRAMs. LVT, which is implemented by
synthesizing slices on FPGA, enables multiple write ports by
duplicating BRAMs and tracking which BRAM stores the
latest value of an address. The other approach to increase write
ports is referred to as XOR-based [2]. Different from LVT,
which uses a table to track the location of the latest value, the
XOR-based design duplicates BRAMs and encodes the stored
data with XOR operations. The target data can be retrieved by
applying the XOR again. In general, the XOR-based approach
can achieve a higher operating frequency, but requires more
BRAMs than the LVT approach.
Note that this paper focuses on architectural solutions to
achieve multiple accesses for a general memory that takes
requests at the current cycle and returns results in the next
cycle. Users of the multiported memory can be completely
ignorant of the details of memory designs. There are other
works focusing on enabling multiple accesses for specific
types of storage elements, such as register files [6]–[8]. They
enable concurrent reads with an approach similar to repli-
cation, but avoid write conflicts by renaming the registers
with software approaches, such as compiler or assembler.
These approaches, which tackle specific storage functions and
involve effort of users, are not in the scope of this paper.
The following sections will provide more in-depth discus-
sions about implementations and design concerns of these
techniques. To facilitate a more general discussion, the fol-
lowing paragraphs use a memory bank to refer to a standalone
memory module used as a building block to implement a mem-
ory system. A memory system usually consists of multiple
banks. The memory space, also referred to as memory depth,
is distributed across the banks. When designing a memory
system on FPGAs, a BRAM can be used to support the com-
plete memory space. BRAMs can also be deployed as banks
to enable larger memory space or higher access bandwidth.
A. Techniques to Increase Read Ports
Replication is a widely adopted technique to increase read
ports [1], [3]. This technique enables multiple read ports
LAI AND LIN: EFFICIENT DESIGNS OF MULTIPORTED MEMORY ON FPGA
Fig. 1. (a) Replication technique that replicates BRAMs to support m read
ports. (b) Example of a memory design that can support two concurrent reads
with two BRAMs M0 and M1 . The read R1 is accessing M0 at address 2,
while the read R2 is accessing M1 at address 3.
by replicating the data to multiple BRAMs. When there are
multiple reads, each of these reads will be directed to a distinct
BRAM to access the target data without conflicting with other
reads. The data between these BRAMs should be updated
simultaneously. When there is a write to an address, this write
needs to be routed to every BRAM and updates the data to
the corresponding address in each BRAM.
Fig. 1(a) illustrates how multiple read ports are enabled
by the replication technique. Assume a multiported memory
design supporting m concurrent reads. Each Mi , where i is
from 0 to m−1, is a BRAM module. The data in M0 are
replicated to other BRAMs (M1 to Mm−1 ) in order to support
multiple concurrent reads R0 to Rm−1 . When there is a
write W0 , the write request is routed to the write ports of
all the BRAMs and updates the values at the corresponding
address of each BRAM simultaneously. Fig. 1(b) shows an
example of a memory that can support two concurrent reads.
In this example, there are two data stored in the BRAMs,
where data A are at address 2, and data B are at address 3.
When the memory receives two read requests R0 and R1
accessing addresses 2 and 3, respectively, each read request
can access one of the BRAMs and avoid conflicting with each
other. In this way, the memory with two BRAMs M0 and M1
can support two simultaneous reads.
The main advantage of replication is its simplicity without
requiring complex control logic; however, it needs to replicate
m times the number of memory modules, where m is the
number of read ports supported by the target multiported
memory design.
B. Techniques to Increase Write Ports
There are two types of techniques that have been used
to increase write ports in a multiported memory design
on FPGAs. The first technique applies LVT. This technique
utilizes multiple replicated BRAMs to enable multiple con-
current writes. Different write ports are connected to differ-
ent BRAMs. A table, called LVT, is used to track the correct
BRAM that stores the most up-to-date data of an address.
The second technique uses an XOR-based scheme to enable
multiple write ports. The XOR-based technique encodes the
stored data by using XOR operations, and retrieves the correct
141
Fig. 2. (a) LVT technique that supports n write ports. The design replicates
nBRAMs and uses an LVT to track the most up-to-date value of each address.
(b) Example of a memory design that can support two concurrent writes with
LVT technique. This figure shows the initial state of the memory module
before the two writes W0 and W1 . W0 is going to address 5 in BRAM M0
while W1 is going to address 7 in BRAM M1 . (c) For the same example, this
figure shows the memory state after completing the W0 and W1 requests.
data by applying the XOR again. The following paragraphs
will elaborate the details of these techniques.
LVT is a technique proposed in [1] and [3] to support
multiple write ports on FPGAs. Fig. 2(a) illustrates the data
access flow of the LVT design that enables n concurrent
write requests. The memory is replicatedn times with BRAMs
M0 to Mn−1 . In Fig. 2, each BRAM Mi , where i is from
0 to n − 1, can support one write port. Since multiple writes
would update different memory addresses, an additional block
LVT is implemented to keep track of the location of the latest
value of a memory address. Fig. 2(b) illustrates an example
when there are two write requests W0 and W1 . W0 writes
data A to address 5, while W1 writes data B to address 7.
In this example, W0 stores data A to BRAM M0 , and W1
stores data B to BRAM M1 . Each BRAM is associated with
an identification number defined by designers. This paper
simply uses the serial number of a BRAM as its identification
number. Then the writes W0 and W1 will, respectively, update
the LVT with identification numbers of the BRAMs that
keep the latest data. As shown in Fig. 2(c), the identification
numbers for M0 and M1 (values 0 and 1) are updated to the
entries 5 and 7, respectively, in the LVT. After the LVT is
updated, the following read request R0 will query the LVT
to select the correct BRAM that stores the latest value of the
target data.
142 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
Fig. 3. XOR-based memory design that can support two simultaneous writes
W0 and W1 and one read R0 . A write will store an encoded value of both
the new and stale data. A read can recover the most recent value of the target
address by applying the XOR operation again.
The XOR-based approach proposed in [2] is a way to
increase write ports without a table. Fig. 3 illustrates an
XOR-based memory design that can support two simultaneous
writes W0 and W1 and one read R0 . The design contains a total
of four BRAMs where each BRAM is assumed to support one
read and one write. The XOR-based design encodes the stored
data by using XOR operations. For example, when W0 stores
a new value Anew , the Anew will be XOR-ed with the stale
value Astale at the same memory address from the two bottom
BRAMs. The XOR-ed value of the two instances (Anew ⊕Astale )
will be stored to the two top BRAMs in Fig. 3. Similarly, the
write W1 will XOR the values Bnew and Bstale and store the
encoded value to the two bottom BRAMs in Fig. 3.
With the encoded values, the read R0 can recover the most
recent value Anew by XOR-ing the two values from the two
BRAMs on the right of Fig. 3. The value-recovering operation
is also shown in (1). The XOR-based approach can achieve
multiple writes without requiring a table to track the position
of the most recent value. However, this approach needs n 2
memory modules to enable a design with n writes and one
read
R0 = (Anew ⊕ Astale ) ⊕ Astale = Anew .
C. Integrating the Read/Write Techniques
A general multiported memory needs to support multiple
read ports and multiple write ports simultaneously. The respec-
tive techniques for reads and writes discussed in the previous
sections therefore should be integrated in a design to support
both multiple read ports and write ports. This section uses
examples to discuss how these techniques can be integrated to
enable a multiported memory design.
Fig. 4 illustrates the integrated design proposed
in [1] and [3]. The design combines the techniques of
replication and LVT to support two reads (R0 and R1 ) and
two writes (W0 and W1 ). The multiple writes are handled
by the LVT, while the multiple reads can be serviced by the
replicated BRAMs. The basic building block shown in Fig. 4
is a BRAM2 module M2i . By composing two basic BRAMs,
each BRAM2 module applies the replication technique
introduced in Fig. 1 to support 2R1W. Fig. 4(a) shows the
architecture of this design. Each write is associated with
Fig. 4. (a) Example of a 2R2W memory that integrates both replication and
LVT techniques. (b) Initial state of the multiported memory. W0 is going to
address 2 in BRAM2 M20 while W1 is going to address 3 in BRAM2 M21 .
R0 reads address 0 and R1 reads address 1. (c) Memory state after completing
all the reads and writes (W0 , W1 , R0 , and R1 ).
one of the BRAM2 modules. For example, W0 is connected
to M20 while W1 is connected to M21 . When there is a read
request, the read will query the LVT to locate the correct
BRAM2 module that stores the latest value and retrieve the
correct target data from the BRAM2 module.
Fig. 4(b) and (c) use an example to show the data flow
of this integrated design. In Fig. 4(b), the write W0 updates
the value C to address 2 while W1 stores the value D to
address 3. The reads R0 and R1 are retrieving the data from
(1)
address 0 (value A) and address 1 (value B), respectively.
These four accesses (W0 , W1 , R0 , and R1 ) are sent to the
memory simultaneously. The reads try to identify the correct
BRAM2 modules that have the most recent values of the
target data. After querying the LVT, the most recent values
for R0 (address 0) and R1 (address 1) are both located
at M20 . Recall that each BRAM2 is a 2R1W module. The
two reads (R0 and R1 ), in this example, will both access M20 .
Meanwhile, the two writes W0 and W1 will, respectively, store
the data to M20 and M21 , and update the LVT. Fig. 4(c) shows
the memory state after completing the requests of all the reads
and writes.
Fig. 5 shows the approach adopted in [2] that combines
replication and XOR-based to support two reads (R0 and R1 )
and two writes (W0 and W1 ). Note that each building block
in Fig. 5 is also a BRAM2 module that can support 2R1W.
Fig. 5(a) shows the initial state of the 2R2W memory. Fig. 5(b)
shows the data flow of two reads and two writes. R0 reads both
the values Astale and A ⊕ Astale from address 2 at two BRAM2
modules, and recovers A by XOR-ing these two values.
LAI AND LIN: EFFICIENT DESIGNS OF MULTIPORTED MEMORY ON FPGA
Fig. 5. Example of a 2R2W memory that integrates both replication and
XOR-based techniques. (a) Initial state of the memory module. W0 is going
to address 0 while W1 is going to address 1. R0 reads address 2 and
R1 reads address 3. (b) Memory state after completing all the reads and writes
(W0 , W1 , R0 , and R1 ).
R1 can recover B with a similar flow. The operations of reads
are shown in the following equations:
R0 = (A ⊕ Astale ) ⊕ Astale = A
R1 = (B ⊕ Bstale ) ⊕ Bstale = B.
At the same time, W0 reads value Cstale from three BRAMs
at the bottom of Fig. 5(b), and updates the encoded value
Cnew ⊕ Cstale to address 0 of the three BRAMs on the top of
Fig. 5(b). W0 can update the values at address 1 with a similar
flow.
Recall that each BRAM2 is a 2R1W module. In this
2R2W design, each write needs to first read all of the stale
values from BRAM2 modules and update the XOR-ed values.
Therefore, the design in Fig. 5 needs a total of six BRAM2
modules to provide sufficient internal read ports and support
all the data accesses. Each read port of the multiported
memory needs to occupy two internal read ports of a BRAM2
module. Overall, a mRnW replication-XOR-based memory
needs n × (n − 1 + m) BRAM2s.
III. P ROPOSED D ESIGN
This section proposes efficient solutions to implement mul-
tiported memories on FPGAs. Unlike the replication method
in [1] and [3], the approach proposed inthis paper supports
multiple reads with XOR operations, while multiple writes
can be enabled using additional BRAMs. A remap table is
143
Fig. 6. Example of a 2R1W memory implemented by BDX technique.
(a) Supporting multiple reads with XOR operations. (b) Supporting a write
request in the two-cycle pipeline architecture.
added to track the location of the correct data. The main
memory architecture is similar to that of our previous work
introduced in [9]. On top of the main architecture, this paper
introduces a brand new perspective of using a 2R1W module
as either a 2R1W or a 4R module, denoted as a 2R1W/4R
memory. By applying the 2R1W/4R, this paper exploits the
versatile usage mode and proposes a hierarchical XOR-based
design of 4R1W memory that requires fewer BRAMs than
previous designs. Memories with more read/write ports can
be supported by extending the proposed 2R1W/4R memory
and the hierarchical 4R1W memory.
A. Techniques to Increase Read Ports
1) Bank Division With XOR Design Scheme: Bank
Division With XOR (BDX) is an approach to increase read
(2) ports proposed in [9]. Unlike the method used in [1] and [3],
BDX avoids replicating the storage elements of the whole
(3)
memory space. With BDX, multiple reads can be supported by
using the XOR operations. Note that BDX is different from the
XOR-based design in [2]. The XOR-based approach in [2] uses
XOR operations to increase write ports by storing the encoded
data to maintain the data coherence between memory modules.
BDX uses XOR operations to increase read ports by retrieving
the target data from the encoded value.
Fig. 6 illustrates an example of a 2R1W memory imple-
mented with the BDX scheme. As shown in Fig. 6(a), the
memory space is distributed to four data banks (banks 0–3).
One XOR-bank is added to keep the XOR values of the data
banks. Each of these memory banks is assumed to be a 2RW
module that can support two reads, or two writes, or one
read and one write. This is the dual-port mode supported
by the BRAMs in Virtex-7 FPGA. Compared with the dual-
port mode of BRAMs, the BDX scheme in Fig. 6 enables
one more read port. Therefore, the BDX design becomes a
2R1W memory module which can support two reads and one
write concurrently. The XOR-bank stores the XOR-ed value of
all the data at the same offset in every data bank. The XOR
operation for this example is shown in (4). Pn represents the
value stored at offset n of the XOR-bank. D(m,n) represents the
144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
Fig. 7. Example of mR1W memory implemented with multiple
2R1W modules.
data at offset n of bank m. Since there are four data banks in
the example shown in Fig. 6(a), the value at the same offset
(offset n) of each bank (banks 0–3) will be XOR-ed and stored
to the same offset (offset n) at the XOR-bank
Pn = D(0,n) ⊕ D(1,n) ⊕ D(2,n) ⊕ D(3,n) . (4)
As shown in Fig. 6(a), two reads R0 and R1 are both going
to bank 1. In this example, one read (R0 ) will access the data
directly from bank 1 (R0 = D(1,0) ). Due to the bank conflict,
the other read R1 cannot access bank 1. Instead, the target
data of R1 can be recovered by XOR-ing the values at the
same offset of the other data banks as well as the XOR-bank.
As shown in the following equation, the target data at offset n
of data bank 1 can be recovered by XOR-ing the values at
the same offset (offset n) from banks 0 to 3, as well as the
XOR-bank:
D(1,n) = D(0,n) ⊕ D(2,n) ⊕ D(3,n) ⊕ Pn . (5)
The write request in this example is implemented in the
two-cycle pipeline architecture. As illustrated in Fig. 6(b), at
the first cycle W0 writes the data D(1,n) directly to bank 1.
At the same cycle, the data at the same offset of the other
banks [D(0,n) , D(2,n) , and D(3,n) ] together with D(1,n) are read
and XOR-ed. At the second cycle, the XOR-ed value will be
written back to the XOR bank at offset n. With the pipeline
architecture, this design can process one write request every
cycle.
The 2R1W memory introduced previously only needs an
additional XOR-bank that requires the same storage size of
each data bank. In this case, assume all the data banks are of
equal size. The number of memory entries in the XOR-bank
is MemoryDepth/#DataBanks, where MemoryDepth represents
the total number of memory entries in the memory space
and #DataBanks denotes the number of data banks in the
multiported memory.
To support more than two read ports, BDX needs to deploy
multiple 2R1W memories. Fig. 7 shows an example of mR1W
memory. Each 2R1W module supports two out of m reads.
In this way, all the m reads can be serviced concurrently
by multiple 2R1W modules. Note that when implementing a
multiported memory on FPGAs, replicating memory modules
could significantly increase the usage of the limited BRAMs
on an FPGA. To address this issue, this paper proposes a
new architecture to increase read ports, referred to as hier-
archical bank division with XOR (HBDX). HBDX applies
Fig. 8. Two modes of 2R1W/4R module. The module is implemented with
four data banks and one XOR-bank. (a) 2R1W mode. (b) 4R mode.
a new perspective of using a 2R1W module as a 2R1W/4R
module. Section III-A2 will discuss the 2R1W/4R module
while Section III-A3 will introduce the design of HBDX.
2) 2R1W/4R (An Efficient Two-Mode Memory): To imple-
ment HBDX in an efficient way, this paper introduces a brand
new perspective of using a 2R1W module as either a 2R1W
or a 4R module. This new way of using the 2R1W module is
denoted as 2R1W/4R. This hybrid module can support either
2R and 1W or 4R. Note that the 2R1W/4R module uses exactly
the same design as the 2R1W module introduced in Fig. 6.
Fig. 8 illustrates how the two modes work. Fig. 8(a) shows
the 2R1W mode. When there is a write request W0 , this design
can support up to two conflicting reads. The write request W0
stores the data directly to the target data bank, and reads all
the data at the same offset from the other data banks (Rupdate )
to update the XOR-bank. Fig. 8(b) shows the 4R mode. This
mode only works when there is no write request. In this case,
the design can support up to four conflicting reads. Consider
one of the worst cases when all the four reads (R0 to R3 ) are
going to bank 0. As illustrated in Fig. 8(b), R0 and R2 access
bank 0 directly. At the same time, R1 and R3 can retrieve the
target data by XOR-ing the values at the same offset of the
other data banks as well as the XOR-bank.
3) HBDX Designs With 2R1W/4R Module: Fig. 7 illus-
trates a design scheme that can support more read ports by
replicating the 2R1W module. However, this design scheme
could significantly increase the usage of the limited BRAMs
on an FPGA. To achieve a more BRAM-efficient design, this
paper proposes HBDX, which adopts a hierarchical structure
that organizes the 2R1W to achieve 4R1W without replicating
the 2R1W module. To further enhance the design, HBDX in
this section leverages the 2R1W/4R scheme introduced in the
previous section as the basic building module to implement
a 4R1W module.
Fig. 9 illustrates a 4R1W memory design by using the
HBDX scheme. In this 4R1W design, each basic building
block is a 2R1W module of the BDX scheme introduced in
Fig. 6. According to the 2R1W/4R memory proposed in the
previous section, this 2R1W module can be used as either a
2R1W or a 4R module. The HBDX in Fig. 9 will utilize this
versatile usage mode to achieve a more efficient 4R1W design.
LAI AND LIN: EFFICIENT DESIGNS OF MULTIPORTED MEMORY ON FPGA 145

Fig. 10. Example of a 1R2W memory implemented with BDRT technique.

Fig. 9. HBDX 4R1W implemented with 2R1W/4R modules. (a) According to the remap table, both W0 and W1 are going to bank 0.
The null entries in BRAMs are the entries that do not store any valid data.
(b) Final state of the multiported memory after completing the two writes
Consider one of the worst cases when all the 4R and 1W W0 and W1 .
are going to bank 0. Two read requests, R0 and R1 in this
example, would read directly from bank 0. The other two read
requests, R2 and R3 , would read the same offset from the
other data banks (banks 1–3) and the XOR-bank to recover
the target data. And the write request W0 can be supported
with a pipeline architecture similar to the one shown in the
example of Fig. 6(b). In this case, W0 stores the data directly
to bank 0. The data at the same offset of the other data banks
are read and XOR-ed at the same cycle. The XOR-ed value
will be stored back to the XOR bank in the next cycle. In this
example, bank 0 is used in the 2R1W mode, while other banks
are used in the 4R mode.
The HBDX-based 4R1W memory has demonstrated to be
more BRAM efficient than the previous approach of simply
Fig. 11. Architecture that integrates HBDX and BDRT to achieve a mRnW
duplicating the 2R1W module [9]. Section IV will more memory.
comprehensively discuss the design concerns between the
number of BRAMs and operating frequency on an FPGA. Compared with the LVT approach used in previous works,
the BDRT requires smaller storage space. The extra cost of
B. Techniques to Increase Write Ports BDRT is the additional registers to implement the remap table.
The required number of these extra registers is shown in the
Bank division with remap table (BDRT) is an approach to
following equation, where MemoryDepth is the total number of
increase write ports proposed in [9]. Unlike the LVT design
memory entries in the memory space and #DataBanks denotes
used in [1] and [3], BDRT avoids replicating the whole
the number of data banks in the multiported memory:
memory space and supports multiple writes using additional
BRAMs and a remap table to track the location of the # of registers for remap table
latest data. Fig. 10 shows an example of the design for = (log2 (# Data Banks + 1) − 1) × Memor y Depth. (6)
a 1R2W memory. This example consists of two data banks
(banks 0 and 1), one bank buffer, and a remap table. The Null
entries in a memory bank are the entries that do not store any C. Integrating the Read/Write Techniques
valid data. When receiving W0 and W1 , these requests will This section shows the design of a multiported memory that
first look up the remap table to identify the correct BRAM that integrates HBDX and BDRT. Fig. 11 shows an architecture
stores the latest data. According to the remap table, W0 and W1 that uses HBDX and BDRT to implement an mRnW memory.
are, respectively, going to address 0 and address 1 in bank 0. This memory architecture is divided into k data banks. Based
In this case, W0 will store the value directly to address 0 in on BDRT, to support all the writes, there require total n − 1
bank 0. W1 will be directed to the bank buffer whose offset 1 bank buffers. A hash mechanism is added to distribute the
is a Null entry. At the same time, the remap table needs to writes to banks.
be updated to reflect the modified location of W1 , as shown 1) Example of 2R2W Memory: Fig. 12 shows an example
in Fig. 10(b). The address 1 of the remap table stores the of 2R2W memory that applies this architecture. In Fig. 12(a),
value 2 which is the identification number of the bank buffer. assume there are two write requests and two read requests.
This state of remap table shows that the data of address 1 is The writes W0 and W1 are going to addresses 0 and 1,
now stored in the bank buffer. respectively. The reads R0 and R1 are retrieving the data from
146 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
Fig. 12. Example of a 2R2W memory that integrates BDX and BDRT.
(a) Initial state of the memory module. W0 is going to address 0 while W1 is
going to address 1. R0 reads address 2, and R1 reads address 3. (b) Memory
state after completing the W0 , W1 , R0 , and R1 .
addresses 2 and 3, respectively. Each bank is a 2R1W module
that can support two read ports and one write port. The 2R1W
module can be implemented with BDX as illustrated in Fig. 6.
A read request will access all the banks and choose the data
returned by the bank that stores the latest value of the target
data based on the record in the remap table. The two write
requests, W0 and W1 , will look up the remap table for the
correct banks to store the values. In this example, the addresses
of the two writes, addresses 0 and 1, both belong to bank 0.
In this case, W0 will store the value directly to bank 0. W1 will
be directed to a bank buffer that has a Null entry at the same
offset of W1 on bank 0. At the same time, the remap table
needs to be updated to reflect the modified location of W1 , as
shown in Fig. 12(b).
2) Extend to 4RnW Memory With 2R1W/4R Module: This
section further extends the design to a 4RnW memory. Accord-
ing to the architecture presented in Fig. 11, a 4RnW memory
requires 4R1W modules as building blocks. A 4R1W mod-
ule can be implemented simply by the replication technique
introduced in [1], [3], and [9].
This paper proposes a more efficient way of implementing
a 4RnW memory by using the 2R1W/4R module introduced
in this paper. Although supporting two different usage modes,
a 2R1W/4R module is essentially a 2R1W memory block in
terms of design cost and performance. As will be shown in
Section IV, compared with the 4R1W module from replication,
the 2R1W/4R module on an FPGA requires fewer BRAMs and
attains higher operating frequencies.
Fig. 13 shows a 4RnW memory implemented with k data
banks and using 2R1W/4R as the building block. The four
reads can be supported by exploiting the 4R mode of the
2R1W/4R module. Note that a 2R1W/4R module cannot
support any write requests when it is servicing more than two
reads. To support n write requests, this design needs n extra
bank buffers to solve conflicting write requests. More detailed
results and comparisons will be discussed in Section IV.
IV. E XPERIMENTAL R ESULTS
This section compares the cost and performance of the
proposed multiported memory designs with approaches from
Fig. 13. 4RnW memory that integrates HBDX and BDRT, and applies
2R1W/4R modules as building blocks.
TABLE II
D IFFERENT D ESIGNS OF M ULTIPORTED M EMORY
previous works. Section IV-A introduces the FPGA platform
used in this paper and the experimental setup. Section IV-B
uses 4R2W memory as the design target to compare the
maximum operating frequencies and slice utilization of dif-
ferent design approaches. Section IV-C further extends the
discussions to designs for a 4R3W multiported memory.
Section IV-D discusses the impact of increasing write ports
and memory depth and Section IV-E explores the impact of
different bank organizations, and presents the great potential of
future design refinement that could be achieved by optimizing
the bank organizations. Section IV-F summarizes important
observations and design concerns of the proposed multiported
memory.
A. Experimental Environment
To have fair comparisons, we implemented the works
of [1]–[3] on the same FPGA platform. All the multiported
memory designs are listed in Table II. The target FPGA plat-
form is Virtex-7 XC7V585 FPGA that contains 795 BRAMs
and 91 050 slices [4]. Each BRAM is 32-bit data width by
1K-depth, and can be configured as two-port mode (supporting
one read and one write), or dual-port mode (supporting two
reads, or two writes, or one read and one write). A slice
contains four 6-input look-up tables, eight registers, and
multiplexers. The design environment is based on Xilinx
ISE 14.2. The synthesis tool is set to favor clock frequency.
The data width is 32 bit for all the multiported designs in this
paper. The designs of multiported memory assume no stalls.
LAI AND LIN: EFFICIENT DESIGNS OF MULTIPORTED MEMORY ON FPGA
TABLE III
P ERFORMANCE AND C OST OF D ESIGNS FOR 4R2W M EMORY W ITH 8K-D EPTH AND 16K-D EPTH
All the requests will be completed within one cycle. The
timing analysis is performed between input registers and
output registers of the multiported memory.
B. Designs for 4R2W Memory
Table III compares the 4R2W multiported designs with
8K and 16K memory depth. Table III lists the performance
and cost of these designs, including the numbers of BRAMs,
operating frequencies, and slice utilization. Each entry in
a multiported memory is 32 bit. Based on the results in
Table III, the multiported designs can be generally categorized
into two types based on how the multiple read ports are
supported. The first type enables multiple read ports with
mapping tables [1], [3], such as LVT-based and BDRT-based
designs. The second type enables multiple read ports without
mapping tables [2], such as the XOR-based designs. Since the
mapping table helps tracking the correct location of the most
recent data, designs with mapping tables usually require fewer
BRAMs to implement a multiported memory. However, these
designs would cause lower operating frequencies due to the
need for table lookups and more complex control mechanisms.
On the other hand, designs with replication techniques (no
mapping tables) can achieve higher operating frequencies, but
demand more BRAMs on an FPGA. Note that both types of
designs, as discussed in Section III-B, still use table-lookup
to implement multiple write ports.
For 4R2W designs with 8K-depth, compared with the
XOR-based designs (including XOR-based, XOR-based_BDX,
and XOR-based_HBDX) that require no mapping tables,
LVT-based designs (including LVT-based, LVT-based_BDX,
LVT-based_HBDX) have lower frequencies due to the more
complex logic and circuit routing. The proposed BDX and
HBDX modules can help reducing the number of BRAMs.
Using the proposed BDX and HBDX as the building blocks in
the LVT-based and XOR-based designs, the number of BRAMs
can be reduced by 30%–53% with minor increase in slice
utilization. The operating frequencies, however, are degraded
by around 5% after adopting the BDX and HBDX modules.
This is mainly because BDX and HBDX implement more
complex logic. The connections between BRAMs and output
multiplexers also increase the critical path of the designs.
147
For BDRT-based designs, using 2R1W/4R as the build-
ing blocks will reduce the usage of BRAMs by 33.3%
compared with the previous designs with 4R1W building
blocks. Compared with LVT-based design, the BRAM usage
of BDRT-based designs can be reduced up to 69%. However,
the operating frequencies of BDRT-based designs become
16%–19% slower. This is because the 4R2W design using
2R1W/4R has to check the possible conflicts for all the six
memory requests (four reads and two writes). The multiported
memory designs with original 4R1W building modules only
need to check the two writes since every 4R1W building block
can serve four reads and one write. The extra bank buffer of
BDRT-based designs also requires more slices to implement
the remap table, and further limits the maximum operating
frequency.
For 4R2W designs with 16K-depth, replacing the basic
memory modules with BDX and HBDX modules in
XOR-based designs can reduce the number of BRAMs
by 30%–42.5%. The operating frequencies are degraded
by 11%–17% due to the longer critical paths posed by BDX
and HBDX.
There is an interesting observation when LVT-based_BDX
and LVT-based_HBDX reduce BRAM usage by 37.5%–53%
while at the same time achieving 10% faster clock fre-
quency compared with the original LVT-based design [1], [3].
This is mainly because the excessive number of slices required
by the original LVT-based design has considerably compli-
cated the routing on the target FPGA. The complex rout-
ing becomes a limiting factor to the maximum operating
frequency. BDX and HBDX modules, although being more
complex compared with previous basic memory modules, can
actually help reducing the number of BRAMs in a mul-
tiported memory design on an FPGA. The fewer BRAMs
alleviate the routing congestion and result in faster clock
rates.
C. Designs for 4R3W Memory
Table IV extends the comparisons with 4R3W designs with
8K and 16K memory depth. To support three write ports,
the XOR-based design needs to occupy enormous BRAMs
on the target FPGA. Complex connections from BRAMs to
148 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
TABLE IV
P ERFORMANCE AND C OST OF D ESIGNS FOR 4R3W M EMORY W ITH 8K-D EPTH AND 16K-D EPTH
the output ports, in the XOR-based design, have become a
serious limiting factor to the maximum operating frequency.
For 4R3W with 8K-depth, using BDX and HBDX in the
XOR-based design can greatly reduce the number of BRAMs
by 37.5% and 48%, respectively. The fewer BRAMs also
make the routing less complex and therefore help enhanc-
ing the operating frequency by 13%. Similar results can be
found for LVT-based 4R3W designs with 8K-depth. Reducing
the usage of BRAMs would alleviate the complex routing
in the original LVT-based design. The proposed BDX and
HBDX modules can reduce BRAM usage by 37.5%–53% in
LVT-based designs, and further enhance the operating fre-
quency by 20%.
For 4R3W designs with 8K-depth, compared with
LVT-based_BDX and LVT-based_HBDX, the BDRT-based
design can further reduce the BRAM usage while keeping a
comparable operating frequency. However, the slice utilization
has increased rapidly after applying the 2R1W/4R as the
basic building block. The BDRT-based_2R1W/4R occupies
almost all the available slices and is barely routable in the
target FPGA. This is because the design with 2R1W/4R
needs three extra banks to solve the possible write con-
flicts. The BDRT-based design deploys two banks while
the BDRT-based_2R1W/4R requires total five banks. For
BDRT-based_2R1W/4R, each entry in the remap table now
requires 3 bits, instead of 2 bits in the BDRT-based design.
Compared with the BDRT-based design, which adopts original
4R1W as the basic building block, the BDRT-based_2R1W/4R
reduces the number of BRAMs by 37.5%, but results in a 56%
lower operating frequency.
The designs for 4R3W with 16K-depth have occupied more
slices and more BRAMs than designs with 8K-depth. The
operating frequencies of the designs have dropped due to the
more congested usage of slices and complex routing among
BRAMs and logic. For XOR-based designs of 4R3W with
16K-depth, the BDX and HBDX reduce the usage of BRAMs
by 37.5% and 48%, respectively. BDX and HBDX also help
achieve 17% higher frequency than the original XOR-based
design due to less complex routing.
For designs of 4R3W with 8K-depth, LVT-based_BDX
and LVT-based_HBDX require fewer BRAMs compared with
LVT-based. However, for LVT-based_HBDX, the lower usage
of BRAMs does not provide as much frequency benefit
as in previous cases. LVT-based_HBDX results in a 18%
slower operating frequency than the LVT-based design that
requires more BRAMs. This is mainly because the already
congested usage of slices in the 4R3W design (almost 70% for
LVT-based_HBDX) has limited the opportunity for timing
refinement. The more sophisticated decision-making mecha-
nism in HBDX further aggravates the timing issue. Although
using fewer BRAMs, LVT-based_HBDX designs for 4R3W
with 16K-depth still result in a longer critical path than the
original LVT-based design.
Note that the design of BDRT-based_2R1W/4R cannot be
properly synthesized for the 4R3W memory with 16K depth
because the number of slices required by the design has
already exceeded the available slices on the target FPGA.
D. Impact of Write Ports and Memory Depth
As shown in Tables III and IV, increasing write ports would
significantly increase the slice utilization. This situation is
even more apparent for designs that enable multiple read ports
with mapping tables, such as LVT-based and BDRT-based
designs. This is because the mapping tables are synthesized
by the registers and connections in slices of FPGAs. Having
large mapping tables would not only occupy slices, but also
introduce more complex decision logics and routing. Extra
consumption of slices also blocks the usage of slices by
other logic modules, and would consequently impact on the
overall timing of the design. The experimental results have
also revealed that when the slice utilization approaches the
capacity of the target FPGA, the timing degradation could be
very significant.
Increasing the memory depth introduces linear impact
on the usage of BRAMs. According to the experimental
results, growing the memory depth from 8K to 16K requires
twice the number of BRAMs. The slice utilization is also
increased approximately by two times. But again, the operating
LAI AND LIN: EFFICIENT DESIGNS OF MULTIPORTED MEMORY ON FPGA
TABLE V
P ERFORMANCE I MPACT OF D IFFERENT BANK O RGANIZATIONS
FOR BDRT-B ASED _2R1W/4R D ESIGN OF 4R3W
M EMORY W ITH 8K D EPTH
frequency will drop considerably when the design approaches
the slice capacity of the target FPGA and causes routing
congestion.
E. Impact of Bank Organizations
As noted in the previous section, BDRT-based_2R1W/4R
requires more than 100% slice utilization on the target FPGA,
and cannot be implemented. But BDRT-based_2R1W/4R does
provide advantage of lower BRAM usage. This section takes
BDRT-based_2R1W/4R as a design example, and explores
the potential of design refinement that could be achieved by
optimizing the bank organizations.
Table V lists two different bank organizations for the BDRT-
based_2R1W/4R design of 4R3W memory with 8K-depth.
The nominal implementation used in the previous sections
of this paper adopts a two-data-bank organization, shown
in the second row of Table V. The third row of Table V
lists the results of a four-data-bank design. Together with
the three bank buffers, the four-data-bank design involves a
total of seven banks. Both the two-data-bank and four-data-
bank designs need three extra bank buffers, and require 3 bits
for each entry in the remap table. However, when changing
the design from two-data-bank to four-data-bank, the depth
of each bank is reduced from 4K to 2K. The depth of the
remap table is also shrunk from 8K+4K×3 to 8K+2K×3.
Compared with the original two-data-bank design, the four-
data-bank design has demonstrated a 16% BRAM reduction, a
21% higher frequency, and a 27% lower slice utilization. This
result clearly demonstrates a great opportunity to attain further
performance enhancement by tuning the bank organization.
This will be a major study in our future research.
F. Summary of Multiported Designs
This section summarizes important observations and design
concerns of the proposed multiported memory. First, the
integrated multiported memory design can provide higher
throughput than the time-multiplexing (TMX) based designs.
Table VI compares the throughput of different designs
for 4R2W memory. XOR-based (4R2W) is the XOR-based
4R2W design proposed in this paper. TMX(2R1W) uses the
replication-based 2R1W design [1], [3] and applies the time-
multiplexing scheme to achieve 4R2W. Here we assume the
time-multiplexing scheme induces zero latency overhead and
can run at the same clock frequency as the original 2R1W
design. Therefore, for TMX(2R1W), it takes two cycles to
serve four reads and two writes. As shown in Table VI, the
XOR-based designs run at slower clock rates than the
149
TABLE VI
T HROUGHPUT OF XOR -BASED 4R2W M EMORY AND
T IME M ULTIPLEXING (TMX) BASED 4R2W M EMORY
TMX(2R1W) designs. However, XOR-based designs can
achieve higher total throughput than the time-multiplexing
designs.
Second, to attain the most benefit, users need to properly
choose between designs that support multiple reads with and
without mapping tables. As demonstrated previously, multi-
ported designs with mapping tables can more efficiently utilize
the BRAMs, but would suffer from lower operating frequen-
cies due to more complex routing. The timing issue is further
aggravated when the size and complexity of the multiported
design approaches the capacity of the target FPGA. Therefore,
users would prefer designs with mapping tables when the
target FPGA contains abundant slices and relatively scarce
BRAMs. If the number of slices becomes a design constraint,
users should favor designs without mapping tables in order to
avoid the possible performance degradation due to insufficient
slices and congested connections.
Third, a proper bank-organization can enable further per-
formance enhancement. As shown in Section IV-E, different
bank organizations result in disparate performance. Refining
the bank organization would attain performance enhancement
and worth further exploration.
And fourth, the current designs still require table-lookups to
support multiple writes. A design with mapping tables would
limit the maximum operating frequency. We are currently
developing a technique to support multiple writes without
mapping tables. This technique would avoid the issue of con-
gested routing and potentially enhance the overall performance
of the multiported designs.
V. C ONCLUSION
This paper proposes efficient BRAM-based multiported
memory designs on FPGAs. The existing design methods
require significant amounts of BRAMs to implement a mem-
ory module that supports multiple read and write ports.
Occupying too many BRAMs for multiported memory could
seriously restrict the usage of BRAMs for other parts of
a design. This paper proposes techniques that can attain
efficient multiported memory designs. This paper introduces
a novel 2R1W/4R memory. By exploiting the 2R1W/4R as
the building block, this paper proposes a hierarchical design
of 4R1W memory that requires 33% fewer BRAMs than the
previous designs based on replication. Memories with more
read/write ports can be extended from the proposed 2R1W/4R
memory and the hierarchical 4R1W memory. Compared with
XOR-based and LVT-based approaches, the proposed designs
can, respectively, reduce up to 53% and 69% of BRAM
150 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 1, JANUARY 2017
usage for 4R2W memory designs with 8K-depth. For complex
multiported designs, the proposed BRAM-efficient approaches
can achieve higher clock frequencies by alleviating the
complex routing in an FPGA. For 4R3W memory with
8K-depth, the proposed design can save 53% of BRAMs while
at the same time enhance the operating frequency by 20%.
This paper also demonstrates the importance of applying an
appropriate bank organization in a memory design. It is shown
that a multiported design with proper bank organization could
achieve a 16% BRAM reduction, a 21% higher frequency,
and a 27% lower slice utilization. The results present great
potential of future design refinement that could be achieved
by optimizing the bank organizations.
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Bo-Cheng Charles Lai (M’09) received the
B.S. degree in electronics engineering from National
Chiao Tung University, Hsinchu, Taiwan, in 1999,
and the M.S. and Ph.D. degrees in electrical
engineering from the University of California at
Los Angeles (UCLA), Los Angeles, CA, USA,
in 2003 and 2007, respectively.
He was with Broadcom Corporation, Irvine, CA,
USA, from 2007 to 2009. He joined National Chiao
Tung University in 2009, where he is currently an
Associate Professor with the Department of Elec-
tronics Engineering. His current research interests include parallel computing,
multicore architecture, low power designs, and embedded systems.
Dr. Lai received the scholarship from the John Deere Foundation in 2003.
During his study at UCLA, he won Design Automation Conference student
design contest in 2003 and 2005.
Jiun-Liang Lin received the M.S. degree in
electronics engineering from National Chiao Tung
University, Hsinchu, Taiwan, in 2015.
He is currently a Digital Design Engineer with
Mediatek Inc., Hsinchu. His current research inter-
ests include designs and optimizations of multi-
ported memory and field-programmable gate array.