Heavy Load Light Load Using Synchronous Buck Boost Converter

ABSTRACT

A novel dual-mode control scheme is developed here to enable synchronous buck converters
(SBC) to operate in a continuous conduction mode under heavy-load conditions and in a
discontinuous conduction mode under light-load conditions. When an SBC operates in a
discontinuous conduction mode, a quasi-resonant valley switching technique can be employed to
turn on a synchronous switch, perform zero-voltage switching at main switches, and improve the
light-load efficiency. The proposed scheme does not require the addition of an auxiliary circuit in
the SBC, providing it with the advantages of low cost and easily built-in integrated circuits. To
verify its feasibility, an SBC equipped with the proposed control scheme is de veloped, with
output voltage and output power of 5 V and 25 W, respectively.

1
 CHAPTER 1
INTRODUCTION

This project is aimed at A novel dual-mode control scheme is developed here to enable
synchronous buck converters (SBC) to operate in a continuous conduction mode under heavy-
load conditions and in a discontinuous conduction mode under light-load conditions. When an
SBC operates in a discontinuous conduction mode, a quasi-resonant valley switching technique
can be employed to turn on a synchronous switch, perform zero-voltage switching at main
switches, and improve the light-load efficiency. The proposed scheme does not require the
addition of an auxiliary circuit in the SBC, providing it with the advantages of low cost and
easily built-in integrated circuits. To verify its feasibility, an SBC equipped with the proposed
control scheme is developed, with output voltage and output power of 5 V and 25 W,
respectively. The buck–boost converter is a type of DC-to-DC converter that has an output
voltage magnitude that is either greater than or less than the input voltage magnitude. Two
different topologies are called buck–boost converter. Both of them can produce a range of output
voltages, from an output voltage much larger (in absolute magnitude) than the input voltage,
down to almost zero. The first one is the inverting topology. The output voltage is of the opposite
polarity than the input. This is a switched-mode power supply with a similar circuit topology to
the boost converter and the buck converter. The output voltage is adjustable based on the duty
cycle of the switching transistor. One possible drawback of this converter is that the switch does
not have a terminal at ground; this complicates the driving circuitry. Neither drawback is of any
consequence if the power supply is isolated from the load circuit (if, for example, the supply is a
battery) because the supply and diode polarity can simply be reversed. The switch can be on
either the ground side or the supply side. The next topology is a buck (step-down) converter
followed by a boost (step-up) converter. The output voltage is of the same polarity of the input,
and can be lower or higher than the input. Such a non-inverting buck-boost converter may use a
single inductor which is used for both the buck inductor and the boost inductor. One of the major
trends in power electronics is increasing the switching frequencies. The advances in
semiconductor fabrication technology have made it possible to significantly improve not only

2
voltage and current capabilities but also the switching speed. The faster semiconductors working
at high frequencies result in the passive components of the converters – capacitors, inductors
and transformers – becoming smaller thereby reducing the total size and weight of the
equipment and hence to increase the power density. The dynamic performance is also improved.
This frequency elevation is responsible for the growing importance of pulse-width modulation on
the one hand and for the use of resonance on the other hand. Another important trend resides in
reduction of voltage and current stresses on the semiconductors and limitation of the conducted
and radiated noise generated by the converters due large di/dt and du/dt. Both these
requirements, size and noise, are minimized if each switch in a converter utilizes soft switching
technique to change its status. This paper presents the work of the new buck-boost converter that
provides zero-voltage turn-on and zero current turn-off. This is more useful than purely ZCS or
ZVS operation.

Literature Survey
1.1 High-efficiency, low-voltage dc–dc conversion for portable applications
Author: A. Stratakos
The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into
anoutput supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the
output voltage at1.6 V. For the low load currents the PFM feedback control is used and for the
higher load currents the PWMfeedback control is used. This converter can supply load currents
from 0 to 300 mA with efficiency above 85%.The static line regulation of the system is < 0.1%
and the load regulation of the system is < 0.3%. A digital soft-start circuit is implemented in this
system. The system also includes the capability to trim the output voltage in ~14 mV steps
depending on the 4-bit input digital code.

1.2 A high efficiency dual-mode buck converter IC for portable applications,

Author: W. R. Liou, M. L. Yeh, and Y. L. Kuo
This paper presents the design of a novel wide output current range dual-mode dc to dc step-
down (Buck) switching regulator/converter. The converter can adaptively switch between
pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high
conversion efficiency. Under light load condition the converter enters PFM mode. The function

3
of closing internal idle circuits is implemented to save unnecessary switching losses. The
converter can be switched to PWM mode when the load current is greater than 100 mA. Soft
start operation is designed to eliminate the excess large current at the start up of the regulator.
The chip has been fabricated with a TSMC 2P4M 0.35 mum polycide CMOS process. The range
of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery
supply applications. The maximum conversion efficiency is 95% at 50 mA load current. Above
85 % conversion efficiency can be reached for load current from 3 to 460 mA.

1.3 Spur reduction design of frequency-hopping dc–dc converters

Author: Akshat Shukla, Dhananjay Hedaoo, Manoj B. Chandak, Veena Prakashe, Abhijeet
Raipurkar

This paper presents an inductor current average control (ICAC) method that minimizes the
undesirable transient glitches in dc-dc converters using a frequency-hopping pulsewidth
modulation control. The analysis in this paper shows that without careful control of the
frequency-hopping instant for the dc-dc converters, the transient glitches can be rather large in
magnitude and may interfere with the modulated signal to be transmitted from a mobile
communication device. The ICAC technique selects the frequency-hopping instant such that the
average inductor current is undisturbed when the switching frequency hops. The measurement
result shows that the ICAC technique can suppress the transient spurs by 14.1 dB and the voltage
of the transient glitches by 65.3%.

1.4 Block Diagram for Electronic notice board

4
 Fig: 1.1 BLOCK DIAGRAM FOR DC TO DC CONVERTER

CHAPTER 2
DC-DC Converter Fundamentals
This chapter introduces switching regulators and the requirements imposed on these regulators

by the portable environment. Design equations and closed-form expressions for losses are

presented for the three basic low-voltage CMOS switching regulator topologies - buck, boost,

and buck-boost - controlled via pulse-width or pulse-frequency modulation. Also introduced are

alternative, inductor-less regulator topologies which have advantages in a specialized class of

portable applications.

2.1 Introduction to Switching Regulators

The switching regulator shown in Figure 3.1 converts an unregulated battery source voltage Vin
to the desired regulated DC output voltage Vo. A single-throw, double-pole switch chops Vin
producing a rectangular wave having an average voltage equal to the desired output voltage. A
low-pass filter passes this DC voltage to the output while attenuating the AC ripple to an

5
acceptable value. The output is regulated by comparing Vo to a reference voltage, Vref, and
adjusting the fraction of the cycle for which the switch is shorted to Vin. This pulse-width
modulation (PWM) controls the

Average value of the chopped waveform, and thus controls the output voltage. Unlike a

switched-capacitor converter (see Section 3.6.2) a switching regulator has efficiency.

Which approaches 100% as the components are made more ideal? In practice, efficiencies above

75% are typical, and efficiencies above 90% are attainable.

There are several simple alternative arrangements of the switching and filter components that

can be used to produce an output voltage larger or smaller than the input voltage, with the same

or opposite polarity. Some of these will be discussed below. However, many of the design issues

are similar, so first one topology, the step-down (buck) converter, will be discussed in more

detail.

Buck Convert

The power train of the low-output-voltage buck circuit, which can produce any arbitrary output
voltage 0 £ Vo £ Vin , is given in Figure 3.2. The basic PWM operation is as follows: The power
transistors (pass device Mp and rectifier Mn) chop the battery input voltage Vin to reduce the
average voltage. This produces a square wave of variable duty cycle D and constant period Ts =

6
fs-1 at the inverter output node, vx. A typical periodic steady-state vx(t) waveform is shown in
Figure 3.3. The second-order low-pass

filter (Lf and Cf) passes the desired DC component of this chopped signal, while attenuating the
AC to an acceptable ripple value. In the ideal case, the DC output voltage is given by the product
of the input voltage and the duty cycle:

The switching pattern of Mn and Mp is pulse-width modulated, adjusting the duty cycle of the
rectangular wave at vx, and ultimately, the DC output voltage, to compensate for input and load
variations. The pulse-width modulation is controlled by a negative feedback loop, shown in the
block diagram of Figure 3.1, but omitted from Figure 3.2 for simplicity. Some detail on ultra-
low-power PWM design is included .

2.2 DC-DC Requirements in Portable Systems

Figure 3.4 summarizes the primary requirements of DC-DC converters in portable

electronic systems. The following subsections elaborate on these requirements.

7
2.2.1 High Energy Efficiency

Since battery capacity is limited in any portable electronic device, power minimization is crucial.

DC-DC converters must dissipate minimal energy to extend system run-time, a requirement

which is particularly challenging in the low-voltage and low-current applications common to a

battery-operated device. In the portable multimedia Infopad terminal, the six voltage converters

are the dominant source of power dissipation, consuming 42% of the total system power

[Truman98].

A number of power management schemes are used in most low-power hardware: Unused

circuitry is powered-down and gated clocks are employed to reduce power consumption during

idle mode [Chandrakasan94b]. Such techniques may present severe load variations (up to several

orders of magnitude), and the system may idle for a large fraction of the overall run-time. This

implies the need for a high conversion

Efficiency not only under full load, but over a large load variation. Furthermore, in the ultra-low-
power applications common to portable systems, the quiescent operating power (control power)
of the regulator must be kept to an even lower level to ensure that it does not contribute
significantly to the overall dissipation. For example, a multimedia chipset has been demonstrated
in [Chandrakasan94a] which supports speech I/O, pen input and full motion video, and consumes
less than 5 mW at 1.1 V. The control circuit for a converter supplying this chipset must have
substantially lower quiescent power Section 3.3.2 and Section 3.4.2 summarize the fundamental
mechanisms of loss in the low-voltage CMOS buck converter. Chapter 4 introduces a number of
techniques at the power system and circuit levels to improve the energy efficiency of these
converters. At the power system level, resource sharing between converters is used to minimize
control system overhead. Low-voltage digital control which exploits existing sub-system
voltages is proposed to further reduce control power. A number of power train circuit
optimizations for high efficiency at ultra-low output voltages are presented.

2.2.2 Low Cost

8
As portable electronic devices become increasingly sophisticated, and a greater variety of
technologies are integrated into a single system, their voltage conversion needs grow. While
successive generations of high performance digital ICs demand progressively lower-voltage
supplies, analog and data conversion chips continue to require higher voltages for headroom and
signal distortion considerations. In addition, 3.3 V, 5 V, and 12 V standards remain in most
systems for backward compatibility to existing components.

Cost is often the primary consideration in consumer electronics. A high-performance DC-DC

converter, including the IC and all external components, can cost as much as nine dollars1. Since
as many as six DC-DC converter outputs may be required in a portable electronic device
[Truman98], the overall power system may contribute substantially to the overall cost of the
device.

High levels of functional integration, as proposed in Chapter 4, can be used to reduce the cost of
the power system. Current-day DC-DC converters require as many as ten external components.
The design methodology presented in Chapter 4 reduces this number to three: One input bypass
capacitor, and an output filter inductor and capacitor. In addition, the methodology allows for the
integration of several power supplies on a single IC, further reducing cost. Finally, since vanilla
digital CMOS integration is proposed, small custom power supplies can be integrated together
with their own digital CMOS loads.

Nevertheless, regardless of the number of supplies integrated on a single chip, each DC-DC
converter output requires its own external filter elements. These components, particularly the
inductor, can be quite expensive. In Chapter 4, high operating frequencies are proposed to reduce
the values of these elements, thereby reducing their cost. In addition, a “minimum inductor”
design is presented to trade decreased inductance for increased capacitance, resulting in an
overall lower cost.

Small Size

The portability requirement places severe constraints on physical size and mass. Since several
DC-DC converters are required in almost any portable electronic device, minimization of the
physical size of each is a key design objective. The six voltage converters in the Infopad terminal
consume 12% of the printed circuit board surface area [Truman98]. In addition, the large

9
inductors in DC-DC converters often determine the height of end-products such as cellular
phones and pagers.

The techniques described in Section 3.2.2 for power system cost reduction are equally effective
in reducing overall power system size. Higher levels of functional integration can be used to
minimize external component count. Integration of multiple power supplies on a single IC, and
power supplies together with their loads reduces the total number of IC packages.

Further optimizations can be made at the power system level. As indicated in Chapter 4,
converter topology and battery voltage choices can have a profound impact on the size of the
overall power system. In addition, since there is a fundamental trade-off between the size of a
DC-DC converter and its losses (see Section 4.1.1) the size and efficiency of different converters
in the system may be traded to yield the optimum power system design In low-power
applications, the external components usually dominate the physical size of a DC-DC converter.
Higher operating frequencies reduce the required values of inductance and capacitance, and
ideally, their form factor. “Minimum inductor” designs yield the minimum form factor inductor
for a given application.

Low Noise

DC-DC converters are traditionally among the noisiest components in any electronic system.
Their switching noise generates interference, which is of particular concern in wireless
communications applications. As a result, many cellular handset manufacturers use linear, rather
than switching regulators for all DC-DC down-conversion, despite the negative impact on
battery run-time.Several approaches are used to combat switching noise in DC-DC converters.
The converters are used only in PWM mode, where the switching frequency (and therefore, the
frequencies of fundamental and harmonic switching noise) is known. The switching frequency is
chosen so that the higher-order harmonics.

sensitive IF band, minimizing the effects of spurious transmissions on radio performance. The
magnitude of the noise is reduced with careful physical design. All power traces in the PCB are
kept short and wide, minimizing the area, and thus the stray inductance, in all critical high
current loops. A closed-core output filter inductor design offers a closed magnetic path to

10
contain flux. Finally, a more recent innovation called soft-switching (see Chapter 4) is proposed
to control the high frequency noise emissions.

2.3 PWM Operation

Figure 3.5 shows the steady-state operating waveforms of the buck circuit in PWM operation.
The switching cycle is initiated when PMOS device, Mp, turns on. During the interval, D, of the
switching period, Ts, the inverter output node, vx, is shorted to Vin. A constant positive potential,
Vin-Vo, is applied across the inductor, and iLf linearly increases from its minimum value to
its maximum value. Some of the energy removed from the battery is stored in the magnetic
field of the inductor, and some is delivered to the filter capacitor and the load.Then, the PMOS
device is turned off, and the NMOS rectifier device, Mn, is turned on to pick up the inductor
current, shorting vx to ground. During this interval,(1-D) of the cycle, a constant negative
potential is applied across the inductor, and iLf linearly decreases from its maximum value to its
minimum value. Excess energy in the inductor is delivered to the output filter capacitor and load.
The cycle then repeats by turning off Mn and turning on Mp.In periodic steady-state, regulation is
maintained when the charge drawn from the battery during a switching period is equal to the
charge consumed by the load.

11
 CHAPTER 3
MATLAB SIMULINK

3.1 MATLAB
3.1.1 Introduction
This document is part of the “Introduction to Using Simulink” seminar. This seminar is
designed for people that have never used Simulink. There are two components to the seminar. There
are exercises in a separate document that will take you step by step through the tasks required to build
and use a Simulink model. Once you get started using Simulink, you will find a lot of the functionality
is self-intuitive. Inevitably, there are things that need a bit more explanation. So the other part of the
Seminar is a talk and demonstration. This document contains the notes for the talk. It would be
impossible to put everything about Simulink into such a short document, so this document
concentrates on the parts of the package that are considered the most useful. It also aims to highlight
features that are not obvious to the casual user. The intention is that you use these notes as a reference
when carrying out the exercises and when building your own models. Although these notes have their
limits, I hope that they should be sufficient to get you started using the package and that they cover
most of your modelling needs. This is not a Simulink manual. Sooner or later you will need to know
more detail about something within Simulink. This document is intended to be used in conjunction to
the documentation available within the package. Mathworks, creators of MATLAB & Simulink,
provide extensive online documentation for Simulink that can be accessed using the MATLAB help
system. There is so much online documentation that not many people have the time or inclination to
read all of it. So an aim of the Seminar is to emphasize the things that you ought to know about
Simulink and to give you some idea about where you can find any other information that you require.
3.1.2 Tool for Interactive Simulation

12
 Simulink encourages you to try things out. You can easily build models from scratch, or
take an existing model and add to it. Simulations are interactive, so you can change parameters
on the fly and immediately see what happens. You have instant access to all the analysis tools in
MATLAB®, so you can take the results and analyze and visualize them. A goal of Simulink is to
give you a sense of the fun of modeling and simulation, through an environment that encourages
you to pose a question, model it, and see what happens. Simulink is also practical. With
thousands of engineers around the world using it to model and solve real problems, knowledge of
this tool will serve you well throughout your professional career.
3.1.3 Tool for Model-Based Design With Simulink,
You can move beyond idealized linear models to explore more realistic nonlinear models,
factoring in friction, air resistance, gear slippage, hard stops, and the other things that describe
real-world phenomena. Simulink turns your computer into a lab for modeling and analyzing
systems that simply wouldn’t be possible or practical otherwise, whether the behavior of an
automotive clutch system, the flutter of an airplane wing, the dynamics of a predator-prey model,
or the effect of the monetary supply on the economy. For modeling, Simulink provides a
graphical user interface (GUI) for building models as block diagrams, using click-and-drag
mouse operations. With this interface, you can draw the models just as you would with pencil
and paper (or as most textbooks depict them). This is a far cry from previous simulation
packages that require you to formulate differential equations and difference equations in a
language or program. Simulink includes a comprehensive block library of sinks, sources, linear
and nonlinear components, and connectors. You can also customize and create your own blocks.
For information on creating your own blocks, see the separate Writing S-Functions guide.
3.1.4 Running a Demo Model

An interesting demo program provided with Simulink models the thermodynamics of a house.
To run this demo, follow these steps:

1 Start MATLAB. See your MATLAB documentation if you’re not sure how to do this.

2 Run the demo model by typing thermo in the MATLAB Command Window.This command
starts up Simulink and creates a model window that contains this model.
3 Double-click the Scope block labeled Thermo Plots.

13
4 The Scope block displays two plots labeled Indoor vs. Outdoor Temp and Heat Cost ($),
respectively.To start the simulation, pull down the Simulation menu and choose the
Start command (or, on Microsoft Windows, click the Start button on the Simulink toolbar).
As the simulation runs, the indoor and outdoor temperatures appear in the Indoor vs. Outdoor
Temp plot and the cumulative heating cost appears in the Heat Cost ($) plot.
5 To stop the simulation, choose the Stop command from the Simulation menu (or click the
Pause button on the toolbar). If you want to explore other parts of the model, look over the
suggestions in “Some Things to Try” on page 1-6.
6 When you’re finished running the simulation, close the model by choosing Close from
the File menu.

3.1.5 Building a Model

This example shows you how to build a model using many of the model-building commands and
actions you will use to build your own models. The instructions for building this model in this
section are brief. All the tasks are described in more detail in the next chapter.The model
integrates a sine wave and displays the result along with the sine wave. The block diagram of the
model looks like this.

14
To create the model, first enter simulink in the MATLAB Command Window. On Microsoft
Windows, the Simulink Library Browser appears.

To create a new model on UNIX, select Model from the New submenu of the Simulink library
window’s File menu. To create a new model on Windows, click the New Model button on the
Library Browser’s toolbar.

15
To create this model, you need to copy blocks into the model from the following
Simulink block libraries:
• Sources library (the Sine Wave block)
• Sinks library (the Scope block)
• Continuous library (the Integrator block)
• Signal Routing library (the Mux block)
You can copy a Sine Wave block from the Sources library, using the Library Browser (Windows
only) or the Sources library window (UNIX and Windows).To copy the Sine Wave block from
the Library Browser, first expand the Library Browser tree to display the blocks in the Sources
library. Do this by clicking the Sources node to display the Sources library blocks. Finally, click

16
the Sine Wave node to select the Sine Wave block.Here is how the Library Browser should look
after you have done this.

Now drag a copy of the Sine Wave block from the browser and drop it in the model window.To
copy the Sine Wave block from the Sources library window, open the Sources window by
double-clicking the Sources icon in the Simulink library window.(On Windows, you can open
the Simulink library window by right-clicking the Simulink node in the Library Browser and
then clicking the resulting Open Library button.)

3.1.6 Modeling Dynamic Systems

A Simulink block diagram model is a graphical representation of a mathematical model of a
dynamic system. A mathematical model of a dynamic system is described by a set of equations.
The mathematical equations described by a block diagram model are known as algebraic,
differential, and/or difference equations.
A classic block diagram model of a dynamic system graphically consists of blocks and lines
(signals). The history of these block diagram model is derived from engineering areas such as
Feedback Control Theory and Signal Processing. A block within a block diagram defines a
dynamic system in itself. The relationships between each elementary dynamic system in a block
diagram are illustrated by the use of signals connecting the blocks. Collectively the blocks and

17
lines in a block diagram describe an overall dynamic system. Simulink extends these classic
block diagram models by introducing the notion of two classes of blocks, nonvirtual block and
virtual blocks. Nonvirtual blocks represent elementary systems. A virtual block is provided for
graphical organizational convenience and plays no role in the definition of the system of
equations described by the block diagram model. Examples of virtual blocks are the Bus Creator
and Bus Selector which are used to reduce block diagram clutter by managing groups of signals
as a “bundle.” You can use virtual blocks to improve the readability of your models. In general,
block and lines can be used to describe many “models of computations.” One example would be
a flow chart. A flow chart consists of blocks and lines, but one cannot describe general dynamic
systems using flow chart semantics. The term “time-based block diagram” is used to distinguish
block diagrams that describe dynamic systems from that of other forms of block diagrams. In
Simulink, we use the term block diagram (or model) to refer to a time-based block diagram
unless the context requires explicit distinction. To summarize the meaning of time-based block
diagrams: • Simulink block diagrams define time-based relationships between signals and state
variables. The solution of a block diagram is obtained by evaluating these relationships over
time, where time starts at a user.

3.2 Time
Time is an inherit component of block diagrams in that the results of a block diagram simulation
change with time. Put another way, a block diagram represents the instantaneous behavior of a
dynamic system. Determining a system’s behavior over time thus entails repeatedly executing
the model at intervals, called time steps, from the start of the time span to the end of the time
span. Simulink refers to the repeated execution of a model at successive time steps as simulating
the system that the model represents. It is possible to simulate a system manually, i.e., to execute
its model manually. However, this is unnecessary as the Simulink engine performs this task
automatically on command from the user.
3.3 States
Typically the current values of some system, and hence model, outputs are functions of
the previous values of temporal variables. Such variables are Modeling Dynamic Systems 2-5
called states. Computing a model’s outputs from a block diagram hence entails saving the value

18
of states at the current time step for use in computing the outputs at a subsequent time step.
Simulink performs this task during simulation for models that define states. Two types of states
can occur in a Simulink model: discrete and continuous states. A continuous state changes
continuously. Examples of continuous states are the position and speed of a car. A discrete state
is an approximation of a continuous state where the state is updated (recomputed) using finite
(periodic or aperiodic) intervals. An example of a discrete state would be the position of a car
shown on a digital odometer where it is updated every second as opposed to continuously. In the
limit, as the discrete state time interval approaches zero, a discrete state becomes equivalent to a
continuous state. Blocks implicitly define a model’s states. In particular, a block that needs some
or all of its previous outputs to compute its current outputs implicitly defines a set of states that
need to be saved between time steps. Such a block is said to have states. The following is a
graphical representation of a block that has states. Blocks that define continuous states include
the following standard Simulink blocks: • Integrator • State-Space • Transfer Fcn • Zero-Pole
The total number of a model’s states is the sum of all the states defined by all its blocks.
Determining the number of states in a diagram requires parsing the diagram to determine the
types of blocks that it contains and then aggregating the number of states defined by each
instance of a block type that defines states. Simulink performs this task during the Compilation
phase of a simulation.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle.

3.4 Continuous States

Computing a continuous state entails knowing its rate of change, or derivative. Since the
rate of change of a continuous state typically itself changes continuously (i.e., is itself a state),
computing the value of a continuous state at the current time step entails integration of its
derivative from the start of a simulation.Thus modeling a continuous state entails representing
the operation of integration and the process of computing the state’s derivative at each point in
time. Simulink block diagrams use Integrator blocks to indicate integration and a chain of
operator blocks connected to the integrator block to represent the method for computing the
state’s derivative. The chain of block’s connected to the Integrator’s is the graphical counterpart

19
to an ordinary differential equation (ODE). In general, excluding simple dynamic systems,
analytical methods do not exist for integrating the states of real-world dynamic systems
represented by ordinary differential equations. Integrating the states requires the use of numerical
methods called ODE solvers. These various methods trade computational accuracy for
computational workload. Simulink comes with computerized implementations of the most
common ODE integration methods and allows a user to determine which it uses to integrate
states represented by Integrator blocks when simulating a system. Computing the value of a
continuous state at the current time step entails integrating its values from the start of the
simulation. The accuracy of numerical integration in turn depends on the size of the intervals
between time steps. In general, the smaller the time step, the more accurate the simulation. Some
ODE solvers, called variable time step solvers, can automatically vary the size of the time step,
based on the rate of change of the state, to achieve a specified level of accuracy over the course
of a simulation. Simulink allows the user to specify the size of the time step in the case of fixed-
step solvers or allow the solver to determine the step size in the case of variable-step solvers. To
minimize the computation workload, the variable-step solver chooses the largest step size
consistent with achieving an overall level of precision specified by the user for the most rapidly
changing model state. This ensures that all model states are computed to the accuracy specified
by the user.

3.5 Discrete States

Computing a discrete state requires knowing the relationship between the current time
and its value at the time at which it previously changed value. Simulink refers to this relationship
as the state’s update function. A discrete Modeling Dynamic Systems 2-7 state depends not only
on its value at the previous time step but also on the values of a model’s inputs. Modeling a
discrete state thus entails modeling the state’s dependency on the systems’ inputs at the previous
time step. Simulink block diagrams use specific types of blocks, called discrete blocks, to specify
update functions and chains of blocks connected to the inputs of the block’s to model the state’s
dependency on system inputs. As with continuous states, discrete states set a constraint on the
simulation time step size. Specifically a step size must be chosen that ensure that all the sample
times of the model’s states are hit. Simulink assigns this task to a component of the Simulink
system called a discrete solver. Simulink provides two discrete solvers: a fixed-step discrete

20
solver and a variable-step discrete solver. The fixed-step discrete solver determines a fixed step
size that hits all the sample times of all the model’s discrete states, regardless of whether the
states actually change value at the sample time hits. By contrast, the variable-step discrete solver
varies the step size to ensure that sample time hits occur only at times when the states change
value. Modeling Hybrid Systems A hybrid system is a a system that has both discrete and
continuous states Strictly speaking a hybrid model is identified as having continuous and discrete
sample times from which it follows that the model will have continuous and discrete states.
Solving a model of such a system entails choosing a step size that satisfies both the precision
constraint on the continuous state integration and the sample time hit constraint on the discrete
states. Simulink meets this requirement by passing the next sample time hit as determined by the
discrete solver as an additional constraint on the continuous solver. The continuous solver must
choose a step size that advances the simulation up to but not beyond the time of the next sample
time hit. The continuous solver can take a time step short of the next sample time hit to meet its
accuracy constraint but it cannot take a step beyond the next sample time hit even if its accuracy
constraint allows it to. Block Parameters Key properties of many standard blocks are
parameterized. For example, the Constant value of the Simulink Constant block is a parameter.
Each parameterized block has a block dialog that lets you set the values of the parameters. You
can use MATLAB expressions to specify parameter values. Simulink evaluates the expressions
before running a simulation. You can 2 How Simulink Works 2-8 change the values of
parameters during a simulation. This allows you to determine interactively the most suitable
value for a parameter. A parameterized block effectively represents a family of similar blocks.
For example, when creating a model, you can set the Constant value parameter of each instance
of the Constant block separately so that each instance behaves differently. Because it allows each
standard block to represent a family of blocks, block parameterization greatly increases the
modeling power of the standard Simulink libraries. Each time you change parameters, you
change the meaning of the model. Simulink lets you modify the parameter values during
execution of your model. For example, you can pause simulation, change parameter values, and
continue simulation. It should be pointed out that parameter changes do not immediately occur,
but are queued up and then applied at the start of the next time step during model execution.
Returning to our example of the constant block, the function it defines is for all time. If we were
to allow the constant value to be changed immediately, then the solution at the point in time at

21
which the change occurred would be invalid, thus we must queue the change for processing on
the next time step. Tunable Parameters Many block parameters are tunable. A tunable parameter
is a parameter whose value can change while Simulink is executing a model. For example, the
gain parameter of the Gain block is tunable. You can alter the block’s gain while a simulation is
running. If a parameter is not tunable and the simulation is running, Simulink disables the dialog
box control that sets the parameter. Simulink allows you to specify that all parameters in your
model are nontunable except for those that you specify. This can speed up execution of large
models and enable generation of faster code from your model. See “Model Parameter
Configuration Dialog Box” on page 10-47 for more information. Block Sample Times Every
Simulink block is considered to have a sample time, even continuous blocks (e.g., blocks that
define continuous states, such as the Integrator block) and blocks that do not define states, such
as the Gain block. Discrete blocks allows you to specify their sample times via a Sample Time
parameter. Continuous blocks are considered to have an infinitesimal sample time called a
continuous sample time. A block that is neither discrete or continuous is said signal t( ) = Cons
tValue tan Modeling Dynamic Systems 2-9 to have an implicit sample time that it inherits from
its inputs. The implicit sample time is continuous if any of the block’s inputs are continuous.
Otherwise, the implicit sample time is discrete. An implicit discrete sample time is equal to the
shortest input sample time if all the input sample times are integer multiples of the shortest time.
Otherwise, the implicit sample time is equal to the fundamental sample time of the inputs, where
the fundamental sample time of a set of sample times is defined as the greatest integer divisor of
the set of sample times. Simulink can optionally color code a block diagram to indicate the
sample times of the blocks it contains, e.g., black (continuous), magenta (constant), yellow
(hybrid), red (fastest discrete), and so on. See “Mixed Continuous and Discrete Systems” on
page 2-40 for more information. Custom Blocks Simulink allows you to create libraries of
custom blocks that you can then use in your models. You can create a custom block either
graphically or programmatically. To create a custom block graphically, you draw a block
diagram representing the block’s behavior, wrap this diagram in an instance of the Simulink
Subsystem block, and provide the block with a parameter dialog, using the Simulink block mask
facility. To create a block programmatically, you create an M-file or a MEX-file that contains the
block’s system functions (see Writing S-Functions in the online Help for Simulink). The
resulting file is called an S-function. You then associate the S-function with instances of the

22
Simulink S-Function block in your model. You can add a parameter dialog to your S-Function
block by wrapping it in a Subsystem block and adding the parameter dialog to the Subsystem
block. Systems and Subsystems A Simulink block diagram can consist of layers. Each layer is
defined by a subsystem. A subsystem is part of the overall block diagram and ideally has no
impact on the meaning of the block diagram. Subsystems are provided primarily to help in the
organization aspects a block diagram. Subsystem do not define a separate block diagram.
Simulink differentiates between two different types of subsystems virtual and nonvirtual
subsystems. The main difference is that nonvirtual subsystems provide the ability to control
when the contents of the subsystem are evaluated. 2 How Simulink Works 2-10 Flattening the
Model Hierarchy While preparing a model for execution, Simulink generates internal “systems”
that are collections of block methods (equations) that are evaluated together. The semantics of
time-based block diagrams doesn’t require creation of these systems. Simulink creates these
internal systems as a means to manage the execution of the model. Roughly speaking, there will
be one system for the top-level block diagram window which is referred to as the root system,
and several lower-level system derived from the nonvirtual subsystem and other elements within
the block diagram. You will see these systems within the Simulink Debugger. The act of creating
these “internal” systems is often referred to as flattening the model hierarchy. Conditionally
Executed Subsystems You can create conditionally executed subsystems that are executed only
when a transition occurs on a triggering, function-call, action, or enabling input (see “Creating
Conditionally Executed Subsystems” on page 4-26). Conditionally executed subsystems are
atomic. Unconditionally executed subsystems are virtual by default. You can, however,
designate an unconditionally executed subsystem as atomic. This is useful if you need to ensure
that the equations defined by a subsystem are evaluated “together” as a unit. Signals Simulink
uses the term signal to refer to a time varying quantity that has values at all points in time.
Simulink allows you to specify a wide range of signal attributes, including signal name, data type
(e.g., 8-bit, 16-bit, or 32-bit integer), numeric type (real or complex), and dimensionality (one-
dimensional or two-dimensional array). Many blocks can accept or output signals of any data or
numeric type and dimensionality. Others impose restrictions on the attributes of the signals they
can handle. On the block diagram, you will find that the signals are represented with lines that
have an arrow head. The source of the signal corresponds to the block that writes to the signal
during evaluation of its block methods (equations). The destinations of the signal are blocks that

23
read the signal during the evaluation of its block methods (equations). A good analogy of the
meaning of a signal is to consider a classroom. The teacher is the one responsible for writing on
the white board and the students read what is written on the white board when Modeling
Dynamic Systems 2-11 they choose to. This is also true of Simulink signals, a reader of the
signal (a block method) can choose to read the signal as frequently or infrequently as so desired.
Block Methods Blocks represent multiple equations. These equations are represented as block
methods within Simulink. These block methods are evaluated (executed) during the execution of
a block diagram. The evaluation of these block methods is performed within a simulation loop,
where each cycle through the simulation loop represent evaluation of the block diagram at a
given point in time. Method Types Simulink assigns names to the types of functions performed
by block methods. Common method types include: • Outputs Computes the outputs of a block
given its inputs at the current time step and its states at the previous time step. • Update
Computes the value of the block’s discrete states at the current time step, given its inputs at the
current time step and its discrete states at the previous time step. • Derivatives Computes the
derivatives of the block’s continuous states at the current time step, given the block’s inputs and
the values of the states at the previous time step.

24
 CHAPTER 4
BUCK AND BUCK-BOOST DC-DC CONVERTERS
4.1 Introduction
We use the experimental assembly from Fig. 3, equipped with an IRF9130 transistor (enhanced p
– channel MOS transistor), a diode, an inductor, resistors and capacitors of different values. The
positive voltage supply is applied from a dc voltage supply, and the command voltage is obtained
from the signal generator. We use a dual channel oscilloscope to visualize the signals, and a
multimeter to measure the dc values.
4.2 Buck converter (Step – down)
The output voltage of the Buck converter is lower than the input voltage.
 For the circuit in Fig.1, supplied with VI=10V, controlled with a rectangular signal vcmd
from the function generator, with an amplitude of 10V, frequency 33KHz and a duty cycle
δ=50%, draw the waveforms of the following signals:
o vI(t), vcmd(t), vD3(t), vO(t);
o iI(t), iD3(t), iL1(t), iC1(t).
 Write the relationship between VO and VI and find the value of VO for VI=10V and duty
cycle δ=50%. The duty cycle is computed as δ=TL/T, where TL represents the time during which
the control signal is 0V (control transistor M1 is in conduction state) and T is the period of the
signal.

4.3 Buck-Boost converter (Step – down/step – up)

25
 The output voltage of a Buck – Boost converter has an inverted polarity compared with the
input voltage.
 For the circuit in Fig. 2, supplied with VI=10V, controlled with a rectangular signal vcmd
from the function generator, with an amplitude of 10V, frequency 20KHz and a duty cycle
δ=50%, draw the waveforms of the following signals:
o vI(t), vcmd(t), vL2(t), vO(t);
o iI(t), iD3(t), iL2(t), iC2(t).
 Write the relationship between VO and VI and find the value of VO for VI=10V and duty
cycle δ=50%.
Buck converters are used to buck or reduce output from solar panel. Panel output voltage is fed
into gate of MOSFET. On switching MOSFET, current flows. As inductor starts building up
oscillations by developing magnetic field across it due to which voltage is “buck” up or reduced.
When MOSFET is

turned off, EMF is suddenly reversed in the inductor that opposes further drop in current. It
supplies current to the load itself via Diode.

26
4.4 Description

The buck boost converter is a DC/DC converter with the output voltage magnitude that is either
greater than or less than the input voltage magnitude. It is comparable to a flyback converter
where an inductor is used in place of a transformer. The theoretical transfer function of the buck
boost converter is:where is the duty cycle.The inverting buck-boost topology produces an output
voltage that is of the opposite polarity as the input voltage. The output voltage is determined by
the duty cycle of the MOSFET transistor.The non-inverting topology, also named the 4-switch
topology, produces an output voltage that is of the same polarity as the input voltage. In the buck
mode, the output voltage is determined by the operation of the MOSFET and diode D1. In the
boost mode, the output voltage is determined by the operation of the IGBT and diode D2.

27
 CHAPTER 5
Dual-Mode Control Scheme

I. INTRODUCTION
The market for portable consumer electronic products (e.g., laptop computers and
mobile communication devices) has undergone rapid growth in the last few years.
In turn, consumers have become increasingly concerned about the usage duration
of their electronics devices. Currently, such devices are powered by batteries, and
the voltage supply to such products tends to decrease gradually. Therefore, to
extend the battery life, synchronous buck converters (SBC) have been widely used
in personal and portable devices (Fig. 5(a)). Conventional SBCs are controlled
28
using complementary pulse-width modulation (PWM), as shown in Fig. 1(b).
Under heavy-load conditions, the low conduction loss inherent in a switch, MB, is
used to operate an SBC in a continuous conduction mode (CCM), thus increasing
the conversion efficiency. However, when the mean load current is lower than he
inductance current associated with a boundary conduction mode, the reverse
inductance current creates excess loss [1], as shown by the red dotted lines in Fig.
1(b). Specifically, the operation of SBCs under light-load conditions is inadequate
due to the low conversion efficiency.In order to address the drawbacks of SBC,
hybrid mode control strategies based on different loading conditions from several
different studies have been proposed [2–14]. The most popular technique of the
dual mode control is to combine with CCM and discontinuous conduction mode
(DCM). Generally, dual-mode operations can be divided into fixed-frequency
mode and variable-frequency mode. In variable-frequency control, a PFM
technique based on the hysteresis of the output voltage determines the timing for
the turning on and off of a metal-oxide-semiconductor field-effect transistor
(MOSFET) [2–5]. In other words, the output power decreases, thereby decreasing
the switching frequency.Therefore, the light-load efficiency of the SBC increases.
The drawback of this control strategy is a much wider range of switching
frequencies, making EMI filter design difficult. In addition, the output ripple
voltage for this control strategy is higher than that for the PWM control
strategy.Another variable-frequency technique involves detecting the valley of the
inductor current. If the inductor current reaches the valley, the main switch will be
triggered on. Thus, the SBC can be operated at the boundary between CCM and
DCM. The main switch operated in this region has the characteristics ofzero-
current-switching (ZCS) [6]. The quasi-resonant switching technique is similar to
the aforementioned controlstrategy [7–9]. This scheme involves resonance
generated through the parasitic capacitance and inductance of switches.To improve
29
the efficiency, it turns on the MOSFET when thev resonance reaches a valley. The
above-mentioned controlstrategies still have problems related to a wider variation
range ds of switching frequencies when the output power drops.Due to the
aforementioned drawbacks of variable-frequency control, some authors have opted
for fixed-frequency PWMtechniques [10–14]. These control methods need to
detect the zero point of the inductor current. When the inductor currentreaches
zero, the synchronous switch is turned off to prevent aninverse inductor current.
Another control strategy is to emulate the inductor current with an auxiliary circuit,
and the result isthe same as for the previous method [13]. In order to improvethe
efficiency of SBCs under light-load conditions, Ref. [14] adopted the ZVS
technique. The key point of the controlstrategy is that the synchronous switch is
turned on twice in acomplete switching cycle; therefore, the main switch has a
ZVS characteristic without considering the v of the synchronousswitch for the on-
state. That is, the synchronous switchgenerates extra switching losses at the instant
that the switch is dsturned on. In order to overcome this drawback, this paper
proposes a novel control strategy.Previous studies have proposed the use of soft-
switching
5.2. PROPOSED DUAL-MODE CONVERTER STRUCTURE AND
OPERATING PRINCIPLES
Figure 2(a) presents the block diagram of the proposed ontrol scheme, including a fixed-
frequency PWM controller nd an LZC. To achieve ZVS while avoiding reverse nductance
currents, an external current transformer and aero-hysteresis comparator must be used when
inductance urrent levels are less than zero in order to generate v gnals to turn off the synchronous
switch (M). In other words,n the proposed control scheme, the SBC operating mode can be
Bvided into a DCM and a CCM. The error signal v is generated by comparing the feedback
voltage v of the errorompensation amplifiers with the reference voltage VFB. Thisgnal can be
used to determine the duty cycle of the main witch. In addition, v is mainly supplied by an
auxiliary inding for detecting the drain voltage of M ZCD Furthermore, the negative-edge of v

30
Z2_OB triggers LZC to generate v signals,hich turn on M and the rest of the PWM controller
tomplement the valley switching of MB and ZVS of the main witch MA Here, Vref1 is close to
VOB pulse/2. Figure 2(b) shows the theoretical waveform of the proposed ontroller, which
involves DCM and CCM operations. TheCM operation is described as follows. When the
inductance urrent drops to zero, the v signal changes from a high level o a low level in order to
turn off MZ1_O and prevent the occurrence of a reverse induction current. Subsequently, the
LZC begins to B ref EAO Z1_Oreaches the MPP. This algorithm is not suitable when the
variation in the solar irradiation is high. The voltage never actually reaches an exact value but
perturbs around the maximum power point (MPP).

31
5.3 CIRCUIT IMPLEMENTATION
QR control strategy usually has a problem about much higher switching frequency. This
drawback is typically resolved by limit ing the highest switching frequency, which can be done by
adding a minimum off-time (during which energy is transmitted to an output load) to a switching
cycle [26, 27]. Although this technique can prevent an increase in the frequency, it requires the
addition of blanking time circuits and time delay circuits, rendering the overall control circuit design
more complex. Instead, this study proposes an LZC that only requires one additional pulse generator
circuit to limit the maximum frequency of the QR mode (Fig. 3). Additionally, M has characteristics
of ZVS.
When the inductance current I drops to zero, the v signal turns off MBL through the AND gate. In
the QR mode, C induces resonance with L, as shown in Fig. 3(b). When the vds_MB voltage
resonance reaches a valley, the v signal immediately changes from a positive potential to a negative
potential, and processing this signal using a differentiator and a resistive divider (Rth1and R) yields

32
an adjustable pulse signal vp_thth2 To limit the maximum frequency, the PWM IC oscillator signals
vosc and v must be composed for comparison with VTHp_th to determine the valley switching
timing (Fig. 3(a)). If the vsoc_p signal (vsoc_p= vp_th+ vsoc_p where vp_th= V) is lower than VTH
, then the v pulseZ1_OZO_2p_h signal is maintained at a low potential without influencing the
operation of the oscillator. This operating mode is repeated until t is achieved. At t0 vds_MB0
reaches the valley in resonance. At this moment,vsoc_p is higher than VTH. Hence, v changes from
a low to a high level. During this transient state, M pulse and Q are turned on simultaneously. This
causes the oscillator to discharge rapidly and the inductor starts to store energy. After tB1 M and Q
are turned off simultaneously. Thus, the PWM controller restarts to B change the designed oscillation
frequency. As mentioned above,the frequency of the PWM controller increases if v
is higher.Conversely, the frequency of the PWM controller will decrease.These results indicate that v
p_th p_th can be adjusted according to the maximum switching frequency. Furthermore, the energy
stored in the inductor in the previous state causes the parasitical capacitor to discharge, forcing M
to achieve ZVS in the subsequent switching cycle. The following circuit design is divided into two
parts—the ZVS of MA and valley switching of Mass.

33
5.4 POWER LOSS ANALYSIS
Because the aim of this study is to improve the light-load power losses of SBCs that employ
conventional control strategies, the device losses are analyzed under light-load conditions.
Devices such as high-side MOSFETs, low-side MOSFETs, and inductors cause most of the
power losses in conventional SBCs. The total power losses in conventional MOSFETs can thus
be categorized as conduction losses and switching losses. Therefore, P𝐶𝑜𝑛._MA𝑇𝑟𝑎𝑑.and
P𝐶𝑜𝑛._MB 𝑇𝑟𝑎𝑑. can be expressed as follows.

34
5.6 DESIGN CONSIDERATION

The proposed scheme can therefore strongly constrain the operating frequency of the QR mode
and prevent an excessively high switching frequency that is observed in conventional control
methods during operation under light-load conditions.

35
36
37
 CHAPTER 6

6.1 CONCLUSION

In this study, a novel dual-mode control scheme suitable for synchronous buck converters
(SBC) was developed, and the operating principle of this strategy was explained. It was then
analyzed to demonstrate its efficiency. The novel control scheme mainly integrates a continuous
conduction mode and adiscontinuous conduction mode (DCM). In particular, when the SBC was
operated in the DCM, the second synchronous switch conduction that occurred before the main
switch conduction contributed to the zero-voltage switching (ZVS) of the main switch. In
addition, composing the pulse and sawtooth waveform signals prompted the synchronous switch
to achieve valley switching under limited frequency conditions. This scheme possesses the
following advantages. First, it is integrated with asynchronous rectification technique to reduce
the conduction losses of the converter and improve the
efficiency of the overall circuit. Second, operating an SBC in the DCM can achieve ZVS in the
main switch without requiring additional auxiliary switches or passive devices comprising a
resistor, an inductor, and a capacitor. The simple pulse generators are employed to limit the
highest switching frequency of the quasi-resonant mode. Finally,in Appendix, a comparison
between the proposed control method with variable switching frequency and the control method
with constant switching frequency presented in [14] is provided.

38
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