Professional Documents
Culture Documents
• Docking Station
package.
1.5Mhz 1.5Mhz
VOUT1 PWM PWM VOUT2
0.9V~1.675V/1.5A Converter Converter 1.5V~2.6625V/1A
Buck1 Buck2
1.5Mhz
VOUT3 PWM 1.5Mhz
Converter PWM VOUT4
0.7V~3.3V/1A
Buck3 Converter 0.7V~3.3V/1.5A
Buck4
Reference
(2.56V) 1.5Mhz
PWM VOUT5
Converter 0.7V~1.475V/2.5A
Buck5
I2C
Interface
VLDO
LDO
1.75V~3.0427V/300mA
Therma
l
AD
C
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
28 ALERT1
34 PGND5
31 VCC5
29 GND
35 FB3
32 FB5
30 FB4
33 LX5
36 NC
VCCDR 1 27 DEVSLP
VCC3 2 26 VSELB
LX3 3 25 PGND4
PGND23 4 24 LX4
LX2 5 23 VCC14
GND
VCC2 6 22 LX1
FB2 7 21 PGND1
LDO_INT 8 20 ALERT0
VCC 9 19 FB1
VSELA 17
POK 18
LDO 10
VBUS 11
SDA 12
VREF 13
TS 14
SCL 15
AGND 16
TQFN5x5-36
(Top View)
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in free air (Note 2)
43 o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFN5x5-36 is soldered directly on the PCB.
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
BIAS
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
Electrical Characteristics
Unless otherwise specified, these specifications apply over TA= -40 to 85 oC. Typical values are at TA=25oC.
APW77 05
Sym bol Pa ra mete r Tes t Condit ions Unit
Min Typ Max
LDO
Inp ut Voltage Ran ge 2.7 - 5.5 V
O utput Vo ltag e Ra nge 1.05 - 3.0 43 V
Note 5: Efficiency is measured between VCC14 and BUCK1 VOUT while BUCK4 is off.
Note 6: Efficiency is measured between VCC2 and BUCK2 VOUT.
Note 7: Efficiency is measured between VCC3 and BUCK3 VOUT.
Note 8: Efficiency is measured between VCC14 and BUCK4 VOUT while BUCK1 is off.
Note 9: Efficiency is measured between VCC5 and BUCK5 VOUT.
1.51 1.86
1.50 1.85
1.49 1.84
1.48 1.83
1.47 1.82
1.46 1.81
1.45 1.80
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (oC) Temperature (oC)
998 1.04
996 1.03
VOUT3 Voltage (mV)
994 1.02
VOUT4 Voltage (V)
992 1.01
990 1.00
988 0.99
986 0.98
984 0.97
982 0.96
980 0.95
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
o
Temperature ( C) Temperature (oC)
1.04 1.89
1.03 1.88
VLDO_INT Voltage (V)
1.02 1.87
VOUT5 Voltage (V)
1.01 1.86
1.00 1.85
0.99 1.84
0.98 1.83
0.97 1.82
0.96 1.81
0.95 1.80
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
o
Temperature ( C) Temperature (oC)
2.680 2.68
2.660 2.66
2.640 2.64
2.620 2.62
2.600 2.60
2.580 2.58
2.560 2.56
2.540 2.54
2.520 2.52
2.500 2.50
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (oC) Temperature (oC)
Pin Description
PIN
Function
NO. NAME
1 VCCDR Power supply
2 VCC3 Power supply
3 LX3 Buck3 regulator switching node
4 PGND23 Buck2 and Buck3 ground
5 LX2 Buck2 regulator switching node
6 VCC2 Buck2 power supply
7 FB2 Buck2 regulator feedback
8 LDO_INT 1.8V LDO Output
9 VCC Power supply
10 LDO LDO output
11 VBUS I2C interface power supply
12 SDA I2C bus data line
13 VREF Reference voltage for temperature sensor
14 TS ADC input for temperature sensor
15 SCL I2C bus clock line
16 AGND Analog ground
17 VSELA With VSELB, set A, B, C and D selection
18 POK Power on reset output
19 FB1 Buck1 regulator feedback
20 ALERT0 Alert output 0, open drain
21 PGND1 Buck1 ground
22 LX1 Buck1 regulator switching node
23 VCC14 Buck and Buck4 power supply
24 LX4 Buck4 regulator switching node
25 PGND4 Buck4 ground
26 VSELB With VSELA, set A, B, C and D selection
27 DEVSLP Digital signal input for entering device sleep mode
28 ALERT1 Alert output 1, open drain
29 GND Digital ground
30 FB4 Buck4 regulator feedback
31 VCC5 Buck5 power supply
32 FB5 Buck5 regulator feedback
33 LX5 Buck5 regulator switching node
34 PGND5 Buck5 ground
35 FB3 Buck3 regulator feedback
36 NC Not connected internally
Block Diagram
VCC14
Voltage
VCCDR Monitor
BUCK 1
POK POR PWM LX1
Switching
Controller
Thermal PGND1
Protection
FB1
Oscillator
GND
Bias
BUCK 4
PWM LX4
Switching
Controller
VBUS PGND4
SCL I2C Interface
FB4
SDA
VCC2
MTP
BUCK 2
PWM LX2
DEVSLP Switching
Controller
VSELA PGND23
VSELB
FB2
ALERT0 Power
Control
VCC3
Logic
ALERT1 BUCK 3
PWM LX3
Switching
Controller
VCC5
VREF VREF
(2.56V)
BUCK 5
PWM LX5
VCC LDO_INT Switching
(1.8V) Controller
LDO_INT
PGND5
FB5
LDO LDO
AGND
L1
VBUS 1µH
LX1 VOUT1
VBUS C2
22µF
R1 R2 PGND1
10kΩ 10kΩ
SCL FB1
SDA L4
1µH
POK LX4 VOUT4
System
Control DEVSLP
C3
22µF
PGND4
VSELA
VSELB FB4
VCC2 VIN
VBUS C4
4.7µF
L2
R3 R4
10kΩ 10kΩ
APW7705 1µH
LX2 VOUT2
ALERT0 C5
22µF
ALERT1 PGND23
LDO_INT
C11 FB2
4.7µF
VCC3 VIN
C6
4.7µF
VCC
C12 L3
4.7µF 1µH
LX3 VOUT3
C7
22µF
LDO
C13
4.7µF
FB3
AGND
VCC5 VIN
VREF C8
4.7µF
C14
4.7µF
L5
1µH
LX5 VOUT5
TS
C9
22µFx2
NTC PGND5
FB5
Function Description
Main Control Loop Over-Temperature Protection (OTP)
The APW7705A/B/C/D is a single chip power supplies The over-temperature circuit limits the junction tempera-
designed to for SSD and Docking station applications. ture of the APW7705A/B/C/D. When the junction tempera-
Five high efficiency DC/DC buck converters and one LDO ture exceeds 160 oC, a thermal sensor turns off the all
regulator generate 0.7V~3.3V rails, programmable via I2C power MOSFETs, allowing the devices to cool. The ther-
interface, which can support up to 1A~2.5A of output cur- mal sensor allows the converters to start a soft-start pro-
rent in each buck converter and 300mA of output current cess and regulate the output voltage again after the junc-
in LDO regulator. The power on sequence of all rails is tion temperature cools by 30oC. The OTP designed with
adjustable through the I2C interface to accommodate spe- a 30oC hysteresis lowers the average Junction Tempera-
cific SSD requirements. ture (TJ) during continuous thermal overload conditions,
increasing the life time of the device.
Under-Voltage Lockout
Current-Limit Protection
Soft-Start
The APW7705A/B/C/D monitors the output current, flows
The APW7705A/B/C/D has a built-in soft-start to control
through the high-side and low-side power MOSFETs, and
the output voltage rise during start-up. During soft-start,
limits the current peak at current-limit level to prevent the
an internal ramp voltage, connected to the one of the posi-
IC from damaging during overload, short-circuit and over-
tive inputs of the error amplifier, raises up to replace the
voltage conditions.
reference voltage until the ramp voltage reaches the ref-
erence voltage. Then the voltage on FBx regulated at ref-
erence voltage. Under Voltage Protection
The address 00 bit [5:0] is setting LDO output voltage. Adjustment output voltage range is from 1.75V to 3.5014V. See
the REG00 LDOVL Register of Register Map.
The address 01 bit [6] is setting BUCK1 over current function. When the bit [6] =0 then over current is enable, On the
contrary; the bit [6] was setting 1 then BUCK1 over current is disable. But, In BUCK1 over current was disabling and
loading is adjustment very heavy, this condition can be caused IC damage. See the table 3.
The address 01 bit [5:0] is setting BUCK1 output voltage. Adjustment output voltage range is from 0.9V to 2.475V. See
the REG01 PSR1VL Register of Register Map.
The address 02 bit [6] is setting BUCK3 over current function. When the bit [6] =0 then over current is enable, On the
contrary; the bit [6] was setting 1 then BUCK3 over current is disable. But, In BUCK3 over current was disabling and
loading is adjustment very heavy, this condition can be caused IC damage. See the table 5.
The address 02 bit [5:0] is setting BUCK3 output voltage. Adjustment output voltage range is from 0.7V to 3.3V. See the
REG02 PSR3VL Register of Register Map.
The address 03 bit [6] is setting BUCK2 over current function. When the bit [6] =0 then over current is enable, On the
contrary; the bit [6] was setting 1 then BUCK2 over current is disable. But, In BUCK2 over current was disabling and
loading is adjustment very heavy, this condition can be caused IC damage. See the table 7.
The address 03 bit [4:0] is setting BUCK2 output voltage. Adjustment output voltage range is from 1.5V to 2.6625V. See
the REG03 PSR2VL Register of Register Map.
The address 04 bit [6] is setting BUCK4 over current function. When the bit [6] =0 then over current is enable, On the
contrary; the bit [6] was setting 1 then BUCK4 over current is disable. But, In BUCK4 over current was disabling and
loading is adjustment very heavy, this condition can be caused IC damage. See the table 9.
The address 04 bit [5:0] is setting BUCK4 output voltage. Adjustment output voltage range is from 0.7V to 3.3V. See the
REG04 PSR4VL Register of Register Map.
The address 05 bit [6] is setting BUCK5 over current function. When the bit [6] =0 then over current is enable, On the
contrary; the bit [6] was setting 1 then BUCK5 over current is disable. But, In BUCK5 over current was disabling and
loading is adjustment very heavy, this condition can be caused IC damage. See the table 11.
The address 05 bit [4:0] is setting BUCK5 output voltage. Adjustment output voltage range is from 0.7V to 1.475V. See
the REG05 PSR5VL Register of Register Map.
The address 06 bit [1] is setting LDO Fault Deglitch Time. See the table 13. The function is avoiding fast noise when
LDO output has any irregularity.
The address 06 bit [0] is setting LDO UVM function. See the table 14. When LDO has happened under voltage, The IC
will be shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when LDO has happened under
voltage then IC is not happened shutdown.
The address 07 bits [6:4] are setting BUCK1 order in power on sequence. See the table 16. That’s adjustment BUCK1
order in power on sequence from first to sixth to be powered on.
The bits [1:0] are setting driver slew rate. See the table 17. That’s adjustment driver rising slew rate from 500V/us to
2000V/us.
The bit [1] is setting low side enable or disable. See the table 18. When bit [1] =0 then BUCK1 is synchronous converter, On the
contrary; that bit is setting = 1, the BUCK1 was asynchronous converter.
The address 07 bit [0] is setting BUCK1 UVM function. See the table 19. When BUCK1 has happened under voltage, The IC will be
shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when BUCK1 has happened under voltage then IC is not
happened shutdown.
The bits [1:0] are setting driver slew rate. See the table 21. That’s adjustment driver rising slew rate from 500V/us to
2000V/us.
The bit [1] is setting low side enable or disable. See the table 22. When bit [1] =0 then BUCK3 is synchronous
converter, On the contrary; that bit is setting = 1, the BUCK3 was asynchronous converter.
The address 08 bit [0] is setting BUCK3 UVM function. See the table 23. When BUCK3 has happened under voltage, The IC will be
shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when BUCK3 has happened under voltage then IC is not
happened shutdown.
The bits [1:0] are setting driver slew rate. See the table 25. That’s adjustment driver rising slew rate from 500V/us to
2000V/us.
The bit [1] is setting low side enable or disable. See the table 26. When bit [1] =0 then BUCK2 is synchronous
converter, On the contrary; that bit is setting = 1, the BUCK2 was asynchronous converter.
The address 09 bit [0] is setting BUCK2 UVM function. See the table 27. When BUCK2 has happened under voltage, The IC will be
shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when BUCK2 has happened under voltage then IC is not
happened shutdown.
The bits [1:0] are setting driver slew rate. See the table 29. That’s adjustment driver rising slew rate from 500V/us to
2000V/us.
The bit [1] is setting low side enable or disable. See the table 30. When bit [1] =0 then BUCK2 is synchronous
converter, On the contrary; that bit is setting = 1, the BUCK2 was asynchronous converter.
The address 0A bit [0] is setting BUCK4 UVM function. See the table 31. When BUCK4 has happened under voltage, The IC will be
shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when BUCK4 has happened under voltage then IC is not
happened shutdown.
The bits [1:0] are setting driver slew rate. See the table 33. That¡¦s adjustment driver rising slew rate from 500V/us to
2000V/us.
The bit [1] is setting low side enable or disable. See the table 34. When bit [1] =0 then BUCK5 is synchronous
converter, On the contrary; that bit is setting = 1, the BUCK2 was asynchronous converter.
The address 0B bit [0] is setting BUCK5 UVM function. See the table 35. When BUCK5 has happened under voltage, The IC will be
shutdown in the address bit [0] =0. On the contrary; that bit is setting = 1, when BUCK5 has happened under voltage then IC is not
happened shutdown.
The address 0C bits [6:5] are setting Delay 2 time. It’s setting delay time between each output channels. The delay
time range is from 0ms to 2ms. See the table 38.
In addition, the bits are setting = 01, the POK goes high is must waiting after all channels has already. That’s go high
time is by DLY2 [2:0] setting.
Finally, the bits are setting = 11, the delay time is both form POR rising to first channel and the last one channel to POK
go high.
The address 0E bit [6] is LDO pull down function. When the address bit is setting =0 then LDO have pull down function
in not DSM, in addition to this the others has pull down capability. On the contrary; that bit is setting = 1, it’s always pull
down capability. See the table 41.
The address 0E bit [5] is BUCK5 regulator enable function. When the bit is setting =0, it’s represent the BUCK5 is
enable. On the contrary; that bit is setting = 1, the BUCK5 will be turn off.
The address 0E bits [4] to [0] are respectively representing BUCK4 regulator to LDO output. See the table 42.
But, the 0E bit [5] to [1] function enable was must setting to between VCCDR=2.1V to VCCDR falling. If the VCCDR
voltage exceed VCCDR rising level then this function was disable.
The address 0F bits [1:0] are factory mode function. It cans load to different power sequence and output voltage. See
the table 44.
The address 10 bit [5] is BUCK5 regulator fault function. When the bit is reading to 0 then the BUCK5 is normal work.
On the contrary; that bit is reading = 1 then the BUCK5 is error status.
The address 10 bits [4] to [0] are respectively representing BUCK4 regulator to LDO output. See the table 46.
The address 11 bits [2:1] are temperature conversion rate function. The bits are adjustment from 0.25Hz to 8Hz. It’s
reading TS pin output voltage sampling time and return to REG12 TEMPREG register. See the table 48.
The address 11 bit [0] is temperature conversion enable/disable function. The bit is setting = 0 then TS pin output
voltage information will be return to REG 12 TEMPREG register. On the contrary; the bit is setting = 1, the TS pin output
voltage information is not return to TEMPREG register. At the same time, the TEMPREG data is keeping to previous one
temperature conversion data. See the table 49.
Application Information
Input Capacitor Selection Output Capacitor Selection
Because buck converters have a pulsating input current, The current-mode control scheme of the APW7705 al-
a low ESR input capacitor is required. This results in the lows the use of tiny ceramic capacitors. The higher ca-
best input voltage filtering, minimizing the interference pacitor value provides the good load transients response.
with other circuits caused by high input voltage spikes. Ceramic capacitors with low ESR values have the lowest
Also, the input capacitor must be sufficiently large to sta- output voltage ripple and are recommended. When
bilize the input voltage during heavy load transients. For choosing the input and output ceramic capacitors, choose
good input voltage filtering, usually a 4.7µF input capaci- the X5R or X7R dielectric formulations. These dielectrics
tor is sufficient. It can be increased without any limit for have the best temperature and voltage characteristics of
better input-voltage filtering. Ceramic capacitors show all the ceramics for a given value and size.
better performance because of the low ESR value, and
they are less sensitive against voltage transients and Min footprint
spikes compared to tantalum capacitors. Place the input
capacitor as close as possible to the input and GND pin of
the device for better performance.
5mm
3.65mm
Inductor Selection 0.54mm
3.65mm
5mm
m
core losses. This needs to be considered when select-
ing the appropriate inductor. The inductor value deter-
0.25mm
V
VOUT 1 − OUT
VIN
L≥
FSW ⋅ ∆IL
I2C Programming
The APW7705’s I2C Slave Address is a hard-coded 7-bit address 1111100. The APW7705 supports the following write
and read protocol.
0 0 0 0
Start Slave Address Register Address Data Stop
0 0 0 0
Start Slave Address Register Address Data Stop
Register Map
Register Definition
REG00 LDOVL Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e LDOVLEN Reserved LDOVL[5:0]
Read/Write R/W R/W R/W R/W R/W R/W R/ W R/W
Pow er On Default 0 Default v alues are power-on-strapped with VSELA, VSELB
Bit Nam e Bit Definition
LDO Output Voltage Level Selection Enable:
LDOVLEN 0: Voltage level selection register LDOVL [5:0] is disabled; voltage lev el is s elected via VSELA, VSELB pins.
(Default:APW7705A/B/C/D)
1: Voltage level selection register LDOVL [5:0] is enabled; output voltage changed acc ording to the LDOVL [5:0] setting.
LDO Output Voltage Level Selection:
Register Definition
REG01 PSR1VL Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name PSR1VLEN PSR1OCDIS PSR1VL[5:0]
Power On De fault 0 0 Default values are power-on-s trapped with VSELA, VSELB
Bit Name Bit Definition
Buck 1 Regulator Output Voltage Level Selec tion Enable:
PSR1VLEN 0: Voltage level s election register PSR1VL [5:0] is disabled; voltage level is selected via VSELA, VSELB pins.
(Default :APW7705A/B/ C/D)
1: Voltage level s election register PSR1VL [5:0] is enabled; output voltage changed according to t he PSR1VL [4:0]
setting.
Buck 1 Regulator Over-current Disable:
PSR1OCDIS
0: Ov er-current protec tion for Buck 1 Regulator is enabled. (Default:APW7705A/B/C/D)
1: Ov er-current protec tion for Buck 1 Regulator is dis abled.
Buck 1 Regulator Output Voltage Level Selec tion:
Register Definition
REG02 PSR3VL Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name PSR3VLEN PSR3OCDIS PSR3VL[5:0]
Power On Defa ult 0 0 Default values are power-on-strapped with VSELA, VSELB
Bit Name Bit Definition
Buck 3 Regulator Output Voltage Level Selection Enable:
PSR3VLEN 0: Voltage lev el selec tion register PSR3VL [5:0] is disabled; voltage level is s elected v ia VSELA, VSELB pins .
(Default:APW 7705A/B/C/D)
1: Voltage lev el selec tion register PSR3VL [5:0] is enabled; output volt age changed acc ording to the PSR3VL [5:0]
sett ing.
Buck 3 Regulator Ov er-current Disable:
PSR3OCD IS
0: Over-current protection for Buck 3 Regulator is enabled. (Default: APW7705A/B/C/D)
1: Over-current protection for Buck 3 Regulator is disabled.
Buck 3 Output Voltage Level Selection:
Register Definition
REG03 PSR2VL Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name PSR2VLEN PSR2OCDIS Reserved PSR2VL[4:0]
Power On Defa ult 0 0 Default v alues are power-on-strapped with VSELA, VSELB
Bit Name Bi t D efinition
Buck 2 Regulator Output Voltage Level Selection Enable:
PSR2VLEN 0: Volt age lev el selec tion register PSR2VL [4:0] is disabled; voltage level is s elected v ia VSELA, VSELB pins . (Default:
APW 7705A/B/C/D )
1: Volt age lev el selec tion register PSR2VL [4:0] is enabled; output voltage changed acc ording to the PSR2VL [4:0]
setting.
Buck 2 Regulator Ov er-current Disable:
PSR2OCD IS
0: Over-current protect ion for Buck 2 Regulator is enabled. (Default : APW7705A/B/C/D)
1: Over-current protect ion for Buck 2 Regulator is disabled.
Buck 2 Regulator Output Voltage Level Selection:
Register Definition
REG04 PSR4VL Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name PSR4VLEN PSR4OCDIS PSR4VL[5:0]
Power On Defa ult 0 0 Default values are power-on-s trapped with VSELA, VSELB
Bit Name Bit D efinition
Buck 4 Regulator Output Voltage Level Selection Enable:
PSR4VLEN 0: Voltage level s elec tion register PSR4VL [5:0] is disabled; voltage lev el is selected via VSELA, VSELB pins. (Default:
APW7705A/B/C/D)
1: Voltage level s elec tion register PSR4VL [5:0] is enabled; output volt age changed ac cording to the PSR4VL [5:0]
set ting.
Buck 4 Regulator Over-current Disable:
PSR4OCD IS
0: Over-c urrent prot ection for Buck 4 Regulator is enabled. (Default: APW7705A/B/C/D )
1: Over-c urrent prot ection for Buck 4 Regulator is disabled.
Buck 4 Output Voltage Level Selection:
Register Definition
REG05 PSR5VL Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name PSR5VLEN PSR5OCDIS Reserved PSR5VL[4:0]
Power On Defa ult 0 0 Default v alues are power-on-strapped with VSELA, VSELB
Bit Name Bit D efinition
Buck 5 Regulator Output Voltage Level Selection Enable:
PSR5VLEN 0: Voltage lev el selec tion register PSR5VL [4:0] is disabled; voltage level is s elected v ia VSELA, VSELB pins . (Default:
APW 7705A/B/C/D )
1: Voltage lev el selec tion register PSR5VL [4:0] is enabled; output volt age changed acc ording to the PSR5VL [4:0]
sett ing.
Buck 5 Regulator Ov er-current Disable:
PSR5OCD IS
0: Over-current protection for Buck 5 Regulator is enabled. (Default: APW7705A/B/C/D)
1: Over-current protection for Buck 5 Regulator is disabled.
Buck 5 Regulator Output Voltage Level Selection:
Register Definition
REG06 LDOCFG Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved LDOORDER[2:0] Reserved DEGL UVM
Under-voltage Mask:
UVM
0: LDO Under-voltage generates fault. (Default: APW7705A/B/C/D)
1: LDO Under-voltage does not generate fault.
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved PSR1ORDER[2: 0] RSLEW[1:0] LSDIS UVM
00: 500V/µs
RSLEW[1:0]
01: 1000V/µs
10: 1500V/µs
11: 2000V/µs (Default: APW7705A/B/C/D)
Buck 1 Regulator Low Side Disable:
LSDIS
0: Buck 1 regulator low side enabled. (Default:APW7705A/B/C/D)
1: Buck 1 regulator low side disabled.
Register Definition
REG08 PSR3CFG Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved PSR3ORDER[ 2:0] RSLEW[1:0] LSDIS UVM
Register Definition
REG09 PSR2CFG Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved PSR2ORDER[ 2:0] RSLEW[1:0] LSDIS UVM
00: 500V/µs
RSLEW[1:0]
01: 1000V/µs
10: 1500V/µs
11: 2000V/µs (Default:APW7705A/B/C/D)
Buck 2 Regulator Low Side Disable:
LSDIS
0: Buck 2 regulator low side enabled. (Default:APW7705A/B/C/D)
1: Buck 2 regulator low side disabled.
Register Definition
REG0A PSR4CFG Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved PSR4ORDER[2: 0] RSLEW[1:0] LSDIS UVM
Register Definition
REG0B PSR5CFG Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e Reserv ed PSR4ORDER[ 2:0] RSLEW [1:0] LSDIS UVM
Pow er On Default 0 0 0 0 0
Bit Nam e Bit Definition
Order In Power On Sequence:
00: 500V/µs
RSLEW [1:0]
01: 1000V/µs (Default:APW 7705A/B/C/D)
10: 1500V/µs
11: 2000V/µs
Buck 5 Regulator Low Side Disable:
LSDIS
0: Buck 5 regulator low s ide enabled. (Default:APW7705A/B/C/D)
1: Buck 5 regulator low s ide disabled.
Register Definition
REG0C SEQCFG Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e DLY1[3] DLY2[1:0] DLY1CFG[1:0] DLY1[2:0]
Pow er On Default 1 0 1 0 1 0 0 0
Bit Nam e Bit Definition
00: 0ms
DLY2[1:0]
01: 0.5ms (Default:APW7705A/B/C/D)
10: 1ms
11: 2ms
Delay 1 Configuration:
00: No delay
DLY1CFG[1:0]
01: Delay 1 is the d elay before POK rising edge. (Default:APW 7705A/B/C/D)
10: Delay 1 is the delay before starting sequence.
11: Delay 1 is both the delay before starting sequence and before POK rising edge.
Delay 1 Time Sett ing:
Register Definition
REG0E REGCTRL Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e DSM LDO_PDWN PSR5DIS PSR4DIS PSR2DIS PSR3DIS PSR1D IS LDODIS
Pow er On Default 0 1 0 0 0 0 0 0
Bit Nam e Bit Definition
Register Definition
REG0F SETCTRL Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e Reserved BUSY Reserved CMD[1:0]
Pow er On Default 0 0 0 0 0 0 0 0
Bit Nam e Bit Definition
OT P Memory Bus y:
BUSY
0: New operation can be commanded.
1: No new operation can be commanded; all registers are loc ked; writing operation will not have effect.
Command:
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e Reserved TEMPFL PSR5FL PSR4FL PSR2FL PSR3FL PSR1FL LDOFL
Read/Write R R R R R R R R
Pow er On Default 0 0 0 0 0 0 0 0
Bit Nam e Bit Definition
Temperature Fault:
TEMPFL
0: No fault.
1: Temperature fault detected.
Register Definition
REG11 TEMPEN Register
Data Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Nam e Reserved AL1 AL0 CR[1:0] SD
Pow er On Default 0 0 0 0 0 1 0 0
Bit Nam e Bit Definition
ALERT1 Status:
AL1
0: ALERT1 is not ass erted.
1: ALERT1 is as serted.
ALERT0 Status:
AL0
0: ALERT0 is not ass erted.
1: ALERT0 is as serted.
Temperature Conversion Rate:
00: 0.25Hz
CR[1:0]
01: 1Hz
10: 4Hz (Default:APW7705A/B/C/D)
11: 8Hz
Temperature Conversion Shut down:
SD
0: Temperature Conversion is not shut down. (D efault:APW7705A/B/ C/D)
1: Temperature Conversion is shut down
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name TEMPREG[7:0]
Re ad/Write R R R R R R R R
Power On De fault
Bit Name Bit Definition
Temperature Readout According To External Temperature Information(via TS pin):
Register Definition
REG13 THIGH Register
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name THIGH[7:0]
Power On De fault 0 0 1 1 0 0 1 0
Bit Name Bi t Definition
Da ta Bit D7 D6 D5 D4 D3 D2 D1 D0
Bit Name TLOW[7:0]
Power On De fault 0 0 0 0 0 0 0 0
Bit Name Bi t Definition
Package Information
TQFN5x5-36
D A
b
Pin1
D2 A1
A3
NX
aaa c
Pin 1 Corner
E2
L K
S TQFN5*5-36
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.20 0.30 0.008 0.012
D 4.90 5.10 0.193 0.201
OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 A
OD1 B
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.10
-0.00 -0.20
TQFN 5x5 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.10 1.5 MIN. 5.35±0.20 5.35±0.20 1.00±0.20
-0.00 -0.40
(mm)
Classification Profile
Customer Service
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838