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ZZZ0 ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 PCB DAZ0I200101

MB DA60000KP10
PCB LA-7071P LS-7071P LS-7074P LS-7075P LA-7076P USB IO/B DA60000KQ10
M/B M/B USB IO/B HDD/B LED/B TP/B
DAZ@ DA@ DA@ DA@ DA@ DA@ HDD/B DA400011R10
LED/B DA400011T10
TP/B DA400013910
1 1

Compal Confidential
2
P1VE6 LA7071P Schematics Document 2

AMD Ontario Processor with DDRIII + Hudson M1

11.6" M/B

2011-03-17 3

Rev : 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 1 of 37
A B C D E
A B C D E

Compal Confidential
Model Name : P1VE6 Brazos Platform
File Name : LA-7071P
HDMI
1 AMD Memory Bus (DDRIII) 1

RGB
Dual Channel 204 Pin DDRIII SO-DIMM x2
LVDS Ontario FT1
APU 1.5V DDRIII 800/1066 BANK 0, 1, 2, 3
6.4G/8.5G
BGA 413-Ball Page 7 , 8
100M/133M
19mm X 19mm
Page 4,5,6

HDMI Conn. D-Sub Conn. LVDS Conn. UMI x4


Page 10 Page 11 Page 9
Gen.1 USB Conn.x2 USB Conn.x1 Camera Bluetooth Card Reader
(Left Side) (Right Side) RTS 5138
2.5GT/s Port 5 Port 7
Port 0 , 1 Port 2
per Lane IO/B Page 25 Page 9 Page 20
Port 6 Page 19
2
Fan Circuit 2

PWM Page 27 USB 3.3V 48MHz


PCI-Express X3 AMD
Hudson M1 HD Audio 3.3V 24MHz
100MHz PCIE Gen1 2.5GT/S FCH SATA 3G Card
Gen1 1.5GT/S ,Gen2 3GT/S 100MHz
Port 1 Port 3 Port 2 BGA 605-Ball Port 3, 9
23mm X 23mm Page 20
WWAN WLAN LAN(10/100) Page 12 ~ 16
JMINI1 JMINI2
AR8158 SIM Card
Media processor Wireless Card HDD
Port 1 Port 3 Port 2
Page 20 Page 21 Page 18
(2.5") Port 4
LPC Port 0 Page 20
Page 22
33MHz
3 3

RJ-45 WLAN
Page 18
Port 8
ENE KB930 Page 21
Page 26 Small Board

IO/B HDD/B HDA Codec+AMP


LS-7071P LS-7074P
CX20584
Page 17

RTC Ckt. LED/B TP BTN/B


Page 12 LS-7072P LS-7073P
BIOS ROM HP Jack x1
MIC Jack x1
4 2MB 4

Power Button Page 27 IO/B


Page 23

Security Classification Compal Secret Data Compal Electronics, Inc.


DC/DC Interface Ckt. Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

Page 28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 2 of 37
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A B C D E

Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1


Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 NC

APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
NC
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
USB2.0 PCIE3 SATA3 NC
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Left conn PCIE0 NC SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 Left conn PCIE1 WWAN SATA5 NC

FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Right conn PCIE2 LAN
+1.1VALW 1.1V always on power rail ON ON ON*
Port3 WWAN PCIE3 WLAN
+3VS 3.3V switched power rail ON OFF OFF
+1.5VS 1.5VS switched power rail ON OFF OFF Port4 SIM
+5VALW 5V always on power rail ON ON ON*
Port5 USB Camera
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON* Port6 CardReader
+RTCBATT RTC power ON ON ON
Port7 BT
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 WiMax

2 Port9 WWAN 2
EC SM Bus1 address EC SM Bus2 address
Port10 NC
Device Address HEX Device Address HEX
Smart Battery 0001-011xb 16H SB-TSI 1001-100xb 98H
Port11 NC
Port12 NC
Port13 NC

SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Board ID / SKU ID Table for AD channel
Vcc +3VALW
Device Address HEX
Ra 100K +/- 5%
APU SIC/SID (FCH_SMB3) Board ID Rb V AD_BID min V AD_BID typ V AD_BID max PCB Revision
H_THERMTRIP# (FCH_ALERT#) 0 0 0 V 0 V 0 V
* 0.1
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 0.2
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
3
SM Bus Controller 1 (FCH_SMB0) 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 3

5 100K +/- 5% 1.453 V 1.650 V 1.759 V


Device Address HEX
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 7 NC 2.500 V 3.300 V 3.300 V

SMBUS Control Table


BOM Structure Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU
EC_SMB_CK1 KB930
EC_SMB_DA1 V
HDMI@ : HDMI function
EC_SMB_CK2 KB930
BT@ : BT function EC_SMB_DA2 V
CONN@ : Connetors
HDMI_DATA APU FT1
45@ : 45 Level HDMI_CLK V
3G@ : 3G function
EDID_DATA APU FT1
N3G@ : None 3G function EDID_CLK V
4 4
CMBS@ : Combo Jack POPO noise Solution
FCH_SMDAT0 FCH M1
NCMBS@: None Combo Jack POPO noise Solution FCH_SMCLK0 V V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 3 of 37
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5 4 3 2 1

APU C50 P/N change to SA00004KD50 R9 R352 Display


Tock 2010/12/30
mount @ LVDS
SA00004KD50 *
U1B @ mount eDP
APU_SVD
+1.8VS C1 .1U_0402_16V7K HDMI_TX2P_C DP_ZVSS R1 2 150_0402_1%

DISPLAYPORT 1
<10> HDMI_TX2P 1 2 A8 TDP1_TXP0 DP_ZVSS H3 1
@ C6 .1U_0402_16V7K HDMI_TX2N_C

DP MISC
1 <10> HDMI_TX2N 1 2 B8
TDP1_TXN0
DP_BLON G2 APU_ENBKL <26>
C433 C2 1 2 .1U_0402_16V7K HDMI_TX1P_C B9 H2
<10> HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD <9>
100P_0402_50V8J C3 1 2 .1U_0402_16V7K HDMI_TX1N_C A9 H1
D APU_SVC 2 <10> HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM <9> D
R3 1 2 1K_0402_5%
R4 1 2 1K_0402_5% APU_SVD C7 1 2 .1U_0402_16V7K HDMI_TX0P_C D10
<10> HDMI_TX0P HDMI_TX0N_C TDP1_TXP2 HDMI_CLK
C8 1 2 .1U_0402_16V7K C10 B2
<10> HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK <10>
C2 HDMI_DATA HDMI_DATA <10>
R8 TEST_25_L APU_SVC HDMI_CLKP_C TDP1_AUXN
1 2 510_0402_1% <10> HDMI_CLKP
C4 1 2 .1U_0402_16V7K A10 8/25 Pull-up 100k(@ R352) to +3VS
R6 TEST36 HDMI_CLKN_C TDP1_TXP3
1 2 1K_0402_5% <10> HDMI_CLKN
C5 1 2 .1U_0402_16V7K B10 C1 HDMI_DET <10>
@ 1
TDP1_TXN3 TDP1_HPD on LTDP0_HPD for eDP
+3VS B5 A3 EDID_CLK
<9> LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_CLK <9>
C432 EDID_DATA R352 1 @ 2 100K_0402_5%

DISPLAYPORT 0
<9> LVDS_A2# A5 LTDP0_TXN0 LTDP0_AUXN B3 EDID_DATA <9> +3VS
R10 1 2 10K_0402_5% HDMI_DATA 100P_0402_50V8J
R11 HDMI_CLK 2 LTDP0_HPD
1 2 10K_0402_5% <9> LVDS_A1 D6 LTDP0_TXP1 LTDP0_HPD D3 R9 1 2 100K_0402_5%
Reserve C432, C433, C434, C435 <9> LVDS_A1# C6
LTDP0_TXN1
Michael 2010/11/18 C12 eDP@
DAC_RED DAC_RED <11>
R13 1 2 1K_0402_5% APU_PROCHOT# A6 D13 R12 1 2 150_0402_1% R389 1 2 0_0402_5% DMIC_CLK
APU_ALERT#_R APU_SID <9> LVDS_A0 LTDP0_TXP2 DAC_REDB DMIC_CLK <9,17>
R14 1 2 1K_0402_5% B6 A12
<9> LVDS_A0# LTDP0_TXN2 DAC_GREEN DAC_GRN <11>
R16 1 2 1K_0402_5% APU_SIC B12 R15 1 2 150_0402_1%
APU_SID DAC_GREENB
R17 1 2 1K_0402_5% @ D8 A13 Reserve R389 for eDP function

VGA DAC
1 <9> LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU <11>
C8 B13 R18 1 2 150_0402_1% Tock 2010/12/30
<9> LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
C435
Change R10, R11 to RP1 100P_0402_50V8J <12> APU_CLK V2 E1 CRT_HSYNC <11>
2 CLKIN_H DAC_HSYNC
Michael 2010/12/23 <12> APU_CLK# V1
CLKIN_L DAC_VSYNC
E2 CRT_VSYNC <11>

CLK
<12> DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <11>
<12> DISP_CLK# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <11>
C405 1 2 100P_0402_50V8J LDT_RST# J1 D12 DAC_ZVSS R19 1 2 499_0402_1%
<36> APU_SVC SVC DAC_ZVSS
Power Circuit <36> APU_SVD
J2
SVD

SER
10/05 Add 100p(C405) on LDT_RST# APU_SIC TEST4
R1

APU_SID
P3 SIC TEST5 R2 10/01 Remove T1,T3~T7,T11,T12,T31,T32
APU_SIC
9/9 Change R24 from @ to mount R26 from mount to @ P4 SID TEST6 R6
T5
TEST14 TEST15 R20
9/15 Change R24 from mount to @ <12> LDT_RST# T3 E4 1 2 1K_0402_5%
C @ RESET_L TEST15 C
1 <12> APU_PWRGD T4 K4

CTRL
PWROK TEST16
L1
C434 APU_PROCHOT# TEST17 TEST18 R21
U1 L2 1 2 1K_0402_5%
APU_PROCHOT# APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19 R22
100P_0402_50V8J M2 1 2 1K_0402_5%

TEST
@ 2 R24 1 @ APU_ALERT#_R T2 THERMTRIP_L TEST19 TEST25_H
1 <14> APU_ALERT#_FCH 2 0_0402_5% ALERT_L TEST25_H K1 R25 1 2 510_0402_1%
R26 1 @ 2 0_0402_5% K2 TEST_25_L
<26> APU_ALERT#_EC TEST25_L
C429 APU_TDI N2 L5
APU_TDO TDI TEST28_H
100P_0402_50V8J Connection to EC, FCH input need to pull-down N1
TDO TEST28_L
M5
2 APU_TCK TEST31
P1 TCK TEST31 M21 PAD T8

JTAG
Add C429 for APU_PROCHOT# APU_TMS P2 J18 TEST33_H C9 1 2 0.1U_0402_16V4Z R28 1 2 51_0402_1%
APU_TRST# TMS TEST33_H TEST33_L C10 1
Michael 2010/11/18 M4 TRST_L TEST33_L J19 2 0.1U_0402_16V4Z R29 1 2 51_0402_1%
APU_DBRDY M3 U15
Close to APU APU_DBREQ# DBRDY TEST34_H
M1 DBREQ_L TEST34_L T15
H4 TEST35 R30 1 @ 2 1K_0402_5%
TEST35
R23 1 @ 2 0_0402_5% APU_PROCHOT# <36> APU_VDDNB_RUN_FB_H F4 N5 TEST36
<12> FCH_PROCHOT# VDDCR_NB_SENSE TEST36 TEST37
Power Circuit <36> APU_VDD0_RUN_FB_H G1
VDDCR_CPU_SENSE TEST37
R5 PAD T13 R386 1 2 1K_0402_5% +1.8VS
R27 1 2 0_0402_5% T14PAD F3
<26> EC_PROCHOT# VDDIO_MEM_S_SENSE
9/9 Add R386 (1k@) to +1.8VS on TEST35
R379 1 2 0_0402_5% F1
<36> APU_VDD0_RUN_FB_L VSS_SENSE
Power Circuit R380 1 TEST38 K3 9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)
<36> APU_VDDNB_RUN_FB_L 2 0_0402_5% B4 T1 ALLOW_STOP# <12>
+3VS RSVD_1 DMAACTIVE_L
W11
RSVD_2 R31
V5 1 2 1K_0402_5% +1.8VS
RSVD_3
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! ALLOW_STOP#
1

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L @ 1


R32 8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P
10K_0402_5% C438
2

<BOM Structure> 100P_0402_50V8J


R33 2
2

1K_0402_5% Reserve C438 for ALLOW_STOP#


2
B

B B
Michael 2010/11/18
1

Q1
E

APU_THERMTRIP# 3 1 H_THERMTRIP# <13>


C

MMBT3904_NL_SOT23-3

1 2 +1.8VS
R34 @ 0_0402_5% 9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32
If FCH internal pull-up disabled, level-shifter could be deleted.
APU_TRST# R37 1 1K_0402_5%
Need BIOS to disable internal pull-up!! 9/20 Delete R41~R43 AMD Debug 2
APU_TDI R38 2 1 1K_0402_5%
+3VS APU_TMS R36 2 1 1K_0402_5%
2N7002DW-T/R7 APU_TCK R35 2 1 1K_0402_5%
1

R39
Vgs(th): min 1.0V
APU_PWRGD
10K_0402_5% Typ 1.6V
@ 1
Max 2.0V
2

C421 T29PAD APU_TDO


If Q8 or R429, R432 implemented, 2
100P_0402_50V8J
@ APU_PWRGD R5 2 1 300_0402_5%
EC side pull-up need to be mounted
2
G

LDT_RST# R7 2 1 300_0402_5%
DMN66D0LDW-7_SOT363-6
T30PAD APU_DBRDY
APU_SID 1 6 EC_SMB_DA 1 @ 2 FCH_SID T0 FCH Reserve C421 for APU_PWRGD
R47 0_0402_5% FCH_SID <13> APU_DBREQ# R2 1 300_0402_5%
D
S

Michael 2010/11/18 2
1 2 EC_SMB_DA2 TO EC
A @ R48 0_0402_5% EC_SMB_DA2 <26> A
Q2A
1 2
R49 0_0402_5%
8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
5
G

DMN66D0LDW-7_SOT363-6

APU_SIC 4 3 EC_SMB_CK 1
R50
@ 2
0_0402_5%
FCH_SIC
FCH_SIC <13> T0 FCH
Security Classification Compal Secret Data Compal Electronics, Inc.
D

2010/11/09 2012/11/09 Title


S

EC_SMB_CK2
Issued Date Deciphered Date
1 2 TO EC
@ R51 0_0402_5%
EC_SMB_CK2 <26>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT1 CTRL/DP/CRT
Q2B 1 2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R52 0_0402_5% Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 4 of 37
5 4 3 2 1
A B C D E

DDR_A_D[0..63]
DDR_A_D[0..63] <7,8>
DDR_A_MA[0..15]
DDR_A_MA[0..15] <7,8>
DDR_A_DM[0..7]
DDR_A_DM[0..7] <7,8>
U1E
DDR_A_MA0 R17 B14 DDR_A_D0
DDR_A_MA1 M_ADD0 M_DATA0 DDR_A_D1
H19 A15
DDR_A_MA2 M_ADD1 M_DATA1 DDR_A_D2
J17 A17
DDR_A_MA3 M_ADD2 M_DATA2 DDR_A_D3
H18 D18
DDR_A_MA4 M_ADD3 M_DATA3 DDR_A_D4
H17 A14
DDR_A_MA5 M_ADD4 M_DATA4 DDR_A_D5
G17 C14
DDR_A_MA6 M_ADD5 M_DATA5 DDR_A_D6
H15 C16
DDR_A_MA7 M_ADD6 M_DATA6 DDR_A_D7
G18 D16
4 DDR_A_MA8 M_ADD7 M_DATA7 4
F19
DDR_A_MA9 M_ADD8 DDR_A_D8
E19 C18
DDR_A_MA10 M_ADD9 M_DATA8 DDR_A_D9
T19 A19
DDR_A_MA11 M_ADD10 M_DATA9 DDR_A_D10
F17 B21
DDR_A_MA12 M_ADD11 M_DATA10 DDR_A_D11
E18 D20
DDR_A_MA13 M_ADD12 M_DATA11 DDR_A_D12
W17 A18
DDR_A_MA14 M_ADD13 M_DATA12 DDR_A_D13
E16 B18
DDR_A_MA15 M_ADD14 M_DATA13 DDR_A_D14
G15 A21
M_ADD15 M_DATA14

DDR SYSTEM MEMORY


C20 DDR_A_D15 8/22 Delete C11~C18 (No VGA)
M_DATA15
<7,8> DDR_A_BS0 R18
M_BANK0 DDR_A_D16
<7,8> DDR_A_BS1 T18 C23
M_BANK1 M_DATA16 DDR_A_D17
<7,8> DDR_A_BS2 F16
M_BANK2 M_DATA17
D23
DDR_A_D18
9/6 Change PCI-E from FCH to APU
F23
DDR_A_DM0 M_DATA18 DDR_A_D19
D15 F22
DDR_A_DM1 M_DM0 M_DATA19 DDR_A_D20
DDR_A_DM2
B19
M_DM1 M_DATA20
C22
DDR_A_D21
9/6 Update PCI-E port List
D21 D22
DDR_A_DM3 M_DM2 M_DATA21 DDR_A_D22
DDR_A_DM4
H22
M_DM3 M_DATA22
F20
DDR_A_D23
9/15 Change PCI-E from APU to FCH
P23 F21
DDR_A_DM5 M_DM4 M_DATA23
V23
DDR_A_DM6 M_DM5 DDR_A_D24
AB20 H21
DDR_A_DM7 M_DM6 M_DATA24 DDR_A_D25
AA16 H23
M_DM7 M_DATA25 DDR_A_D26 U1A
K22
DDR_A_DQS0 M_DATA26 DDR_A_D27
<7,8> DDR_A_DQS0
A16 K21 AA6 AB6
DDR_A_DQS#0 M_DQS_H0 M_DATA27 DDR_A_D28 P_GPP_RXP0 P_GPP_TXP0
<7,8> DDR_A_DQS#0 B16 G23 Y6 AC6
DDR_A_DQS1 M_DQS_L0 M_DATA28 DDR_A_D29 P_GPP_RXN0 P_GPP_TXN0
<7,8> DDR_A_DQS1 B20 H20
DDR_A_DQS#1 M_DQS_H1 M_DATA29 DDR_A_D30
A20 K20 AB4 AB3

PCIE I/F
<7,8> DDR_A_DQS#1 DDR_A_DQS2 M_DQS_L1 M_DATA30 DDR_A_D31 P_GPP_RXP1 P_GPP_TXP1
<7,8> DDR_A_DQS2 E23 K23 AC4 AC3
DDR_A_DQS#2 M_DQS_H2 M_DATA31 P_GPP_RXN1 P_GPP_TXN1
<7,8> DDR_A_DQS#2
E22
DDR_A_DQS3 M_DQS_L2 DDR_A_D32
<7,8> DDR_A_DQS3 J22 N23 AA1 Y1
DDR_A_DQS#3 M_DQS_H3 M_DATA32 DDR_A_D33 P_GPP_RXP2 P_GPP_TXP2
<7,8> DDR_A_DQS#3 J23 P21 AA2 Y2
DDR_A_DQS4 M_DQS_L3 M_DATA33 DDR_A_D34 P_GPP_RXN2 P_GPP_TXN2
<7,8> DDR_A_DQS4
R22 T20
DDR_A_DQS#4 M_DQS_H4 M_DATA34 DDR_A_D35
<7,8> DDR_A_DQS#4 P22 T23 Y4 V3
3 DDR_A_DQS5 M_DQS_L4 M_DATA35 DDR_A_D36 P_GPP_RXP3 P_GPP_TXP3 3
<7,8> DDR_A_DQS5
W22 M20 Y3 V4
DDR_A_DQS#5 M_DQS_H5 M_DATA36 DDR_A_D37 P_GPP_RXN3 P_GPP_TXN3
<7,8> DDR_A_DQS#5 V22 P20
DDR_A_DQS6 M_DQS_L5 M_DATA37 DDR_A_D38 P_ZVDD_10 R54 1.27K_0402_1%
<7,8> DDR_A_DQS6 AC20 R23 +1.05VS 1 2 Y14 AA14 P_ZVSS 1 2
DDR_A_DQS#6 M_DQS_H6 M_DATA38 DDR_A_D39 R53 2K_0402_1% P_ZVDD_10 P_ZVSS
<7,8> DDR_A_DQS#6
AC21 T22
M_DQS_L6 M_DATA39
<7,8> DDR_A_DQS7
DDR_A_DQS7 AB16
M_DQS_H7
Less than 1"
DDR_A_DQS#7 AC16 V20 DDR_A_D40 Less than 1"
<7,8> DDR_A_DQS#7 M_DQS_L7 M_DATA40 DDR_A_D41 UMI_TX0P_C C19 .1U_0402_16V7K
V21 <12> UMI_RX0P AA12 AB12 1 2 UMI_TX0P <12>
DDR_A_CLK0 M_DATA41 DDR_A_D42 P_UMI_RXP0 P_UMI_TXP0 UMI_TX0N_C C20 .1U_0402_16V7K
<7> DDR_A_CLK0 M17 Y23 <12> UMI_RX0N Y12 AC12 1 2 UMI_TX0N <12>
DDR_A_CLK#0 M_CLK_H0 M_DATA42 DDR_A_D43 P_UMI_RXN0 P_UMI_TXN0
<7> DDR_A_CLK#0 M16 Y22
DDR_A_CLK1 M_CLK_L0 M_DATA43 DDR_A_D44 UMI_TX1P_C C21 .1U_0402_16V7K
<7> DDR_A_CLK1 M19 T21 <12> UMI_RX1P AA10 AC11 1 2 UMI_TX1P <12>
DDR_A_CLK#1 M_CLK_H1 M_DATA44 DDR_A_D45 P_UMI_RXP1 P_UMI_TXP1 UMI_TX1N_C C22 .1U_0402_16V7K
M18 U23 Y10 AB11 1 2

UMI I/F
<7> DDR_A_CLK#1 M_CLK_L1 M_DATA45 <12> UMI_RX1N P_UMI_RXN1 P_UMI_TXN1 UMI_TX1N <12>
DDR_B_CLK2 N18 W23 DDR_A_D46
<8> DDR_B_CLK2 M_CLK_H2 M_DATA46
DDR_B_CLK#2 N19 Y21 DDR_A_D47 <12> UMI_RX2P AB10 AA8 UMI_TX2P_C C23 1 2 .1U_0402_16V7K
<8> DDR_B_CLK#2 M_CLK_L2 M_DATA47 P_UMI_RXP2 P_UMI_TXP2 UMI_TX2P <12>
DDR_B_CLK3 L18 <12> UMI_RX2N AC10 Y8 UMI_TX2N_C C24 1 2 .1U_0402_16V7K
<8> DDR_B_CLK3 M_CLK_H3 P_UMI_RXN2 P_UMI_TXN2 UMI_TX2N <12>
DDR_B_CLK#3 L17 Y20 DDR_A_D48
<8> DDR_B_CLK#3 M_CLK_L3 M_DATA48
AB22 DDR_A_D49 <12> UMI_RX3P AC7 AB8 UMI_TX3P_C C25 1 2 .1U_0402_16V7K
M_DATA49 P_UMI_RXP3 P_UMI_TXP3 UMI_TX3P <12>
DDR_RST# L23 AC19 DDR_A_D50 <12> UMI_RX3N AB7 AC8 UMI_TX3N_C C26 1 2 .1U_0402_16V7K
<7,8> DDR_RST# M_RESET_L M_DATA50 P_UMI_RXN3 P_UMI_TXN3 UMI_TX3N <12>
<7,8> DDR_EVENT# DDR_EVENT# N17 AA18 DDR_A_D51
M_EVENT_L M_DATA51 DDR_A_D52 S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
AA23
M_DATA52 DDR_A_D53
AA20
DDR_CKE0 M_DATA53 DDR_A_D54
<7,8> DDR_CKE0 F15 AB19
DDR_CKE1 M_CKE0 M_DATA54 DDR_A_D55
<7,8> DDR_CKE1 E15 Y18
M_CKE1 M_DATA55
AC17 DDR_A_D56
M_DATA56 DDR_A_D57
Y16
DDR_A_ODT0 M_DATA57 DDR_A_D58
<7> DDR_A_ODT0 W19 AB14
DDR_A_ODT1 M0_ODT0 M_DATA58 DDR_A_D59
<7> DDR_A_ODT1 V15 AC14
DDR_B_ODT0 M0_ODT1 M_DATA59 DDR_A_D60
<8> DDR_B_ODT0 U19 AC18
DDR_B_ODT1 M1_ODT0 M_DATA60 DDR_A_D61
<8> DDR_B_ODT1 W15 AB18
M1_ODT1 M_DATA61 DDR_A_D62
AB15
DDR_CS0_DIMMA# M_DATA62 DDR_A_D63
<7> DDR_CS0_DIMMA# T17 AC15
DDR_CS1_DIMMA# M0_CS_L0 M_DATA63
<7> DDR_CS1_DIMMA# W16
2 DDR_CS0_DIMMB# M0_CS_L1 2
<8> DDR_CS0_DIMMB# U17
DDR_CS1_DIMMB# M1_CS_L0 +MEM_VREF
<8> DDR_CS1_DIMMB# V16 M23
M1_CS_L1 M_VREF
DDR_A_RAS# U18
<7,8> DDR_A_RAS# M_RAS_L
DDR_A_CAS# V19 R55
<7,8> DDR_A_CAS# M_CAS_L
DDR_A_WE# V17 M22 +M_ZVDDIO 2 1 +1.5V
<7,8> DDR_A_WE# M_WE_L M_ZVDDIO_MEM_S
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! 39.2_0402_1%

9/11 Delete DDR Signal link to JDIMM2

+1.5V
2

Reserve C439 for DDR_EVENT#


+1.5V Michael 2010/11/18 R56
1K_0402_1%

R57 1 2 DDR_EVENT#
1

1K_0402_5% +MEM_VREF
2

@ 1 1 1
R58 C27 C28
1 C439 1K_0402_1% 1
100P_0402_50V8J 1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2
1

Place within 1000 mils to APU


20100526 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT1 DDRIII/UMI/PCIE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 5 of 37
A B C D E
5 4 3 2 1

+APU_CORE

+1.8VS
4500 mA
2000 mA
U1C L1
+APU_CORE +VDD_18 2 1 U1D

TSense/PLL/DP/PCIE/IO
E5 U8 FBMA-L11-201209-221LMA30T_0805 A7 N13
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
180P_0402_50V8J
VDDCR_CPU_1 VDD_18_1 VSS_1 VSS_50
1 1 1 1 1 1 1 E6 W8 1 1 1 1 1 1 1 B7 N20
VDDCR_CPU_2 VDD_18_2 VSS_2 VSS_51
C31

C29

C32

C41

C42

C30

C33

C34

C35

C36

C37

C38

C39

C40
F5 U6 B11 N22
D VDDCR_CPU_3 VDD_18_3 VSS_3 VSS_52 D
F7 U9 B17 P10
VDDCR_CPU_4 VDD_18_4 VSS_4 VSS_53
G6 W6 B22 P14
2 2 2 2 2 2 2 VDDCR_CPU_5 VDD_18_5 2 2 2 2 2 2 2 VSS_5 VSS_54
G8 T7 C4 R4
VDDCR_CPU_6 VDD_18_6 VSS_6 VSS_55
H5 V7 D5 R7
VDDCR_CPU_7 VDD_18_7 VSS_7 VSS_56

CPU CORE
H7 D7 R20
VDDCR_CPU_8 VSS_8 VSS_57
J6 D9 T6
VDDCR_CPU_9 VSS_9 VSS_58
J8 D11 T9
VDDCR_CPU_10 VSS_10 VSS_59
L7 D14 T11
VDDCR_CPU_11 VSS_11 VSS_60
M6 B15 T13
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
VDDCR_CPU_12 VSS_12 VSS_61
1 1 1 1 1 1 M8 D17 U4
VDDCR_CPU_13 VSS_13 VSS_62
C43

C44

C45

C46

C47

C48
N7 D19 U5
VDDCR_CPU_14 +1.8VS VSS_14 VSS_63
8000 mA R8
VDDCR_CPU_15
E7
VSS_15 VSS_64
U7

GND
2 2 2 2 2 2 +APU_CORE_NB
W = 20 mil / Spcae = 20 mil E9
VSS_16 VSS_65
U12
L2 E12 U20
VSS_17 VSS_66

DAC
E8 W9 +VDD_18_DAC 2 1 E20 U22
VDDCR_NB_1 VDD_18_DAC VSS_18 VSS_67
E11 F8 V8

10U_0603_6.3V6M
180P_0402_50V8J
VDDCR_NB_2 FBMA-L11-201209-221LMA30T_0805 VSS_19 VSS_68
E13 1 1 1 F11 V9

1U_0402_6.3V6K
VDDCR_NB_3 VSS_20 VSS_69

C49

C50

C51
F9 F13 V11
VDDCR_NB_4 VSS_21 VSS_70
F12
VDDCR_NB_5 8/25 Change +1.0VS to +1.05VS G4
VSS_22 VSS_71
V13

GPU AND NB CORE


G11
G13
VDDCR_NB_6
VDDCR_NB_7
POWER 2 2 2
G5
G7
VSS_23
VSS_24
VSS_72
VSS_73
W1
W2
H9 +1.05VS G9 W4
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
VDDCR_NB_8 VSS_25 VSS_74
1 1 1 1 1 H12 G12 W5
VDDCR_NB_9 VSS_26 VSS_75
C52

C53

C54

C55

C56
K11
VDDCR_NB_10 W = 15 mil / Spcae = 20 mil G20
VSS_27 VSS_76
W7
K13 L3 G22 W12
VDDCR_NB_11 VSS_28 VSS_77

DIS PLL
L10 U11 +VDDL_10 2 1 H6 W20
2 2 2 2 2 VDDCR_NB_12 VDDPL_10 VSS_29 VSS_78
L12 H11 Y5

.1U_0402_16V7K

1U_0402_6.3V6K
180P_0402_50V8J

10U_0603_6.3V6M
VDDCR_NB_13 FBMA-L11-201209-221LMA30T_0805 VSS_30 VSS_79
L14 1 1 1 1 H13 Y7
VDDCR_NB_14 VSS_31 VSS_80

C57

C58

C59

C60
M11 J4 Y9
VDDCR_NB_15 VSS_32 VSS_81
M12 J5 Y11
VDDCR_NB_16 VSS_33 VSS_82
M13 J7 Y13
VDDCR_NB_17 2 2 2 2 VSS_34 VSS_83
N10 J20 Y15
VDDCR_NB_18 VSS_35 VSS_84
+APU_CORE_NB
N12
VDDCR_NB_19 5500 mA K10
VSS_36 VSS_85
Y17
N14 L4 K14 Y19
VDDCR_NB_20 VSS_37 VSS_86

PCIE/IO/DDR3 Phy
P11 +VDD_10 2 1 L4 AA4
VDDCR_NB_21 VSS_38 VSS_87
2000 mA P13 U13 L6 AA22

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
180P_0402_50V8J
VDDCR_NB_22 VDD_10_1 FBMA-L11-201209-221LMA30T_0805 VSS_39 VSS_88
W13 1 1 1 1 1 1 1 L8 AB2
+1.5V VDD_10_2 VSS_40 VSS_89

C61

C62

C63

C64

C65

C66

C67
C V12 L11 AB5 C
VDD_10_3 VSS_41 VSS_90
G16 T12 L13 AB9
VDDIO_MEM_S_1 VDD_10_4 VSS_42 VSS_91
G19 L20 AB13
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

VDDIO_MEM_S_2 2 2 2 2 2 2 2 VSS_43 VSS_92


1 1 1 1 1 E17 L22 AB17
VDDIO_MEM_S_3 VSS_44 VSS_93
C68

C69

C70

C71

C72

J16 M7 AB21
VDDIO_MEM_S_4 VSS_45 VSS_94

DDR3
L16 N4 AC5
VDDIO_MEM_S_5 VSS_46 VSS_95
L19 N6 AC9
2 2 2 2 2 VDDIO_MEM_S_6 VSS_47 VSS_96
N16 N8 AC13
VDDIO_MEM_S_7 VSS_48 VSS_97
R16 N11 A11

DP Phy/IO
VDDIO_MEM_S_8 +3VS VSS_49 VSSBG_DAC
R19
VDDIO_MEM_S_9 500 mA
W18 R333
VDDIO_MEM_S_10 +VDD_33 S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
U16 A4 1 2
VDDIO_MEM_S_11 VDD_33 0_0603_5%

.1U_0402_16V7K

1U_0402_6.3V6K
1 1

C73

C74
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

1 1 1 1 1 1 1 2 2
C75

C76

C77

C78

C79

C80

C81

8/22 Reserve R333 ( 0 ohm 0603 )


2 2 2 2 2 2 2
+1.5V
10U_0603_6.3V6M

10U_0603_6.3V6M
1 1
C82

C83
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1 1 1 1 2 2
C84

C85

C86

C87

2 2 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
C88

C89

C90

C91
B B

POWER +1.05VS
2 2 2 2

9/20 Change C93 to SGA00004L00


1
10U_0603_6.3V6M

1
+
C92

C93
220U_D2_2VY_R15M
@ SGA00004L00 1 1 1 1 1
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

180P_0402_50V8J

2 2 180P_0402_50V8J
C94

C95

C96

C97

C98

2 2 2 2 2

9/15 Change C99,C100 to 470U(SGA00003K00)

+APU_CORE POWER
SGA00003K00 8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10)
8/25 Change C111 from poly-cap to E-cap (SF000002Z00)
1 1 By case (Along split)
+ +
1 9/11 Change C111 to SGA20331E10
C99 C100 C102 @
10U_0603_6.3V6M +1.5V
330U_D2_2V_Y 330U_D2_2V_Y
2 2 2

+1.5V
POWER +1.8VS
POWER

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J
+APU_CORE_NB Near CPU Socket 1 1 1 1 1 1 1 1

C103

C104

C105

C106

C107

C108

C109

C110
A 1 A
10U_0603_6.3V6M

1 1
22U_0805_6.3V6M

C112 + 2 2 2 2 2 2 2 2
C116

1
C111 + 330U_D2_2V_Y
C115

1
1 330U_D2_2V_Y @
+ C114 C117 2 2
2 2
330U_D2_2V_Y 10U_0603_6.3V6M
2 2
SGA20331E10 SGA20331E10

Near CPU Socket Near CPU Socket Near CPU Socket


Security Classification Compal Secret Data Compal Electronics, Inc.
SGA20331E10 Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

change C99,C100 from 470U to 330U , 2011/01/28 Tock THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P07-FT1 PWR/VSS
Size Document Number Rev
change C99,C100 footprint from C_D2 to C_X for placement AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 6 of 37
5 4 3 2 1
5 4 3 2 1

Change JDIMM1 socket to SP07000NN00


3500 mA
+1.5V +1.5V 2010/12/06 Tock
W=20mil Change JDIMM1 socket to SP07000NZ00 DDR_A_D[0..63] +1.5V +1.5V
JDIMM1 CONN@
+VREF_DQ 1 2 2010/12/14 Tock DDR_A_D[0..63] <5,8>
VREF_DQ VSS DDR_A_D4 DDR_A_MA[0..15]
3 VSS DQ4 4 DDR_A_MA[0..15] <5,8>

2
1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 DDR_A_DM[0..7] R59 R60
1 1 7 DQ1 VSS 8 DDR_A_DM[0..7] <5,8>

C118

C119
9 10 1K_0402_1% 1K_0402_1%
DDR_A_DM0 VSS DQS0# DDR_A_DQS#0 <5,8>
11 DM0 DQS0 12
DDR_A_DQS0 <5,8>
13 14

1
2 2 DDR_A_D2 VSS VSS DDR_A_D6
15 DQ2 DQ6 16 +VREF_DQ +VREF_CA
D DDR_A_D3 DDR_A_D7 D
17 DQ3 DQ7 18
19 20 DDR_RST#
VSS VSS

2
DDR_A_D8 21 22 DDR_A_D12 Reserve C413 for DDR_RST#
DDR_A_D9 DQ8 DQ12 DDR_A_D13 R61 R62
23
DQ9 DQ13
24 1 Michael 2010/11/18
25 26 @ 1K_0402_1% 1K_0402_1%
VSS VSS DDR_A_DM1 C413
<5,8> DDR_A_DQS#1 27 DQS1# DM1 28
29 30 DDR_RST# <5,8> 100P_0402_50V8J

1
<5,8> DDR_A_DQS1 DQS1 RESET# 2
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 44
VSS VSS DDR_A_DM2
45 46
<5,8> DDR_A_DQS#2 DQS2# DM2
47 48
<5,8> DDR_A_DQS2 DQS2 VSS DDR_A_D22
49 VSS DQ22 50
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS 54
55 56 DDR_A_D28
DDR_A_D24 VSS DQ28 DDR_A_D29
DDR_A_D25
57
DQ24 DQ29
58 9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)
59 60
DQ25 VSS
61 VSS DQS3# 62
DDR_A_DM3 DDR_A_DQS#3 <5,8>
63 DM3 DQS3 64
DDR_A_DQS3 <5,8>
65 66
DDR_A_D26 VSS VSS DDR_A_D30
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31 +1.5V
R396 71 72 R397
VSS VSS
1 2 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<5,8> DDR_CKE0 73 74 DDR_CKE1 <5,8> 2 2 2 2 2 2 2 2 2 2 2 2
100_0402_1% CKE0 CKE1 100_0402_1%
75 76
C VDD VDD DDR_A_MA15 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C
77 NC A15 78
<5,8> DDR_A_BS2 79 80 DDR_A_MA14 @ @ @ @ @ @
BA2 A14 1 1 1 1 1 1 1 1 1 1 1 1
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
DDR_A_MA8
87
VDD VDD
88
DDR_A_MA6
10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98 9/11 Change C137 to SGA00004L00
99 100
VDD VDD
<5> DDR_A_CLK0 101 CK0 CK1 102 DDR_A_CLK1 <5>
<5> DDR_A_CLK#0 103 104 DDR_A_CLK#1 <5>
CK0# CK1#
105 106
DDR_A_MA10 VDD VDD
107
109
A10/AP BA1
108
110
DDR_A_BS1 <5,8> CRB 0.1u X1 4.7u X1 CRB 100U X2
<5,8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <5,8>
111 112
VDD VDD +1.5V
<5,8> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <5>
WE# S0# +0.75VS
<5,8> DDR_A_CAS# 115 CAS# ODT0 116 DDR_A_ODT0 <5>
117 118
DDR_A_MA13 VDD VDD
119 120 DDR_A_ODT1 <5>
A13 ODT1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
<5> DDR_CS1_DIMMA# 121 122
S1# NC
123 124 2 2 1 1
VDD VDD

C134

C135

C136
125
TEST VREF_CA
126 +VREF_CA W=20mil +
127 128 C137
VSS VSS

1000P_0402_50V7K
DDR_A_D32 129 130 DDR_A_D36 @ @ 220U_6.3V_M
DQ32 DQ36 1 1 2

0.1U_0402_16V4Z
DDR_A_D33 131 132 DDR_A_D37 1
DQ33 DQ37 C132 2
133 134 1
VSS VSS

C133
135 136 DDR_A_DM4
<5,8> DDR_A_DQS#4 DQS4# DM4
137 138
<5,8> DDR_A_DQS4 DQS4 VSS DDR_A_D38 2
139 140
B DDR_A_D34 VSS DQ38 DDR_A_D39 2 B
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS DDR_A_D44
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 DQ40 DQ45 148 Place near JDIMM1
DDR_A_D41 149 150 SGA00004L00
DQ41 VSS
151 152
DDR_A_DM5 VSS DQS5# DDR_A_DQS#5 <5,8>
153
DM5 DQS5
154
DDR_A_DQS5 <5,8> change C137 to SF000002Y00
155 156
DDR_A_D42 157
VSS VSS
158 DDR_A_D46 2010/12/14 Tock
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167
VSS VSS
168
DDR_A_DM6
8/25 Change C137 from poly-cap to E-cap (SF000002Y00)
169 170
<5,8> DDR_A_DQS#6
171
DQS6# DM6
172 8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V
<5,8> DDR_A_DQS6 DQS6 VSS DDR_A_D54
173 174
DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
179 180
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186
DDR_A_DM7 VSS DQS7# DDR_A_DQS#7 <5,8>
187 DM7 DQS7 188
DDR_A_DQS7 <5,8>
189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
R63 10K_0402_5% 195 196 9/11 Remove C381
VSS VSS
1 2 197 198 DDR_EVENT# <5,8>
SA0 EVENT#
0.1U_0402_16V4Z
2.2U_0603_6.3V6K

+3VS 199 200


VDDSPD SDA FCH_SMDAT0 <8,13,20,21>
201 202
SA1 SCL FCH_SMCLK0 <8,13,20,21>
1 1 203 VTT VTT 204 +0.75VS
1

A
C138

C139

A
R64 205 206
GND1 GND2
207 BOSS1 BOSS2 208
2 2 10K_0402_5% 100 mA
2

FOX_AS0A621-U4RG-7H

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3 SODIMM-I Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 7 of 37
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
3500 mA Change JDIMM2 socket to SP07000NZ00 for reverse
W=20mil 2010/12/06 Tock
JDIMM2 CONN@ DDR_A_D[0..63]
Change JDIMM2 socket to SP07000NN00 DDR_A_D[0..63] <5,7>
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_A_D4 2010/12/14 Tock DDR_A_MA[0..15]
DDR_A_MA[0..15] <5,7>
VSS2 DQ4

1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 DDR_A_DM[0..7]
1 1 7 DQ1 VSS3 8 DDR_A_DM[0..7] <5,7>

C166

C160
9 10
DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS#0 <5,7>
11 DM0 DQS0 12
DDR_A_DQS0 <5,7>
13 14
@ 2 @ 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 DQ2 DQ6 16
D DDR_A_D3 DDR_A_D7 D
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
VSS9 VSS10 DDR_A_DM1
<5,7> DDR_A_DQS#1 27 DQS#1 DM1 28
29 30 DDR_RST# <5,7>
<5,7> DDR_A_DQS1 DQS1 RESET#
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14 DDR_RST#
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36 Reserve C414 for DDR_RST#
DQ11 DQ15
37 VSS13 VSS14 38 1 Michael 2010/11/18
DDR_A_D16 39 40 DDR_A_D20 @
DDR_A_D17 DQ16 DQ20 DDR_A_D21 C414
41 DQ17 DQ21 42
43 44 100P_0402_50V8J
VSS15 VSS16 DDR_A_DM2 2
45 46
<5,7> DDR_A_DQS#2 DQS#2 DM2
47 48
<5,7> DDR_A_DQS2 DQS2 VSS17 DDR_A_D22
49 VSS18 DQ22 50
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_A_D28
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS21
61 VSS22 DQS#3 62
DDR_A_DM3 DDR_A_DQS#3 <5,7>
63 DM3 DQS3 64
DDR_A_DQS3 <5,7>
65 66
DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31 +1.5V
71 72
VSS25 VSS26
@ R421 @ R401 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2
<5,7> DDR_CKE0 73 74 DDR_CKE1 <5,7>
C 100_0402_1% CKE0 CKE1 100_0402_1% C167 C145 C141 C144 C143 C140 C150 C154 C151 C149 C157 C155 C
75 VDD1 VDD2 76
77 78 DDR_A_MA15 @ @ @ @ @ @ @ @ @ @ @ @
NC1 A15 DDR_A_MA14 1 1 1 1 1 1 1 1 1 1 1 1
<5,7> DDR_A_BS2 79 80
BA2 A14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85
A9 A7
86 9/23 Reserve R421,R401 on CKE0 & CKE1(S3 hang Issue)
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6 10/11 Change R421 R401 from @ to mount (For A1 APU,B0 APU no Need)
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD9 VDD10 100
<5> DDR_B_CLK2 101 102 DDR_B_CLK3 <5>
CK0 CK1
<5> DDR_B_CLK#2 103 104 DDR_B_CLK#3 <5>
CK0# CK1#
DDR_A_MA10
105
107
VDD11 VDD12
106
108
CRB 0.1u X1 4.7u X1
A10/AP BA1 DDR_A_BS1 <5,7>
<5,7> DDR_A_BS0 109 110 DDR_A_RAS# <5,7>
BA0 RAS#
111 112
VDD13 VDD14 +0.75VS
<5,7> DDR_A_WE# 113 WE# S0# 114 DDR_CS0_DIMMB# <5>
<5,7> DDR_A_CAS# 115 116 DDR_B_ODT0 <5>
CAS# ODT0
117 118
VDD15 VDD16

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
DDR_A_MA13 119 120
A13 ODT1 DDR_B_ODT1 <5>
<5> DDR_CS1_DIMMB# 121 122 2 2 1
S1# NC2

C148

C153

C152
123 124
VDD17 VDD18
125
NCTEST VREF_CA
126 +VREF_CA W=20mil
127 128 @ @ @
VSS27 VSS28 1 1 2

1000P_0402_50V7K

0.1U_0402_16V4Z
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132 1 1
DQ33 DQ37
C146

C147
133 134
VSS29 VSS30 DDR_A_DM4
135 136
<5,7> DDR_A_DQS#4 DQS#4 DM4 @ @
137 138
B <5,7> DDR_A_DQS4 DQS4 VSS31 DDR_A_D38 2 2 B
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146 Place near JDIMM2
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS35
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS#5 <5,7>
153 154
DM5 DQS5 DDR_A_DQS5 <5,7>
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 DQ42 DQ46 158
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 DQ48 DQ52 164
DDR_A_D49 165 166 DDR_A_D53
DQ49 DQ53
167 VSS41 VSS42 168
169 170 DDR_A_DM6
<5,7> DDR_A_DQS#6 DQS#6 DM6
171 172
<5,7> DDR_A_DQS6 DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS47
185 VSS48 DQS#7 186
DDR_A_DM7 DDR_A_DQS#7 <5,7>
187 188
DM7 DQS7 DDR_A_DQS7 <5,7>
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
+3VS 191 DQ58 DQ62 192
DDR_A_D59 193 194 DDR_A_D63
@ R130 10K_0402_5% DQ59 DQ63
195 196
VSS51 VSS52
1 2 197 198 DDR_EVENT# <5,7>
SA0 EVENT#
+3VS 199 200
VDDSPD SDA FCH_SMDAT0 <7,13,20,21>
0.1U_0402_16V4Z
2.2U_0603_6.3V6K

201 SA1 SCL 202 FCH_SMCLK0 <7,13,20,21>


A A
1 1 203 204 +0.75VS
VTT1 VTT2
1

10K_0402_5%
C158

C159

R131

205 G1 G2 206
@ @ 100 mA
2 2 @ FOX_AS0A621-U4SG-7H
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3 SODIMM-II Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 8 of 37
5 4 3 2 1
5 4 3 2 1

Camera
11/02 Change Q3 PN to SB934130020 2 1
LCD POWER CIRCUIT 0_0402_5% R71
2011/02/11 Change Q3 PN to SB000006R10
J1
L5 @
+3VS 1 2 +CAM_VCC USB20_N5_1 1 2 USB20_N5 USB20_N5 <13>
+LCDVDD +LCDVDD Q3 +3VS 1 2 1 2
AO3413L_SOT23-3 1
JUMP_43X39 USB20_P5_1 USB20_P5
W=40mils W=40mils 4 4 3 3 USB20_P5 <13>

1
1 3 @ C161

S
R67 +3VALW WCM2012F2S-900T04_0805
D 2 D

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

G
470_0402_5% 0.1U_0402_16V4Z

2
C162 1 1 Remove C164 4.7U 2 1

2
C163 0_0402_5% R72
Michael 2010/11/18

2
6 +LCDVDD_R
R68 1 @ 9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing 9/23 Remove D1 C166 C167
C165 2 2
W=40mils 100K_0402_5% Change C163 BOM Struture to @ 9/23 Add D1 L5 R71 R72 C166 C167 for ESD 9/24 Swap L5
Michael 2010/11/18

1
2 0.047U_0402_16V4Z
D
Q32A 2 2 1
DMN66D0LDW-7_SOT363-6 G
R69 4.7K_0402_5%
S

1
8/31 Change R68.2 link to +3VALW

8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

3
D
5 Q32B
<4> APU_ENVDD G DMN66D0LDW-7_SOT363-6

S
4
2

R70
C 100K_0402_5% 8/26 Change Q3 to SB934130020 Standard Part C
1

9/9 Reserve 100k PD to GND on INVTPWM 9/17 Change R387 from @ to mount

10/04 Add 100p(C401) on INVT_PWM


CMOS & LCD/PANEL BD. Conn. 100K_0402_5%
R387 1 2 INVTPWM 0_0402_5% @ 1 R310
2 INVT_PWM <26> EC C401

Add R344 0
DMIC
ohm for +3VS_MIC
8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA 0_0402_5% 2 1 R311 APU_BLPWM <4> APU INVTPWM 2 1

Michael 2010/11/18 8/31 Update JLVDS1 Pin definition Delete R74 R76 +3VS 100P_0402_50V8J
9/13 Update LVDS Pin definition, Add R74,R76
Connect DMIC_CLK, 10/04 Change C401 on INVTPWM
DMIC_DATA 9/13 Add Net Name +3VS_DMIC 10/01 Remove R74,R76

2.2K_0402_5%

2.2K_0402_5%
to JLVDS1 pin 5 and 6

2
LVDS@ LVDS@
Michael 2010/11/18

R75

R73
JLVDS1 CONN@ 8/22 Reserve R327~R332( 0 ohm) for eDP
1 1
+3VS_MIC
USB20_P5_1
0_0402_5% 2 1 R344 +3VS R75 *
2 2 camera 8/31 Reserve R353 R354 on LVDS_ACLK

1
USB20_N5_1 100K_0402_5%
B 3 3 EDID_CLK_R R383 1 B
4 4 +CAM_VCC W=20mil 2
Display LVDS eDP
DMIC_CLK
5 5 DMIC_DATA DMIC_CLK <4,17> EDID_DATA_R eDP@
6 6 DMIC_DATA <17,26>DMIC
7 7 100K_0402_5% R327 0 ohm 0.1uF
LVDS_ACLK_R 0_0402_5% 2 LVDS@ 1 R353
8 8 LVDS_ACLK#_R 0_0402_5%
LVDS_ACLK <4>
9 2 LVDS@ 1 R354 LVDS_ACLK# <4>
eDP@
9
10 10 LVDS_A2_R
9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP SD028100380 R328 0 ohm 0.1uF
11 0_0402_5% 2 LVDS@ 1 R327 LVDS_A2 <4>
11 LVDS_A2#_R 0_0402_5% INVT_PWM
12 2 LVDS@ 1 R328 LVDS_A2# <4>
12
13 13 LVDS_A1_R 0_0402_5% 2 LVDS@ 1 R329 BKOFF# R381 0 ohm 0.1uF
14 14 LVDS_A1#_R 0_0402_5%
LVDS_A1 <4>
15 2 LVDS@ 1 R330 LVDS_A1# <4>
15
16 16 1 R382 0 ohm 0.1uF

1
17 LVDS_A0_R 0_0402_5% 2 LVDS@ 1 R331
17 LVDS_A0 <4>
18 LVDS_A0#_R 0_0402_5% 2 LVDS@ 1 R332 C168 C169
18 LVDS_A0# <4>
220P_0402_50V7K 1000P_0402_50V7K
19 19 R383 @ 100k ohm

2
EDID_DATA_R 0_0402_5% EDID_DATA 2
2 LVDS@ 1 R381 3G@ 3G@
20 20 EDID_CLK_R 0_0402_5% EDID_CLK
EDID_DATA <4>
2 LVDS@ 1 R382
21 21 BKOFF#
EDID_CLK <4>
22 22 INVTPWM BKOFF# <26> For RF R73 2.2k ohm @
23 23 +3VS_LVDS 0_0402_5%
24 2 1 R334 +3VS
24 +LCDVDD_L
31 GND1 25 25 1 2 +LCDVDD 8/22 Reserve R334(0402 0 ohm) R75 2.2k ohm 100k ohm
32 26 L6 W=20mil
GND2 26 FBMA-L11-201209-221LMA30T_0805 DMIC_CLK
33 GND3 27 27
34 +LEDVDD L7 2 W=20mil
28 28
1 B+
GND4 DMIC_DATA
35 29
GND5 29 FBMA-L11-201209-221LMA30T_0805
36 GND6 30 30 2 1 1 1
2

@
STARC_107K30-000001-G2 C170 C171 DA2 CA55 CA56
330P_0402_50V7K 100P_0402_50V8J PJDLC05C_SOT23-3
1 2 2 22P_0402_50V8J 2 22P_0402_50V8J
3G@ 3G@ 9/3 Pull-Down 10k(R377) to GND on BKOFF#
A BKOFF# R377 1 A
2 10K_0402_5%

change JLVDS1 to SP010011S00


1

2010/12/14 Tock R327 R328 R381 R382

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z LVDS / Camera / DMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP@ eDP@ eDP@ eDP@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
SE070104Z80
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 9 of 37
5 4 3 2 1
5 4 3 2 1

HDMI@ +5VS +5VS +5VS


R107 1 HDMI@ 2 0_0402_5% HDMI_CLK-_CONN Change RP13 to R107 , R112
<4> HDMI_CLKN
<4> HDMI_CLKP R112 1 2 0_0402_5% HDMI_CLK+_CONN Tock 2010/12/30 3 3 3

1 HDMIDAT_R 1 HDMICLK_R 1 HDMI_HPD


HDMI@
R141 1 HDMI@ 2 0_0402_5% HDMI_TX0-_CONN Change RP14 to R141 , R142 2 @ 2 @ 2 @
<4> HDMI_TX0N
<4> HDMI_TX0P R142 1 2 0_0402_5% HDMI_TX0+_CONN Tock 2010/12/30 D2 D3 D4
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

HDMI@
<4> HDMI_TX1N R143 1 HDMI@ 2 0_0402_5% HDMI_TX1-_CONN Change RP15 to R143 , R187 EMI/ESD
R187 1 2 0_0402_5% HDMI_TX1+_CONN Tock 2010/12/30
D <4> HDMI_TX1P D

+3VS
HDMI@ Change RP16 to R188 , R192
R188 1 HDMI@ 2 0_0402_5% HDMI_TX2-_CONN Tock 2010/12/30
<4> HDMI_TX2N
<4> HDMI_TX2P R192 1 2 0_0402_5% HDMI_TX2+_CONN

Swap HDMI Net of RP13~RP16 for layout


Tock 2010/12/24

2
G
@ L8 1 6 HDMICLK_R
HDMI_CLKP HDMI_CLK+_CONN <4> HDMI_CLK

D
1 2

S
1 2 HDMI_CLK+_CONN 1 2
R85 HDMI@ 499_0402_1%

5
Q9A

G
HDMI_CLKN 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN 1 2
4 3 R86 HDMI@ 499_0402_1% DMN66D0LDW-7_SOT363-6
WCM-2012-900T_4P HDMI_TX0+_CONN 1 2 HDMI@
R87 HDMI@ 499_0402_1% 4 3 HDMIDAT_R
@ L9 HDMI_TX0-_CONN <4> HDMI_DATA

D
S
1 2
HDMI_TX0P 1 2 HDMI_TX0+_CONN R88 HDMI@ 499_0402_1%
1 2 HDMI_TX1+_CONN 1 2
R89 HDMI@ 499_0402_1% Q9B
HDMI_TX0N 4 3 HDMI_TX0-_CONN HDMI_TX1-_CONN 1 2 DMN66D0LDW-7_SOT363-6
4 3 R90 HDMI@ 499_0402_1% HDMI@
WCM-2012-900T_4P HDMI_TX2+_CONN 1 2
R91 HDMI@ 499_0402_1%
@ L10 HDMI_TX2-_CONN 1 2
HDMI_TX1P 1 2 HDMI_TX1+_CONN R93 HDMI@ 499_0402_1%
1 2

1
C HDMI_TX1N HDMI_TX1-_CONN D C
4 4 3 3
+5VS 2 Q7 8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
WCM-2012-900T_4P G SSM3K7002FU_SC70-3

1
S

3
@ L11 @ HDMI@
HDMI_TX2P HDMI_TX2+_CONN R95
10/29 Add C409~C412(0.1U) on +5VS_HDMI 10/29 Add C415~C416(0.1U) on +5VS_HDMI_F
1 2
1 2 100K_0402_5%
NEAR CONNECT

2
HDMI_TX2N 4 3 HDMI_TX2-_CONN
4 3 0.1U_0402_16V4Z +5VS_HDMI +5VS_HDMI_F
2 1 C409 0.1U_0402_16V4Z 2 1 C415
WCM-2012-900T_4P
HDMI@ HDMI@
0.1U_0402_16V4Z 2 1 C410 0.1U_0402_16V4Z 2 1 C416
8/26 Change Q7 to SB000009610 Standard Part
HDMI@ HDMI@
0.1U_0402_16V4Z 2 1 C411

HDMI@
+5VS
W=60mil
0.1U_0402_16V4Z 2 1 C412

HDMI@ 9/20 Add F2 on HDMI

2
10/27 Change D5 P/N from SC1B491D000 to SCS00003H00
@ HDMI@
R96 D5
0_0805_5% RB491D_SC59-3

1
10/27 Change F2 P/N from SP04301P120 to SP040001B00 +5VS_HDMI

W=60mil 1 C172
9/20 Change R99 from HDMI@ to @ 0.1U_0402_16V4Z

2
HDMI@
B HDMI@ HDMI@ B
9/20 Change Q8,R100 from @ to HDMI@ 2
R97 R98
R99 2.2K_0402_5% 2.2K_0402_5%

2
1 2

1
F2 HDMI@
0_0402_5% 1.1A_6V_SMD1812P110TF
@

1
+3VS JHDMI1
10/28 Change JHDMI1 footprint from HDMI_HPD 19
+5VS_HDMI_F HP_DET
18
ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S 17
+5V
HDMIDAT_R DDC/CEC_GND
16 SDA
1

C R100 HDMICLK_R 15
HDMI@ Q8 HDMI_HPD SCL
2 1 2 14 Reserved
MMBT3904_NL_SOT23-3 B 150K_0402_5% 13
E HDMI@ HDMI_CLK-_CONN CEC
12 20
3

CK- GND
2

<4> HDMI_DET 11 21
@ @ HDMI_CLK+_CONN CK_shield GND
10 22
CK+ GND
1

R101 R102 HDMI_TX0-_CONN 9 23


200K_0402_5% 100K_0402_5% D0- GND
8
R103 HDMI_TX0+_CONN D0_shield
7
1

100K_0402_5% HDMI_TX1-_CONN D0+


6
HDMI@ D1-
5
2

HDMI_TX1+_CONN D1_shield
4
HDMI_TX2-_CONN D1+
10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P 3
D2-
2
to ACON_HMR2E-AK120D_19P-T HDMI_TX2+_CONN 1
D2_shield
D2+
11/16 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P) ACON_HMR2E-AK120D
CONN@
A A
8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T)
9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 10 of 37
5 4 3 2 1
A B C D E

Close to CRT CONN for ESD.

2
D6
D7
Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615 @ @

PJDLC05C_SOT23-3

PJDLC05C_SOT23-3
1
Change L12. L14, L15 to SM01000C600 2010/04/06 1

1
L12
CHENG-HANN MBK1005470YZF 0402
1 2 RED
<4> DAC_RED
L13
CHENG-HANN MBK1005470YZF 0402
1 2 GREEN
<4> DAC_GRN
L14
CHENG-HANN MBK1005470YZF 0402
1 2 BLUE
<4> DAC_BLU

150_0402_1%

150_0402_1%

150_0402_1%
1

1
1 1 1
R104 R105 R106 C176 1 1 1

10P_0402_50V8J
C177 C178

10P_0402_50V8J

10P_0402_50V8J
C173 C174 C175
2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J

2
2 2 2

+5VS

JVGA_HS
1 2
C179 0.1U_0402_16V4Z
JVGA_VS
U2
2 2
1 G Vcc 5

<4> CRT_HSYNC 2 IN A

3 4 CRT_HSYNC_R R375 1 2 39_0402_5%


GND OUT Y
Delete Q10 , R107
TC7SET125FUF_SC70-5 for CRT Hot Plug detect Circuit
2010/12/15 Tock
R325 1 @ 2 0_0402_5% 8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1
+5VS
9/3 Add R375 R376 for CRT
8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_SC70-5)
1 2
8/21 Reserve R325 R326 for CRT buffer cost down C180 0.1U_0402_16V4Z

U3
1 5
G Vcc

<4> CRT_VSYNC 2
IN A
CRT PORT 8/26 Change Q10 to SB000009610 Standard Part

CRT_VSYNC_R
8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)
3 4 R376 1 2 39_0402_5% +CRT_VCC
GND OUT Y

TC7SET125FUF_SC70-5 +5VS 0.1U_0402_16V4Z


3 3
C181
D8 W=40mils F1 11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT.11
2 1 1 2 +CRT_VCC_F 1 2
R326 1 @ 2 0_0402_5%
RB491D_SC59-3 1.1A_6VDC_FUSE JCRT1 remove CRT11, CRT4
6 Tock 2010/11/26
JCRT_11 11
+3VS T15PAD
RED 1
7
8/26 Update D8 P/N to SCS00003H00 VGA_DDC_DAT 12
+3VS +CRT_VCC_F GREEN 2
8/26 Update F1 P/N to SP040001B00 8 G 16
1

JVGA_HS 13 17
2.2K_0402_5% BLUE G
2.2K_0402_5% 10/4 Change from +CRT_VCC to +CRT_VCC_F 3
9
R109 R108 JVGA_VS 14
1

T26PAD JCRT_4 4
2

R110 R111 10
VGA_DDC_CLK 15
2.2K_0402_5% 2.2K_0402_5% JCRT_5 5
5

T27PAD
G

SUYIN_070546FR015M21TZR
CONN@
4 3 VGA_DDC_DAT
<4> CRT_DDC_DATA
D

Add JCRT_4 , JCRT_5 , JCRT_11


S

2011/01/28 Tock Delete R112 and net CRT_DET#


Q11B for CRT Hot Plug detect Circuit
2
G

DMN66D0LDW-7_SOT363-6
2010/12/15 Tock

1 6 VGA_DDC_CLK
4 <4> CRT_DDC_CLK 4
D
S

Q11A
DMN66D0LDW-7_SOT363-6

8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT PORT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 11 of 37
A B C D E
A B C D E

+3VALW
C182
9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST
2 1
9/20 C183.2 link to R119.2 Follow CRB 10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO! +3VS

5
0.1U_0402_16V4Z U4 Watchdog timer on NB_PWRGD

10K_0402_5%
2 @ enable for pull-up

P
B PLT_RST# 150P_0402_50V8J
Y 4 PLT_RST# <18,20,21,26> disable for pull-down

R113
A_RST# 1 2 1 C183 U5E
A

1
R384 1 @ 2 0_0402_5% P1 W2 PAD T16 20100527
2 PCIE_RST_L PCICLK0

PCI CLKS
R115 A_RST# R119 2 1 33_0402_5% R385 1 2 0_0402_5% L1 W1 PCI_CLK1 <16>

2
R114 100K_0402_5% A_RST_L PCICLK1/GPO36 PCI_CLK2
PCICLK2/GPO37 W3
8.2K_0402_5% NC7SZ08P5X_NL_SC70-5 C184 1 2 .1U_0402_16V7K UMI_RX0P_C AD26 W4
<5> UMI_RX0P UMI_TX0P PCICLK3/GPO38 PCI_CLK3 <16>

10K_0402_5%
C185 1 2 .1U_0402_16V7K UMI_RX0N_C AD27 Y1
@ <5> UMI_RX0N PCI_CLK4 <16>

2
C188 .1U_0402_16V7K UMI_RX1P_C UMI_TX0N PCICLK4/14M_OSC/GPO39
<5> UMI_RX1P 1 2 AC28
1

UMI_TX1P

R116
R120 1 @ 2 0_0402_5% C186 1 2 .1U_0402_16V7K UMI_RX1N_C AC29 V2
1 <5> UMI_RX1N UMI_RX2P_C UMI_TX1N PCIRST_L 1
C187 1 2 .1U_0402_16V7K AB29 PAD T17
<5> UMI_RX2P UMI_RX2N_C UMI_TX2P
C189 1 2 .1U_0402_16V7K AB28
<5> UMI_RX2N

2
C190 .1U_0402_16V7K UMI_RX3P_C UMI_TX2N
<5> UMI_RX3P 1 2 AB26 UMI_TX3P AD0/GPIO0 AA1
C191 1 2 .1U_0402_16V7K UMI_RX3N_C AB27 AA4
<5> UMI_RX3N UMI_TX3N AD1/GPIO1

PCI EXPRESS I/F


AD2/GPIO2
AA3 9/9 Change R117 R122 from mount to @ +5VALW
<5> UMI_TX0P AE24 AB1
9/2 Change R120 from 0603 to 0402 <5> UMI_TX0N AE23
UMI_RX0P AD3/GPIO3
AA5 9/15 PU PE_GPIO1 100k to +5VALW
UMI_RX0N AD4/GPIO4
<5> UMI_TX1P AD25 UMI_RX1P AD5/GPIO5 AB2
AD24 AB6 PE_GPIO1 R117 1 2 100K_0402_5%
<5> UMI_TX1N UMI_RX1N AD6/GPIO6
9/16 Change U4,C182 from @ to mount, <5> UMI_TX2P AC24
UMI_RX2P AD7/GPIO7
AB5
PE_GPIO0 R122 1
AC25 AA6 @ 2 100K_0402_5%
R120, R115 from mount to @ <5> UMI_TX2N UMI_RX2N AD8/GPIO8
<5> UMI_TX3P AB25 AC2
UMI_RX3P AD9/GPIO9
<5> UMI_TX3N AB24 UMI_RX3N AD10/GPIO10 AC3
AC4 PE_GPIO0, PE_GPIO1 are for DIS only
R121 590_0402_1% PCIE_CALRP AD11/GPIO11
9/27 Change R115 from @ to mount 2 1
PCIE_CALRN
AD29
PCIE_CALRP AD12/GPIO12
AC1 It's no function for UMA
+PCIE_VDDAN R118 2 1 2K_0402_1% AD28 AD1 P1VE6 follow P5WE6 Tock 2010/11/26
PCIE_CALRN AD13/GPIO13
AD14/GPIO14 AD2
AA28 AC6
GPP_TX0P AD15/GPIO15
AA29 GPP_TX0N AD16/GPIO16 AE2
C192 1 2 .1U_0402_16V7K PCIE_FTX_DRX_P1 Y29 AE1
<20> PCIE_FTX_C_DRX_P1 GPP_TX1P AD17/GPIO17
C193 .1U_0402_16V7K PCIE_FTX_DRX_N1 10/11 Change Y1 from SJ100006600 to SJ132P7KW10
WWAN FCH TX <20> PCIE_FTX_C_DRX_N1
C194
1
1
2
2 .1U_0402_16V7K PCIE_FTX_DRX_P2
Y28
Y26
GPP_TX1N AD18/GPIO18
AF8
AE3
<18> PCIE_FTX_C_DRX_P2 PCIE_FTX_DRX_N2 GPP_TX2P AD19/GPIO19
C195 .1U_0402_16V7K
LAN FCH TX <18> PCIE_FTX_C_DRX_N2
C379
1
1
2
2 .1U_0402_16V7K PCIE_FTX_DRX_P3
Y27
W28
GPP_TX2N AD20/GPIO20 AF1
AG1 PE_GPIO0 Close to FCH
<21> PCIE_FTX_C_DRX_P3 PCIE_FTX_DRX_N3 GPP_TX3P AD21/GPIO21
C380 .1U_0402_16V7K
WLAN FCH TX <21> PCIE_FTX_C_DRX_N3 1 2 W29
GPP_TX3N AD22/GPIO22
AF2
AE9
AD23/GPIO23 PCI_AD23 <16>
AA22 AD9 @ R123 20M_0402_5%
@R123
GPP_RX0P AD24/GPIO24 PCI_AD24 <16>

PCI I/F
Y21 AC11 PCI_AD25 <16> 1 2
GPP_RX0N AD25/GPIO25
<20> PCIE_FRX_DTX_P1 AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 <16>
WWAN FCH RX <20> PCIE_FRX_DTX_N1 AA24
W23
GPP_RX1N AD27/GPIO27 AF4
AF3
PCI_AD27 <16>
C196
<18> PCIE_FRX_DTX_P2 GPP_RX2P AD28/GPIO28 RTC_32KHO
V24 AH2 1 2
2 LAN FCH RX <18> PCIE_FRX_DTX_N2
W24
GPP_RX2N AD29/GPIO29
AG2 2
<21> PCIE_FRX_DTX_P3 GPP_RX3P AD30/GPIO30 22P_0402_50V8J Y1
WLAN FCH RX <21> PCIE_FRX_DTX_N3 W25
GPP_RX3N AD31/GPIO31
AH3

1
AA8 4 3
CBE0_L R124 OSC NC
9/6 Change PCI-E from FCH to APU CBE1_L AD5
AD8 20M_0603_5% 1 2
CBE2_L OSC NC
9/15 Change PCI-E from APU to FCH CBE3_L
AA10
AE8 32.768KHZ_12.5PF_Q13MC14610002

2
FRAME_L C197
AB9
DEVSEL_L RTC_32KHI
8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P) close to FCH within 1" M23 PCIE_RCLKP/NB_LNK_CLKP IRDY_L AJ3 1 2
P23 AE7
PCIE_RCLKN/NB_LNK_CLKN TRDY_L 22P_0402_50V8J
PAR AC5
R125 1 2 0_0402_5% DISP_CLK_R U29 AF5
<4> DISP_CLK NB_DISP_CLKP STOP_L
+RTCBATT1 R126 1 2 0_0402_5% DISP_CLK#_R U28 AE6
<4> DISP_CLK# NB_DISP_CLKN PERR_L
SERR_L
AE4 10/05 PD 10k(R405) on CLKRUN
T26 AE11
NB_HT_CLKP REQ0_L +1.8VS +3VS
T27 AH5
NB_HT_CLKN REQ1_L/GPIO40
1

CONN@ AH4
REQ2_L/CLK_REQ8_L/GPIO41

1
JBATT1 R127 1 2 0_0402_5% APU_CLK_R V21 AC12 PAD T18
+

<4> APU_CLK CPU_HT_CLKP REQ3_L/CLK_REQ5_L/GPIO42


R128 1 2 0_0402_5% APU_CLK#_R T21 AD12 R129
<4> APU_CLK# CPU_HT_CLKN GNT0_L
AJ5 10K_0402_5%
GNT1_L/GPO44 PE_GPIO1
V23 AH6 R405
SLT_GFX_CLKP GNT2_L/GPO45

2
G
8/21 Delete R130,R131(No VGA) T23 AB12 PAD T19

2
SLT_GFX_CLKN GNT3_L/CLK_REQ7_L/GPIO46
AB11 1 2
R132 1 CLK_PCIE_LAN_R CLKRUN_L APU_PWRGD
<18> CLK_PCIE_LAN 2 0_0402_5% L29 AD7 3 1 H_PWRGD_L <36>
R133 1 CLK_PCIE_LAN#_R GPP_CLK0P LOCK_L
2 0_0402_5%

D
L28
LAN <18> CLK_PCIE_LAN# GPP_CLK0N 10K_0402_5% 2

CLOCK GENERATOR
AJ6
R134 1 CLK_PCIE_WLAN_R INTE_L/GPIO32
<21> CLK_PCIE_WLAN 2 0_0402_5% N29 GPP_CLK1P INTF_L/GPIO33 AG6 FDV301N-NL_SOT23-3 C396
R135 1 2 0_0402_5% CLK_PCIE_WLAN#_R Q12
WLAN <21> CLK_PCIE_WLAN# N28
GPP_CLK1N INTG_L/GPIO34
AG4
1
100P_0402_50V8J
-

AJ4
LOTES_AAA-BAT-019-K01 R348 1 CLK_PCIE_WWAN_R M29 INTH_L/GPIO35
<20> CLK_PCIE_WWAN 2 0_0402_5%
2

R349 1 CLK_PCIE_WWAN#_R M28 GPP_CLK2P


2 0_0402_5%
WWAN <20> CLK_PCIE_WWAN# GPP_CLK2N R136 1 2 0_0402_5%
3 LPCCLK0 <16> 3
8/23 Add R348 R349 for WWAN PCIE T25 GPP_CLK3P
V25 H24 R137 1 2 22_0402_5% LPC_CLK0_EC <26>
C396 near to PR12
GPP_CLK3N LPCCLK0

LPC
H25 R138 1 2 0_0402_5% Michael 2010/11/18
LPCCLK1 CLK_PCI_DB <16>
9/6 Change D10 to SC600000B00 Standard Part L24 GPP_CLK4P LAD0 J27
LPC_AD0 <26>
L23 J26
GPP_CLK4N LAD1 LPC_AD1 <26>
9/13 Add NONCHARGE@ for D10 R244 LAD2
H29
LPC_AD2 <26> 10/04 Add 100p(C396) on H_PWRGD_L
P25 H28
GPP_CLK5P LAD3 LPC_AD3 <26>
12/07 Remove BOM structure NONCHARGE@ for D10 R244 Tock M25
GPP_CLK5N LFRAME_L
G28 LPC_FRAME# <26>
J25
LDRQ0_L LPC_CLK0_EC 1
P29 GPP_CLK6P LDRQ1_L/CLK_REQ6_L/GPIO49 AA18
P28 GPP_CLK6N SERIRQ/GPIO48 AB19
+RTCBATT +CHGRTC +RTCBATT1 SERIRQ <26> C359
D10
N26 GPP_CLK7P 10P_0402_50V8J
3 N27 2
GPP_CLK7N
1 9/1 Add R372 on CLK_48M_CR ALLOW_LDTSTP/DMA_ACTIVE_L G21 ALLOW_STOP# <4>

CPU
2 +RTCBATT1_R 1 2 T29 H21
GPP_CLK8P PROCHOT_L FCH_PROCHOT# <4>
R244 1K_0402_5% 9/7 Change R372 to 22 ohm T28 K19
GPP_CLK8N LDT_PG U5_G22 APU_PWRGD <4>
BAV70W_SOT323-3
LDT_STP_L
G22 T31 reserve C359 for RF
J24 PAD
R372 1 2 22_0402_5%CLK_48M_CR_R
LDT_RST_L LDT_RST# <4> Tock 2010/12/28
W=20mil <19> CLK_48M_CR L25
14M_25M_48M_OSC
C1 RTC_32KHI 10/07 Change R140 from 560 to 1k ohm
32K_X1
2

RTC
R388 1 2 25M_CLK_X1 L26 C2 RTC_32KHO 11/01 Add Net U5_G22 on U5.G22
22_0402_5% 25M_X1 32K_X2
1

3G@ C198 D2
RTCCLK SUSCLK <26>
22P_0402_50V8J 1M_0603_5% B2 +RTCBATT
1

Y2 R139 25M_CLK_X2 INTRUDER_ALERT_L +RTCBATT_R


L27
25M_X2 VDDBT_RTC_G
B1 1 2 W=20mil
1 C199 R140 1K_0402_5%
2

1U_0402_6.3V6K
22P_0402_50V8J S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA 1

1
C361 1 2
10P_0402_50V8J 25MHZ_20PF_7A25000012 SA000046HA0 C200 CLRP1 @
4 3G@ 2 SHORT PADS 4

2
2
9/13 Add Net Name +RTCBATT1_RR 8/25 Change FCH(U5) PN to SA000046H30
9/13 Change Net Name +RTCBATT1 to +RTCBATT2 11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)
reserve R388 , C361 for RF For Clear CMOS, near to RAM door
9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit Tock 2010/12/29
10/07 Change R392 from 1k to 0 ohm
change R388,C361 BS from @ to 3G@ for RF solution Security Classification Compal Secret Data Compal Electronics, Inc.
10/08 Change R392 from 0 ohm to 1k ohm Tock 2011/03/16 Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

11/01 Change R392 from 1k to 0 ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
12/07 Remove R392 , C392 , D23 Tock Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 12 of 37
A B C D E
A B C D E

+3VALW Change to RP3 to R150 , R153 , R154 , R161 Change R145, R147, R151, R152 to RP4
Tock 2010/12/30 Michael 2010/12/23
1 2 USB_OC0# Change RP4 to R145, R147, R151, R152 for layout
R150 1 2 10K_0402_5% USB_OC3# +3VALW Tock 2010/12/27 U5A
R153 1 2 10K_0402_5% USB_OC2#

USB MISC
R154 1 2 10K_0402_5% FCH_PCIE_WAKE# 1 2 FCH_SIC
R161 10K_0402_5% R145 1 2 10K_0402_5% FCH_SID <26> PCI_PME# J2 PCI_PME_L/GEVENT4_L USBCLK/14M_25M_48M_OSC A10

ACPI/WAKE UP EVENTS
R147 1 2 10K_0402_5% USB_OC5# K1 RI_L/GEVENT22_L
R146
R151 1 2 10K_0402_5% USB_OC4# D3 G19 USB_RCOMP 1 2
@ EC_LID_OUT# R152 10K_0402_5% SPI_CS3_L/GBE_STAT1/GEVENT21_L USB_RCOMP 11.8K_0402_1%
1 2 <26> SLP_S3# F1 SLP_S3_L
R144 10K_0402_5% H1
<26> SLP_S5# SLP_S5_L
<26> PBTN_OUT# F2 PWR_BTN_L
10mils and <1"
Swap net of RP3 & RP5 for layout Reserve C418 for KB_RST#, C426 FCH_PWRGD H5
PWR_GOOD

USB 1.1
Tock 2010/12/27 for PBTN_OUT Michael 2010/11/18 G6 SUS_STAT_L USB_FSD1P/GPIO186 J10
1 1
T20PAD B3 TEST0 USB_FSD1N H11
+3VS KB_RST# PBTN_OUT# C4
T21PAD TEST1/TMS
1 1 T22PAD F6 TEST2 USB_FSD0P/GPIO185 H9
1 2 WWAN_CLKREQ# AD21 J8
<26> GATEA20 GA20IN/GEVENT0_L USB_FSD0N
R359 10K_0402_5% C418 C426 AE21
<26> KB_RST# KBRST_L/GEVENT1_L
1 2 LAN_CLKREQ# 100P_0402_50V8J 100P_0402_50V8J K2 B12
2 2 <26> EC_SCI# LPC_PME_L/GEVENT3_L USB_HSD13P
R155 10K_0402_5% @ @ J29 A12
WLAN_CLKREQ# <26> EC_SMI# LPC_SMI_L/GEVENT23_L USB_HSD13N
1 2 H2 GEVENT5_L
R156 10K_0402_5% +3VALW R148 1 @ 2 10K_0402_5% J1 F11 9/15 Update USB Port List
NB_PWRGD SYS_RESET_L/GEVENT19_L USB_HSD12P
1 2 <18,20,21> FCH_PCIE_WAKE# H6 E11
R157 4.7K_0402_5% Reserve C417 for EC_RSMRST# WAKE_L/GEVENT8_L USB_HSD12N
FCH_SMCLK0
F3 IR_RX1/GEVENT20_L 9/1 Update USB Port List
1 2 Michael 2010/11/18 <4> H_THERMTRIP# J6 E14
R149 2.2K_0402_5% NB_PWRGD THRMTRIP_L/SMBALERT_L/GEVENT2_L USB_HSD11P
FCH_SMDAT0 EC_RSMRST#
AC19 NB_PWRGD USB_HSD11N E12 8/23 USB port8 link to SIM
1 2
R158 2.2K_0402_5% 1 G1 J12
<26> EC_RSMRST# RSMRST_L USB_HSD10P
8/31 Pull up 10k(R359) to +3VS on WWAN_CLKREQ# USB_HSD10N
J14
C417 AD19
Reserve C431 for H_THERMTRIP# Michael 2010/11/18 CLK_REQ4_L/SATA_IS0_L/GPIO64
100P_0402_50V8J AA16 A13
2 CLK_REQ3_L/SATA_IS1_L/GPIO63 USB_HSD9P USB20_P9 <20>
@ AB21 SMARTVOLT1/SATA_IS2_L/GPIO50 USB_HSD9N B13
USB20_N9 <20> WWAN
R159 2 @ 1 0_0402_5% AC18
<18> LAN_CLKREQ# CLK_REQ0_L/SATA_IS3_L/GPIO60
H_THERMTRIP# AF20 D13
R160 2 SATA_IS4_L/FANOUT3/GPIO55 USB_HSD8P USB20_P8 <21>
1 1 0_0402_5% 8/31 Delete Net : SATA_DET# AE19 C13 WiMax
SATA_IS5_L/FANIN3/GPIO59 USB_HSD8N USB20_N8 <21>
<17> FCH_SPKR AF19 SPKR_GPIO66

GPIO

USB 2.0
C431 AD22 G12
+3VS @ <7,8,20,21> FCH_SMCLK0 SCL0_GPIO43 USB_HSD7P USB20_P7 <20>
2
100P_0402_50V8J <7,8,20,21> FCH_SMDAT0 FCH_SMCLK1
AE22
SDA0_GPIO47 USB_HSD7N
G14
USB20_N7 <20> Bluetooth
C201 .1U_0402_16V7K F5
FCH_SMDAT1 SCL1_GPIO227
1 2 F4 G16
SDA1_GPIO228 USB_HSD6P USB20_P6 <19>
<20> WWAN_CLKREQ# AH21
CLK_REQ2_L/FANIN4_GPIO62 USB_HSD6N
G18
USB20_N6 <19> Card Reader
5

<21> WLAN_CLKREQ# AB18 CLK_REQ1_L/FANOUT4_GPIO61


2 E1 D16
P

B ICH_POK <26> IR_LED_L/LLB_L/GPIO184 USB_HSD5P USB20_P5 <9>


<36> FCH_PWRGD 4
Y
AJ21
SMARTVOLT2/SHUTDOWN_L/GPIO51 USB_HSD5N
C16
USB20_N5 <9> Camera
1 VGATE <26,36> H4
A DDR3_RST_L/GEVENT7_L
G

2 2
2 2 D5 GBE_LED0/GPIO183 USB_HSD4P B14
@ NC7SZ08P5X_NL_SC70-5 Reserve C422 for ICH_POK USB20_P4 <20>
D7 A14 SIM
3

C397 GBE_LED1/GEVENT9_L USB_HSD4N USB20_N4 <20>


U6 @ 1 Michael 2010/11/18 8/22 Delete Net : R161 R162 G5
GBE_LED2/GEVENT10_L
100P_0402_50V8J C202 K3 E18
1 1 .1U_0402_16V7K C422 GBE_STAT0/GEVENT11_L USB_HSD3P USB20_P3 <20>
AA20 CLK_REQG_L/GPIO65_OSCIN USB_HSD3N E16
USB20_N3 <20> WWAN
100P_0402_50V8J
2
@ USB_HSD2P J16
+3VALW USB_OC7# USB20_P2 <25>
H3
BLINK/USB_OC7_L/GEVENT18_L USB_HSD2N
J18
USB20_N2 <25> USB Conn.(RS) JUSB1

USB OC
<26> EC_LID_OUT# D1 USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC1# USB_OC5# E4 B17
R162 USB_OC7# USB_OC4# USB_OC5_L/IR_TX0/GEVENT17_L USB_HSD1P USB20_P1 <24>
1 2 1 D4 USB_OC4_L/IR_RX0/GEVENT16_L USB_HSD1N A17
USB20_N1 <24> USB Conn.(LS) IO
R186 1 2 10K_0402_5% USB_OC1# USB_OC3# E8
R164 10K_0402_5% FCH_SMCLK1 C474 USB_OC2# USB_OC3_L/AC_PRES/TDO/GEVENT15_L
1 2 F7 USB_OC2_L/TCK/GEVENT14_L USB_HSD0P A16
R163 10K_0402_5% FCH_SMDAT1 USB20_P0 <24>
1 2
2
100P_0402_50V8J <25> USB_OC1# E7
USB_OC1_L/TDI/GEVENT13_L USB_HSD0N
B16
USB20_N0 <24> USB Conn.(LS) IO
10K_0402_5% F8
<24> USB_OC0# USB_OC0_L/TRST_L/GEVENT12_L
change RP5 to R162 , R163 , R164 , R186 Reserve C474 for USB_OC1#
Tock 2010/12/30 Tock 2011/01/07

HD AUDIO
1 2 EC_RSMRST# R166 1 2 33_0402_5% HDA_BITCLK M3 D25 GPIO193 R167 2 1 10K_0402_5%
<17> HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK SCL2/GPIO193 GPIO194
R165 2.2K_0402_5% R168 1 2 33_0402_5% N1 F23 R169 2 1 10K_0402_5%
HDA_BITCLK <17> HDA_SDOUT_AUDIO HDA_SDIN0 AZ_SDOUT SDA2/GPIO194
1 @ 2 L2 B26
<17> HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 FCH_SIC <4>
R170 10K_0402_5% M2 E26
@ HDA_SDIN0 Reserve C358 for RF AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 FCH_SID <4>
1 2 M1 F25
R171 10K_0402_5% AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
Tock 2010/12/28 M4
AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
E22
1 2 HDA_SDOUT R173 1 2 33_0402_5% HDA_SYNC N2 F22 EC_PWM2
<17> HDA_SYNC_AUDIO AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
R172 10K_0402_5%
<17> HDA_RST_AUDIO#
R174 1 2 33_0402_5% HDA_RST# P2 E21 EC_PWM3 Internal Pull-Up available
HDA_BITCLK_AUDIO AZ_RST_L EC_PWM3/EC_TIMER3/GPIO200
1 2
C358 10P_0402_50V8J G24
N3G@ R175 1 KSI_0/GPIO201
2 10K_0402_5% T1 G25
C358 3G@ EC_SCI# R176 1 GBE_COL KSI_1/GPIO202 +3VALW
2 10K_0402_5% T4 E28
GBE_CRS KSI_2/GPIO203

EMBEDDED CTRL
1 L6 E29
co-lay 22P on C358 for 3G @ R177 GBE_MDCK KSI_3/GPIO204
+3VALW 1 2 10K_0402_5% L5 D29
3 C440 GBE_MDIO KSI_4/GPIO205 3
for RF solution T9 GBE_RXCLK KSI_5/GPIO206 D28

2
10K_0402_5%

10K_0402_5%
GBE LAN
Tock 2011/03/16 100P_0402_50V8J U1 GBE_RXD3 KSI_6/GPIO207 C29
2 U3 C28
@ GBE_RXD2 KSI_7/GPIO208

R178

R179
22P_0402_50V8J T2 GBE_RXD1
Pull-down for enable U2
GBE_RXD0 KSO_0/GPIO209
B28
high performance mode T5 A27 @

1
GATEA20 EC_SMI# R180 GBE_RXCTL/RXDV KSO_1/GPIO210
20100527 (required for M1) 1 2 10K_0402_5% V5 B27 8/31 Change R182 from mount to @
GBE_RXERR KSO_2/GPIO211
1 1 P5 D26
GBE_TXCLK KSO_3/GPIO212 Change R183 from @ to mount EC_PWM3
M5 A26
C427 C441 GBE_TXD3 KSO_4/GPIO213 EC_PWM2
P9 GBE_TXD2 KSO_5/GPIO214 C26
+3VALW +3VALW +3VALW +3VALW 2
100P_0402_50V8J
2
100P_0402_50V8J T7 GBE_TXD1 KSO_6/GPIO215 A24 9/15 Change R178 from @ to mount
@ @ P7 B25
GBE_TXD0 KSO_7/GPIO216

2.2K_0402_5%

2.2K_0402_5%
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25

1
P4 D24
GBE_PHY_PD KSO_9/GPIO218

R182

R183
M9 GBE_PHY_RST_L KSO_10/GPIO219 B24
PCI_PME# FCH_PCIE_WAKE# R181 1 2 10K_0402_5% V7 C24
GBE_PHY_INTR KSO_11/GPIO220
1

@ P0@ @ @ 1 1 B23
R414 R406 R409 R411 GPIO187 E23 KSO_12/GPIO221 @
T23 PAD A23

2
C445 C442 GPIO188 E24 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
T24 PAD D22
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
100P_0402_50V8J 100P_0402_50V8J F21 C22
2 2 SPI_CS2_L/GBE_STAT2/GPIO166 KSO_15/GPIO224
@ G29 A22
2

FC_RST_L/GPO160 KSO_16/GPIO225
KSO_17/GPIO226 B22
GPIO189 GPIO189 D27
GPIO190 GPIO190 PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190
GPIO191 GPIO191 F29
PS2M_DAT/GPIO191
EC_PWM3 EC_PWM2 ROM TYPE
GPIO192 Reserve C427 , C440, C441, C442, C445 GPIO192 E27
PS2M_CLK/GPIO192
for SCI, SMI, PCIE_WAKE#, GATE20, PCI_PME#
Michael 2010/11/18 S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA NC L SPI ROM
1

P1@
R413 R407 R408 R410
NC NC Reserved
1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 10/27 Change R408 R410 from @ to mount
4 4
2

10/28 Add R413 R414 on GPIO192 for project ID L L Reserved

Board ID
L H LPC ROM *
R406 R407
change R407,R408,R410,R413 from 10K to 1K
mount @ P1VE6 Security Classification Compal Secret Data Compal Electronics, Inc.
11/26 Tock Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

change R406 BOM to P0@ , R407 BOM to P1@ @ P1VS6 FCH HDA/USB/ACPI
2011/01/04 Tock
mount THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 13 of 37
A B C D E
A B C D E

1 1

U5B
C203 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AH9 AH28
<22> SATA_ITX_DRX_P0 SATA_ITX_C_DRX_N0 AJ9 SATA_TX0P FC_CLK
C204 1 2 0.01U_0402_16V7K AG28
<22> SATA_ITX_DRX_N0 SATA_TX0N FC_FBCLKOUT
HDD FC_FBCLKIN AF26 11/01 Add Net U5_AE29 on U5.AE29
<22> SATA_DTX_C_IRX_N0 AJ8
SATA_RX0N
<22> SATA_DTX_C_IRX_P0 AH8
SATA_RX0P FC_OE_L/GPIOD145
AF28 2011/0103 delete Net U5_AE29 on U5.AE29
AG29
FC_AVD_L/GPIOD146
AH10 SATA_TX1P FC_WE_L/GPIOD148 AG26 T28 2011/01/28 Add Net U5_AE29 on U5.AE29 for Layout test point
AJ10 SATA_TX1N FC_CE1_L/GPIOD149 AF27
AE29 U5_AE29
FC_CE2_L/GPIOD150
AG10 SATA_RX1N FC_INT1/GPIOD144 AF29
AF10 AH27
SATA_RX1P FC_INT2/GPIOD147 PAD

GPIOD
8/21 Delete C205~C208 (No ODD ESATA function) AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
AH25 +3VS
FC_ADQ2/GPIOD130
AJ12 AH24
SATA_RX2N FC_ADQ3/GPIOD131

SERIAL ATA
2 2
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
AH23
FC_ADQ5/GPIOD133

1
AH14 AJ22
SATA_TX3P FC_ADQ6/GPIOD134 R415
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
AF21 @ 10K_0402_5%
FC_ADQ8/GPIOD136
AG14 AH22
SATA_RX3N FC_ADQ9/GPIOD137
AF14 AJ23

2
SATA_RX3P FC_ADQ10/GPIOD138 GPIO56
AF23
FC_ADQ11/GPIOD139
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 AJ25
SATA_TX4N FC_ADQ13/GPIOD141

1
FC_ADQ14/GPIOD142 AG25
AJ17 AH26 R416
SATA_RX4N FC_ADQ15/GPIOD143 @
AH17 SATA_RX4P 10K_0402_5%
8/21 Delete Net : ODD_EN
9/7 Change SATA_CALRN from +1.1VS to +AVDD_SATA AJ18

2
SATA_TX5P 8/22 Delete Net : BT_OFF#, WL_OFF#

HW MONITOR
AH18 W5
SATA_TX5N FANOUT0/GPIO52
W6
FANOUT1/GPIO53
AH19 Y9
SATA_RX5N FANOUT2/GPIO54
AJ19
SATA_RX5P GPIO56
10/29 Add R415(@), R416(@) on GPIO56
10 mils and < 1" FANIN0/GPIO56 W7
V9
R184 SATA_CALRP FANIN1/GPIO57
1 2 1K_0402_1% AB14 W8
R185 SATA_CALRN SATA_CALRP FANIN2/GPIO58
+AVDD_SATA 1 2 931_0402_1% AA14 9/9 Change R189 from mount to @
SATA_CALRN TEMPIN0
B6
TEMPIN0/GPIO171 TEMPIN1
TEMPIN1/GPIO172
A6
TEMPIN2
9/15 Change R189 from @ to mount
<22> HDD_LED# AD11 A5
SATA_ACT_L/GPIO67 TEMPIN2/GPIO173 R189 2
TEMPIN3/TALERT_L/GPIO174 B5 1 10K_0402_5%
+3VS R190 1 2 10K_0402_5% C7
TEMP_COMM APU_ALERT#_FCH <4>
A3 GPIO175 R191 2 1 10K_0402_5%
25M_SATA_X1 AD16 VIN0/GPIO175 GPIO176
1 2 B4
SATA_X1 VIN1/GPIO176 GPIO177
A4
VIN2/GPIO177
1

3 GPIO178 3
@ C209 @ VIN3/GPIO178 C5 R194 2 1 10K_0402_5%
22P_0402_50V8J 1M_0603_5% A7 GPIO179 VIN6/GBE_STAT3/GPIO181
Y3 R195 VIN4/GPIO179 GPIO180
B7 Enable integrated pull-down/up and leave unconnected
VIN5/GPIO180 GPIO181
@ C210 @ B8 R198 2 @ 1 10K_0402_5%
2

22P_0402_50V8J 25M_SATA_X2 AC16 VIN6/GBE_STAT3/GPIO181 GPIO182


A8
SATA_X2 VIN7/GBE_LED3/GPIO182
1 2
25MHZ_20PF_7A25000012
SPI ROM

J5 G27 @
SPI_DI/GPIO164 NC1 GPIO177 R196 10K_0402_5% C406 1 APU_ALERT#_FCH
E2 SPI_DO/GPIO163 NC2 Y2 2 1 2 100P_0402_50V8J
K4 TEMPIN2 R197 2 1 10K_0402_5%
SPI_CLK/GPIO162 TEMPIN0 R199 10K_0402_5%
GPIO161
K9 SPI_CS1_L/GPIO165 GPIO180 R236
2 1
10K_0402_5%
10/05 Add 100p(C406) on APU_ALERT#_FCH
T25 PAD G2 2 1
ROM_RST_L/GPIO161 Change R193, R188, R197, R198 to RP7
S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA Michael 2010/12/23
Change RP7 to R196 , R197 , R199 , R236
Tock 2010/12/30

8/31 remove FCH SPI ROM GPIO182 R237 2 1 10K_0402_5%


GPIO179 R239 2 1 10K_0402_5%
TEMPIN1 R240 2 1 10K_0402_5% Change R199, R196, R187, R192 to RP8
GPIO176 R245 2 1 10K_0402_5% Michael 2010/12/23
Change RP8 to R237 , R239 , R240 , R245
Tock 2010/12/30

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-SATA/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 14 of 37
A B C D E
A B C D E

+3VS
42mA POWER 790mA +1.1VS
R346 U5C

10U_0603_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 2 +VDDIO_33 AH1 N13
VDDIO_33_PCIGP_1 VDDCR_11_1 +1.1VS

CORE S0
22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
0_0603_5% 1 2 2 2 V6 R15 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2

PCI/GPIO I/O
C213

C214

C215

C216

C217

C218

C219

C220

C221
Y19 VDDIO_33_PCIGP_3 VDDCR_11_3 N17
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13
AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17
2 1 1 1 AA2 V12 2 2 2 2 2
VDDIO_33_PCIGP_6 VDDCR_11_6

10U_0603_6.3V6M
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 1
AC8 W12 1
VDDIO_33_PCIGP_8 VDDCR_11_8

C223
AA7 W18 + C222
VDDIO_33_PCIGP_9 VDDCR_11_9 330U_2.5V_M
AA9
VDDIO_33_PCIGP_10 382mA
GPIO I/F implemented: tied to +1.8V_S0 AF7 VDDIO_33_PCIGP_11 2 2

CLKGEN I/O
1 GPIO I/F not implemented: tied to +VDDAN_11_CLK L15 2 1
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 1 +1.1VS
+1.8VS

22U_0805_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
R207 +1.8V_S0 or 0 ohm to ground K29 1 1 1 1 1
VDDAN_11_CLK_2

C224

C225

C226

C227

C228
1 2 +VDDIO_18_FC J28 FBMA-L11-201209-221LMA30T_0805 SF000002Z00
0_0603_5% VDDAN_11_CLK_3
K26
VDDAN_11_CLK_4
1

0_0402_5%

FLASH I/O
.1U_0402_16V7K

.1U_0402_16V7K
4.7U_0603_6.3V6K
2 2 2 0.15mA VDDAN_11_CLK_5
J21
2 2 2 2 2
R208

C229

C230

C231
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20
AE25
VDDIO_18_FC_2 VDDAN_11_CLK_7
K21 8/25 Change C222 from poly-cap to E-cap (SF000002Z00)
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22
@ 1 1 1 AC22
2

VDDIO_18_FC_4

VDDRF_GBE_S V1

22mA VDDIO_33_GBE_S M10

2.2U_0603_6.3V6K
L16

PCI EXPRESS
2 1 +VDDPL33_PCIE AE28
+3VS VDDPL_33_PCIE
FBMA-L11-160808-221LMT_2P 1

GBE LAN
C232
U26 L7
VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1
2 1115mA V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9
+1.1VS +PCIE_VDDAN
V26
VDDAN_11_PCIE_3 8/23 Add R346 R347, +VDDIO_33, +VDDIO_33_S
L17 V27
VDDAN_11_PCIE_4
22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K
2 1 V28 M6
VDDAN_11_PCIE_5 VDDIO_GBE_S_1
1U_0402_6.3V6K

FBMA-L11-201209-221LMA30T_0805 V29 P8
VDDAN_11_PCIE_6 VDDIO_GBE_S_2
1 1 2 2 W22 VDDAN_11_PCIE_7
C233

C234

C235

C236 W26
VDDAN_11_PCIE_8

2 2 1 1 15mA

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
49mA

SERIAL ATA

3.3V_S5 I/O
+VDDPL_33_SATA AD14 R347
VDDPL_33_SATA +VDDIO_33_S
VDDIO_33_S_1 A21 1 2 +3VALW
+AVDD_SATA AJ20 D21 1 1 0_0603_5%
VDDAN_11_SATA_1 VDDIO_33_S_2

C237

C238
AF18 B21
2 VDDAN_11_SATA_4 VDDIO_33_S_3 2
1354mA AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10
AG19 L10
VDDAN_11_SATA_3 VDDIO_33_S_5 2 2
AE18 J9
VDDAN_11_SATA_5 VDDIO_33_S_6
AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6
AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 165mA

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.1VALW
534mA 1 1

CORE S5

C239

C240
L18 F26
+AVDD_USB VDDCR_11_S_1
+3VALW 2 1 A18
VDDAN_33_USB_S_1 VDDCR_11_S_2
G26 15mA
A19 VDDAN_33_USB_S_2 2 2
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805 A20 M8 +VDDIO_AZ


VDDAN_33_USB_S_3 VDDIO_AZ_S
1 1 1 1 1 B18 VDDAN_33_USB_S_4 58mA

USB I/O

10U_0603_6.3V6M
C241

C242

C243

C244

C245

.1U_0402_16V7K

.1U_0402_16V7K
B19 A11 L19
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 +VDDCR_11_USB
B20 B11 1 2 +1.1VALW
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2
C18 1 1 1
2 2 2 2 2 VDDAN_33_USB_S_7

C246

C247

C248
C20 0_0805_5%
VDDAN_33_USB_S_8
D18
VDDAN_33_USB_S_9 VDDPL_33_SYS
M21 +VDDPL33 46mA
D19
VDDAN_33_USB_S_10 2 2 2

PLL
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 +VDDPL11 65mA
E19
VDDAN_33_USB_S_12
88mA VDDPL_33_USB_S
F19 +AVDD_USB 16mA
L20
.1U_0402_16V7K
2.2U_0603_6.3V6K

+1.1VALW 2 1 +VDDAN_11_USB C11 D6 +VDDAN33_HWM 12mA


VDDAN_11_USB_S_1 VDDAN_33_HWM_S L21
D11
FBMA-L11-160808-221LMT_2P VDDAN_11_USB_S_2 +VDDXL_33_S
1 2 L20 2 1 +3VS
VDDXL_33_S
C249

C250

2.2U_0603_6.3V6K
1

C251
S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA 5mA FBMA-L11-160808-221LMT_2P
2 1
2

3 3

For 3V AZ device
+AVDD_SATA +VDDIO_AZ +3VALW
+VDDPL_33_SATA L22
+3VS
22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

L23 +1.1VS 2 1 @
1U_0402_6.3V6K

1U_0402_6.3V6K

+3VS 2 1 FBMA-L11-201209-221LMA30T_0805 1 2
FBMA-L11-160808-221LMT_2P 1 1 1 1 1 R209 0_0603_5%
C253

C254

C255

C256

C257

1 2
1 R210 0_0603_5%
C252 1 2 2.2U_0603_6.3V6K
2 2 2 2 2 C258
2.2U_0603_6.3V6K
2 change +1.5V to +3VS and mount R210 reserve R209
+VDDPL11 +VDDAN33_HWM 11/26 Tock
L24 L25
+1.1VALW 2 1 +3VALW 2 1
FBMA-L11-160808-221LMT_2P FBMA-L11-160808-221LMT_2P Wake On Ring Not Implemented:
.1U_0402_16V7K
2.2U_0603_6.3V6K

HWM@ Tied to a +1.5V_S0 or +3.3V_S0 rail.


C259 1 2 2.2U_0603_6.3V6K
VDDIO_AZ_S and audio CODEC chip HD link IO power rail
1 2
4 should be at same voltage level/domain.
HWM@ C260

C261

9/3 Change L26 to L25(NONHWM@)


L25
2 1

+VDDPL33
L27
+3VS 2 1
FBMA-L11-160808-221LMT_2P 0_0603_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
C262 1 2 2.2U_0603_6.3V6K SD013000080
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PWR
NONHWM@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 15 of 37
A B C D E
5 4 3 2 1

U5D
Y14
Y16
VSSIO_SATA_1
VSSIO_SATA_2
VSS_1
VSS_2
AJ2
A28
REQUIRED STRAPS Check Internal PU/PD
AB16 VSSIO_SATA_3 VSS_3 A2
AC14 VSSIO_SATA_4 VSS_4 E5
AE12 VSSIO_SATA_5 VSS_5 D23 PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 CLK_PCI_DB
AE14 VSSIO_SATA_6 VSS_6 E25
AF9 VSSIO_SATA_7 VSS_7 E6
AF11 VSSIO_SATA_8 VSS_8 F24 PULL ALLOW PCIE USE Reserved internal EC Internal
AF13 N15 GEN2 DEBUG ENABLE CLKGEN
D
AF16
VSSIO_SATA_9 VSS_9
R13
HIGH D
VSSIO_SATA_10 VSS_10 STRAP Mode
AG8 VSSIO_SATA_11 VSS_11 R17
AH7
AH11
VSSIO_SATA_12
VSSIO_SATA_13
VSS_12
VSS_13
T10
P10 * *
AH13 VSSIO_SATA_14 VSS_14 V11 IGNORE
AH16 VSSIO_SATA_15 VSS_15 U15 PULL FORCE PCIE DEBUG CLKGEN Mode internal EC External
AJ7 M18 GEN1 DISABLE CLKGEN
VSSIO_SATA_16 VSS_16 LOW STRAP
AJ11 VSSIO_SATA_17 VSS_17 V19 Internal Mode
AJ13 VSSIO_SATA_18 VSS_18 M11
AJ16 VSSIO_SATA_19
GND VSS_19
VSS_20
L12
L18 * * *
A9 VSSIO_USB_1 VSS_21 J7
B10 VSSIO_USB_2 VSS_22 P3
K11 VSSIO_USB_3 VSS_23 V4
B9 VSSIO_USB_4 VSS_24 AD6
D10 AD4 +3VS +3VS +3VS +3VALW +3VALW
VSSIO_USB_5 VSS_25
D12 VSSIO_USB_6 VSS_26 AB7
D14 VSSIO_USB_7 VSS_27 AC9
D17 VSSIO_USB_8 VSS_28 V8

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
E9 VSSIO_USB_9 VSS_29 W9
F9 VSSIO_USB_10 VSS_30 W10

R211

R212

R213

R214

R215
F12 VSSIO_USB_11 VSS_31 AJ28
F14 VSSIO_USB_12 VSS_32 B29
F16 U4 @ @ @

2
C VSSIO_USB_13 VSS_33 C
C9 VSSIO_USB_14 VSS_34 Y18 9/13 Change R211 from mount to @, R216 from @ to mount
G11 VSSIO_USB_15 VSS_35 Y10
F18 VSSIO_USB_16 VSS_36 Y12 9/13 Change R211 from @ to mount, R216 from mount to @
D9 VSSIO_USB_17 VSS_37 Y11
H12 VSSIO_USB_18 VSS_38 AA11 <12> PCI_CLK1
H14 VSSIO_USB_19 VSS_39 AA12 <12> PCI_CLK3
H16 VSSIO_USB_20 VSS_40 G4 <12> PCI_CLK4
H18 VSSIO_USB_21 VSS_41 J4 <12> LPCCLK0
J11 VSSIO_USB_22 VSS_42 G8 <12> CLK_PCI_DB
J19 VSSIO_USB_23 VSS_43 G9
K12 VSSIO_USB_24 VSS_44 M12
K14 VSSIO_USB_25 VSS_45 AF25
K16 VSSIO_USB_26 VSS_46 H7
K18 VSSIO_USB_27 VSS_47 AH29
H19 VSSIO_USB_28 VSS_48 V10

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
VSS_49 P6
VSS_50 N4

R216

R217

R218

R219

R220
Y4 EFUSE VSS_51 L4
VSS_52 L8
D8 @ @

2
VSSAN_HWM
M19 VSSXL VSSPL_SYS M20

B B
P21 H23
P20
M22
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
H26
AA21
DEBUG STRAPS
M24
M26
VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 AA23
AB23
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
VSSIO_PCIECLK_5 VSSIO_PCIECLK_18
P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23 PCI_AD23
P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 Enable ROM Straps
P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20 USE internal <12> PCI_AD27
T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W21 PLL generated ILA AUTORUN Selects Disable I2C Required Setting <12> PCI_AD26
T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20 PULL Disabled FC PLL ROM <12> PCI_AD25
V20 AE26 PLL CLK
J23
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
L21
HIGH <12> PCI_AD24
VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 <12> PCI_AD23
VSSIO_PCIECLK_27 K20
* * * * *

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

R221

R222

R223

R224

R225
PULL BYPASS ILA FC PLL Getting Value
LOW PCI PLL AUTORUN bypassed from I2C EPROM Reserved
Enabled

2
@ @ @ @ @

A Check AD29,AD28 strap function check default A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-VSS/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 16 of 37
5 4 3 2 1
5 4 3 2 1

08/19 Follow NTUC0 11/04 Change RA19 RA20 from 47k to 10k
@ DA22
2 1
Int. Speaker Conn. JSPK2
SPKL+ RA22 1 2 0_0603_5% SPK_L+ 1
RB751V-40_SOD323-2 SPKL- RA25 0_0603_5% SPK_L- 1
CA33 1 2 2
SPKR+ RA23 0_0603_5% SPK_R+ 2
1 2 3 3 G1 5
1 2 1 2 1 2 MONO_IN SPKR- RA24 1 2 0_0603_5% SPK_R- 4 6
+3VS +3VS_AUDIO <26> BEEP# 4 G2
RA340 0_0805_5% RA19 33_0402_5% 20mil

3
0.1U_0402_16V4Z ACES_88266-04001
1 2 CONN@
Remove RA55,RA56 and add RA340 for power consumption <13> FCH_SPKR RA20 10K_0402_5% 2

1
11/26 Tock @ DA21 1
@ CA34
2 1 RA21 CA32 100P_0402_50V8J
change RA19 from 10K to 33 ohm 10K_0402_5% @ 1 DA5 DA4
0.1U_0402_16V4Z
D RB751V-40_SOD323-2 2 PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 D
Tock 2011/02/11

1
reserve DA21,DA22 by vender review 08/21 Follow PAV70 Delete JSPK1
Tock 2010/12/08 1000P_0402_50V7K 2010/12/15 Tock
+3VS_AUDIO
1 1
CA44 CA45
1000P_0402_50V7K
40 mil 9/25 Add RA54~RA56
10U_0603_6.3V6M 0.1U_0402_16V4Z +3VS_DVDD 2 2
10/26 Remove DA4 CA46 CA47 RA23 RA24
1 1 1 Change RA54 package to 0603
Change RA31/ RA32 package to 0402 +5VS 1 2 Michael 2010/11/18 10/28 Add JSPK1 (2 pin)
Michael 2010/11/18 RA54 0_0603_5% 1 1
CA19 CA21 CA20 10/28 Add DA4 CA46 CA47 RA23 RA24 CA46 CA47
2 2 2
@ 0.1U_0402_16V4Z 60 mil 0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K
+1.5VS 1
RA31
2
0_0402_5% 20 mil +5VS_AVDD 1 1 11/16 Change CA5,CA8,CA11,CA13,CA17,CA18,CA19,CA23,CA25, package from 0805 to 0603
2 2

1 2 1U_0402_6.3V6K +VDD_IO CA13 11/17 Change CA13 CA17 CA18 package from 0603 to 0805
+3VS_AUDIO

1
RA32 0_0402_5% CA12 10U_0805_10V6K
2 2
1 1
RA40 9/6 Update QA2 symbol
9/3 Change CA38~ CA43 from 4.7U to 2.2U CA3 0_1206_5%
CA24 10/11 Change RA40 to 0 ohm (1206)

2
Change RA16 from 1k to 100 ohm 2 2
0.1U_0402_16V4Z 10/12 Change RA40 to 0.1 ohm (1206)
60 mil
Port Configuration
12/08 Change RA40 to 0 ohm (1206) Tock
0.1U_0402_16V4Z Port A: Headphone jack (jack shared with S/PDIF)
+CLASSD_5V 0.1U_0402_16V4Z 10U_0805_10V6K
20 mil 1 1 1 1 1
Port B: Internal MIC (mono or stereo)
+3VS_AUDIO
+3VS_VAUX Port C: Microphone/LI/LO jack
1 1 Port D: Line Out jack (Optional)
C CA14 CA15 CA16 CA17 CA18 C
2 0.1U_0402_16V4Z 2 2 2 2 Port E: Line In jack (Optional)
CA22 CA23
2 2 10U_0603_6.3V6M 10U_0805_10V6K
Port F: Internal AMIC
0.1U_0402_16V4Z Port G: Internal stereo speakers

21

29

31

15

18

20
4

9
UA1 Port J: Internal stereo digital mic (Optional)

VDD_IO
VAUX_3.3

DVDD_3.3

LPWR5.0

RPWR5.0

CLASSDREF
AVDD_HP

AVDD_5V
HP_LEFT 25 Port H: S/PDIF (jack shared with headphone)
<24> HP_LEFT PORTA_L
HP_RIGHT
10/26 Remove SPKR+ SPKR- function
<24> HP_RIGHT 26
PORTA_R
27
PORTD_L SPKL+
SPK_OUT_L+ 14
28
PORTD_R SPKL-
16
SPK_OUT_L-
Add INT Mic circuit on port F 33
PORTE_L SPKR+
Tock 2010/11/26 SPK_OUT_R+
19
RA17 34
PORTE_R SPKR-
10/28 Reserve CA57 CA58 for EMI
17 RA16
INT_MIC0 1 MIC0_R SPK_OUT_R-
2 CA42 1 2 MIC0_C_L 41 PORTF_L
2.2U_0603_6.3V6K 39 MIC2_C_L 1 2 CA40 MIC2_R 1 2 COM_MIC 11/01 Change CA57, CA58 from @ to mount
PORTB_L COM_MIC <24>
100_0402_1% CA43 1 2 MIC0_C_R 42 2.2U_0603_6.3V6K
2.2U_0603_6.3V6K PORTF_R MIC2_C_R 1
40 2 CA41 100_0402_1%
PORTB_R
change RA17 from 0 ohm to 100 ohm 1 22 2.2U_0603_6.3V6K Remove CA57 , CA58
FLY_P
Tock 2011/01/03
CA2 B_BIAS
38 9/1 Add CA49 RA41 on HP_SENSE Tock 2010/11/29
1U_0402_6.3V6K 23 8 HDA_SDIN0_AUDIO 1 2
2 FLY_N SDATA_IN RA27 33_0402_5% HDA_SDIN0 <13>
6 @ 08/31 Reserve CA48(22P) on HDA_SDOUT_AUDIO
MIC1_L SDATA_OUT HDA_SDOUT_AUDIO <13>
<24> MIC1_L
CA38 1 2 MIC1_C_L 35 2 CA48 1
2.2U_0603_6.3V6K PORTC_L @ 22P_0402_50V8J
10 HDA_SYNC_AUDIO
<13>
MIC1_R SYNC
<24> MIC1_R
CA39 1 2 MIC1_C_R 36 1 2 CA36
B 2.2U_0603_6.3V6K PORTC_R 22P_0402_50V8J B
RESET# 11
HDA_RST_AUDIO# <13>
+MIC1_VREFO 37 C_BIAS HDA_BITCLK_AUDIO_R 1
9/6 UA1 Pin 1 link to GNDA
7 2 HDA_BITCLK_AUDIO <13>
BIT_CLK RA28 0_0402_5%
20 mil 9/7 Change UA1 Pin1 to GND
1 2 CA31
22P_0402_50V8J 9/13 Add RA49 for DMIC
+3VS_AUDIO 1 2 1 @ Layout Note: close to UA1
RA7 5.11K_0402_1% MONO_IN DMIC_3/4
13
PCBEEP DMIC_CLK_R @ DMIC_CLK0 RA51 1 @
9/13 Add RA50~RA53 for DMIC
2 1 2 2 0_0402_5% DMIC_CLK <4,9>
HP_PLUG# DMIC_CLK0 RA49 90.9_0402_1%
<24> HP_PLUG# 2 1 <26> EC_MUTE# 12 EXT_MUTE# DMIC_DATA0
10/01 Remove RA50,R52
RA34 39.2K_0402_1% 3 RA53 1 @ 2 0_0402_5% DMIC_DATA <9,26>
DMIC_1/2
MIC_PLUG# 1 2
<24> MIC_PLUG#
RA18 10K_0402_1%

COM_MIC_PLUG# 2 1 SENSEA 44 46 1 2
<24> COM_MIC_PLUG# SENSE A GPIO1/SPK_MUTE# EAPD <26>
RA33 20K_0402_1% 43 45 RA29 0_0402_5%
SENSE B GPIO2/SPDIF2
Add INT Mic circuit on port F
Add net GPIO_0 by vender review <24> GPIO_0
47
GPIO0/EAPD# 20 mil Tock 2010/11/26
Tock 2011/01/03 48 5 +FILT_1.8V 0.1U_0402_16V4Z 10U_0603_6.3V6M
SPDIFO FILT_1.8

1
+AVEE 24 32 +FILT_1.65V 1U_0402_6.3V6K 1 1
1 1
@ 20 mil
AVEE FILT_1.65 CA8 RA26 RA42
20 mil 1 1 49 30 +LDO_OUT_3.3V +LDO_OUT_3.3V CA1 CA7 CA9 +LDO_INT_MIC 1 1 2 +LDO_OUT_3.3V
EP_GND AVDD_3.3 2 2 1K_0402_5%

2
CX20584-21Z_QFN48_7X7 2 2 10K_0402_5% CA27
9/7 Add 0.1U (CA50) between GND & GNDA 1 1 20 mil 10U_0805_10V6K
CA10 CA11 0.1U_0402_16V4Z RA15
1 2 2 2 2
2.2K_0402_5%
CA50 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M CA6 CA5
0.1U_0402_16V4Z 2 2 10U_0603_6.3V6M

1
1 2
A CA51 0.1U_0402_16V4Z A
INT_MIC0
INT_MIC0 <24>
1 2
CA52 0.1U_0402_16V4Z

1 2 10/11 Update UA1 PN:SA000034020


CA53 0.1U_0402_16V4Z
Remove RA36,RA37,RA38,RA39 10/12 Update UA1 PN:SA000034010 (-11Z)
Security Classification Compal Secret Data Compal Electronics, Inc.
Add CA51,CA52,CA53,CA54 Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
1
CA54
2
0.1U_0402_16V4Z
by vender review 12/08 Update UA1 PN:SA000034020 (-21Z) Tock Audio Codec CX20584
Tock 2010/12/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
GND GNDA Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 17 of 37
5 4 3 2 1
5 4 3 2 1

+3V_LAN
Power On strapping
Pin Description Chip Default
RL15 2 @ 1 4.7K_0402_5% LAN_CLKREQ#_R
RL16 2 @ 1 4.7K_0402_5% PLT_RST# H:Over Clock Enable
LED0 H
L:Over Clock Disable *
UL1

2 1 PCIE_C_RXP1 23 31 ACTIVITY
<12> PCIE_FRX_DTX_P2 TX_P LED[0] LAN_LINK#
CL6 .1U_0402_16V7K 32
PCIE_C_RXN1 LED[1]
<12> PCIE_FRX_DTX_N2 2 1 22 TX_N LED[2] 16
CL9 .1U_0402_16V7K
<12> PCIE_FTX_C_DRX_P2 28 RX_P
D MDI0+ RL527 D
1 2 49.9_0402_1% CL550 @ 1000P_0402_50V7K
<12> PCIE_FTX_C_DRX_N2 29 RX_N TRXP0 12
13 MDI0- RL526 1 2 49.9_0402_1% CL592 1 2 0.1U_0402_16V4Z
TRXN0
<12> CLK_PCIE_LAN 26 14
REFCLK_P TRXP1 MDI1+ RL529
<12> CLK_PCIE_LAN# 25 15 1 2 49.9_0402_1% CL551 @ 1000P_0402_50V7K
REFCLK_N TRXN1
1 2 LAN_CLKREQ#_R 17 MDI1- RL528 1 2 49.9_0402_1% CL593 1 2 0.1U_0402_16V4Z
<13> LAN_CLKREQ# CLKREQ#
RL12 0_0402_5%
PLT_RST# 3 11 LAN_RBIAS RL522 1 2 2.37K_0402_1% Close Pin 11
<12,20,21,26> PLT_RST# PERST# RBIAS
LAN_WAKE# 4 2 +3V_LAN
<26> LAN_WAKE# WAKE# VDD33
1 2 1 +1.7_LX
<13,20,21> FCH_PCIE_WAKE# LX
RL14 0_0402_5% 18
SMCLK
2010.08.21 Follow PAWGC 19
SMDATA +1.7_VDDCT CL552 1
6 2 0.1U_0402_16V4Z
VDDCT +1.7_VDDCT_REG
VDDCT_REG 5 W=40mils
20
YL1 TESTMODE +3V_LAN
33 GND
LAN_X1 1 2 LAN_X2 30 +1.1_DVDDL CL562 1 2 1U_0402_6.3V6K 1A
DVDDL_REG RL13 1
+3VALW 2 0_0603_5%
2 25MHZ_20PF_7A25000012 2 CL563 1 2 0.1U_0402_16V4Z

1000P_0402_50V7K

10U_0603_6.3V6M

10U_0603_6.3V6M
LAN_X1 8 10 +2.7_AVDDH
XTLO AVDDH_REG

1U_0402_6.3V6K
0.1U_0402_16V4Z
CL10 CL11 LAN_X2 9 CL571 1 2 1U_0402_6.3V6K
27P_0402_50V8J 27P_0402_50V8J XTLI @ QL1
1 1 1 1 1 1 1
24 CL572 1 2 0.1U_0402_16V4Z AP2301GN-HF_SOT23-3 CL5 CL8 CL7 CL1 CL34
AVDDL @
AVDDL
27 @
21 7 +1.1_AVDDL 3 1
NC AVDDL_REG 2 2 2 2 2

+1.1_AVDDL
AR8158-BL1A-RL_QFN32_4X4

2
C C

CL597

CL568

CL567

CL569
1U_0402_6.3V6K
close to LAN Pin 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
RL18 1 @ 2 10K_0402_5%
PLT_RST# EN_WOL# <26>
Reserve CL419 for PLT_RST#
2 2 2 2
1 Michael 2010/11/18 2
CL41
CL419 @
100P_0402_50V8J 0.1U_0402_16V4Z
2 LL39 LDO@ 1
+1.7_LX 1 2 +1.7_VDDCT RL520 1 2 0_0402_5% +1.7_VDDCT_REG
4.7UH_SIA4012-4R7M_20%
SWR@
10U_0805_10V6K
CL547

CL548

0.1U_0402_16V4Z 1 1
1 1 LL2
CL549 CL564 LDO@
DL8 @ SWR@ SWR@ 0.1U_0402_16V4Z 1U_0402_6.3V6K CL427 2 1 1U_0402_6.3V6K +1.7_VDDCT_R 2 1
2 2 +1.7_VDDCT
LAN_CLKREQ# 2 1 LAN_CLKREQ#_R
2 2 BLM18AG601SN1D_2P
RB751V-40_SOD323-2
TL1
Reserve DL8 for LAN_CLKREQ#
Tock 2011/01/05 MDI1+ 1 16 RJ45_MIDI1+
MDI1- RD+ RX+ RJ45_MIDI1-
2 15
CL436 RD- RX- RJ45_CT0
2 1 0.1U_0402_16V4Z 3 14
CT CT
4 NC NC 13
CL554 @ 1000P_0402_50V7K 5 12
NC NC RJ45_CT1
6 11
CL437 MDI0+ CT CT RJ45_MIDI0+
2 1 0.1U_0402_16V4Z 7 10
MDI0- TD+ TX+ RJ45_MIDI0-
8 9
CL555 @ 1000P_0402_50V7K TD- TX-
B B
350uH_NS0013LF

JRJ45 CONN@
RJ45_MIDI0+ 1 change T1 to SP050005900 <MHPC>
PR1+
LED_YELLOW_A1
9 but use BOTH_GST5009-LF_24P footprint
RJ45_MIDI0- 2 2010/12/14 Tock
PR1- LAN_ACTIVITY#_R ACTIVITY
10 2 1
RJ45_MIDI1+ LED_YELLOW_A2 @ RL17 511_0402_1%
3
PR2+ CL33 1 2 470P_0402_50V7K change TL1 PN to SP050006E00
4 PR3+ 2011/02/11 Tock

1
11 LAN_LINK# 1
LED_GREEN_B1 RL19 CL35 @
5 PR3-
12 LAN_SK_LAN_LINK#_1 RL11 1 2 511_0402_1%
LED_GREEN_B2 +3V_LAN
RJ45_MIDI1- 6 5.1K_0402_5% 470P_0402_50V7K
PR2- 2
1
2

7 13
PR4+ GND CL32 75_0402_5% 2 RL7 RJ45_CT0
14 1
GND
8 470P_0402_50V7K
PR4- 2
@
SANTA_130451-F 75_0402_5% 2 1 RL8 RJ45_CT1

1
For EMI. CL15
1000P_1206_2KV7K
DL1
change JRJ45 to DC234005300 LANGND 1 2 RJ45_GND
CL38 1000P_1206_2KV7K LANGND 2
2010/12/14 Tock 2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
CL39

CL40

1 1 3 LANGND Remove DL2~DL13


RJ45_GND
2010/12/06 Tock
PJDLC05C_SOT23-3
A 2 2 LL3 MCK3225201YZF_2P A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN AR8158
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom P1VE6 Schematics 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 18 of 37

5 4 3 2 1
5 4 3 2 1

+CARDPWR +CARDPWR

30mil 30mil

1 1

2
1 CC8 CC7
0.1U_0402_16V4Z 0.1U_0402_16V4Z
RC6 CC9 2 2
100K_0402_5% 0.1U_0402_16V4Z close pin 11 close pin 18
D @ 2 D

1
close pin 22
Card Reader Connector
JREAD1 CONN@
+CARDPWR 22 XD-VCC SD4-VDD 11 +CARDPWR
18
XDD0_SDCLK_MSD2 MS9-VCC RC7 @
30 XD10-D0
XDD1_MSD0 29 9 XDD0_SDCLK_MSD2 1 2 @
XDD2_SDCMD XD11-D1 SD5-CLK XDCLE_SDD0 CC11 4.7P_0402_50V8C
28 XD12-D2 SD7-DAT0 4
XDD3 27 3 XDCE#_SDD1 0_0402_5%
XDD4_SDD3_MSD1 XD13-D3 SD8-DAT1 XDD5_SDD2
26 21
XDD5_SDD2 XD14-D4 SD9-DAT2 XDD4_SDD3_MSD1
25 19
XDD6_MSBS XD15-D5 SD1-DAT3 XDD2_SDCMD
24 XD16-D6 SD2-CMD 16 Reserve RC7 , CC11 , RC8 , CC12 for EMI
XD_D7 23 1 XDWE#_SDCD#
XD17-D7 SD-CD XDDRY_SDWP_MSCLK
Tock 2010/12/28
SD-WP 2
XDWE#_SDCD# 33
XDWP# XD07-WE
32 6
XDALE_MSD3 XD08-WP SD6-VSS
34 13
XD_CD# XD06-ALE SD3-VSS
39 XD01-CD
XDDRY_SDWP_MSCLK 38 2010.11.02 Del LED circuit
XDRE#_MSINS# XD02-R/B RC8 @
37
XDCE#_SDD1 XD03-RE XDDRY_SDWP_MSCLK @
36 XD04-CE MS8-SCLK 17 1 2
XDCLE_SDD0 35 10 XDD1_MSD0 CC12 4.7P_0402_50V8C
XD05-CLE MS4-DATA0 XDD4_SDD3_MSD1 0_0402_5%
8
MS3-DATA1 XDD0_SDCLK_MSD2
31 XD GND MS5-DATA2 12
40 15 XDALE_MSD3
XD GND MS7-DATA3 XDRE#_MSINS#
MS6-INS
14 Remove CC13 by vender review
7 XDD6_MSBS
C MS2-BS 12/08 Tock C
MS1-VSS 5
41 20
SD CD/WP GND MS10-VSS
42
SD CD/WP GND
T-SOL_144-1300002600_NR

2010.08.19 Copy Symbol from NCQF0


change JREAD1 to SP07000NV00 change JREAD1 to SP07000LW00 for Layout
2010/12/14 Tock 2010/01/05 Tock

+3VS +3VS_CR
JR1 @ +3VS
1
1 2
2 30mil Share Pin XD SD MS
JUMP_43X39
1
XD_CD#
RTS5138 RC5
10K_0402_5%
SP1 XD_RDY SD_WP MS_CLK
CC2 2 1 100P_0402_50V8J 10mil
2

UR1
1 2 RREF 1 SP2 XD_RE# MS_INS#
RC1 6.2K_0603_1% REFE CARD_LED#
17
USB20_N6 GPIO0 CARD_LED# <22>
<13> USB20_N6 2
USB20_P6 DM
<13> USB20_P6 3
DP CLK_IN
24 CLK_48M_CR <12> SP3 XD_CE# SD_D1
+3VS_CR 4 23 XD_D7
3V3_IN XD_D7
1
B +CARDPWR B
30mil 5 CARD_3V3 SP4 XD_CLE SD_D0
VREG 6 22 XDD6_MSBS RC2
V18 SP14 XDD5_SDD2
1 2 1 10mil XD_CD# SP13
21
XDD4_SDD3_MSD1
22_0402_5%
7 XD_CD# SP12 20 SP5 XD_ALE MS_D3
CC1 CC10 CC3 19 XDD3
2

SP11
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

1U_0402_6.3V6K

XDDRY_SDWP_MSCLK_L 8 18 XDD2_SDCMD
2 1 2 XDRE#_MSINS# SP1 SP10 XDD1_MSD0
9
SP2 SP9
16 1 SP6 XD_WE# SD_CD#
XDCE#_SDD1 10 15 XDD0_SDCLK_MSD2_L
SP3 SP8
EPAD

XDCLE_SDD0 11 14 XDWP# CC4


XDALE_MSD3 SP4 SP7 XDWE#_SDCD#
12 SP5 SP6 13
2
10P_0402_50V8J SP7 XD_WP
RTS5138-GR_QFN24_4X4
25

SP8 XD_D0 SD_CLK MS_D2

SP9 XD_D1 MS_D0


Change net name from XDD5_SDD2_MS_D5 to XDD5_SDD2
Close to chip 11/26 Tock SP10 XD_D2 SD_CMD

SP11 XD_D3
XDDRY_SDWP_MSCLK_L 1 2 XDDRY_SDWP_MSCLK

RC3 0_0402_5% 1 SP12 XD_D4 SD_D3 MS_D1


CC5 @
4.7P_0402_50V8C SP13 XD_D5 SD_D2
2

SP14 XD_D6 MS_BS


A XDD0_SDCLK_MSD2_L 1 XDD0_SDCLK_MSD2 A
2
XD_D7
RC4 0_0402_5% 1
CC6 @
4.7P_0402_50V8C
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Add RC3 , CC5 ,RC4 , CC6 by vender review for EMI sol. Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
12/08 Tock
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CARD READER RTS5138
change CC5 , CC6 BOM structure to @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
2011/01/03 Tock DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 19 of 37
5 4 3 2 1
A B C D E

+1.5VS_WWAN
W=40mil

Mini-Express Card for WWAN 3G@ 3G@ 3G@ 3G@

1 1 1
1 C264 C265 C266

0.01U_0402_25V7K
0.1U_0402_16V4Z

4.7U_0603_6.3V6K
3G@ C263

47P_0402_50V8J
+1.5VS 1 2 +1.5VS_WWAN
R335 0_0805_5% 2 2 2 +3VS
2

9/3 Reserver +3VALW for BT (R378 R374)

1
W=40mil 1
+3VS_WWAN 8/31 Change MCP@ to 3G_MP@ 1
3G@ 3G@ 3G@ 3G@ 3G@
10/04 Add 100p(C402) on BT_ON# C267 BT@
2011/02/11 Change Q13 PN to SB000006R10
Reserve C293 for RF
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Tock 2010/12/28 2
1 1 1 1 1 BT@
C268 C270 C271 R226 +3VALW +3VS
C269
C293 C272
22P_0402_50V8J
@ 2
0.1U_0402_16V4Z
2 2 2
0.01U_0402_25V7K
2
47P_0402_50V8J <21,26> BT_ON#
2 1 BT MODULE CONN

2
8/22 Reserve R335 (0 ohm 0805) Add net +1.5VS_WWAN 10K_0402_5% BT@
10U_0805_10V6K R374 R378
8/25 Change C269,C275 to SE000004880 Standard Part 2 0_0603_5% 0_0603_5%
@
BT@ C402 +3VS_BT

1
100P_0402_50V8J Q13 BT@
1 AO3413L_SOT23-3 BT@
+3VS_WWAN C273
Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T 06/29 +3VS +3VS_WWAN +3VALW +3V_BT 3 1 2 1

D
1
10/27 Add R412 (0 ohm) on FCH_PCOE_WAKE# 3G@ @ 0.1U_0402_16V4Z

G
1 2 1 2 @ C274 +

2
R227 0_1206_5% R228 0_1206_5%
150U_B_6.3VM_R40M

+3VS_BT
9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE# 2
Close to WWAN CONN
JMINI1 CONN@
FCH_PCIE_WAKE# 1 @ 2 1 2
<13,18,21> FCH_PCIE_WAKE# 1 2
R412 0_0402_5% 3 4 8/26 Change Q13 to SB934130020 Standard Part
3 4 JBT1
5 6 +1.5VS_WWAN
WWAN_CLKREQ# 5 6 +UIM_PWR
<13> WWAN_CLKREQ# 7 7 8 8 1 1
9 10 UIM_DATA 2
9 10 UIM_CLK USB20_P7 2
<12> CLK_PCIE_WWAN# 11 12 3 5
11 12 UIM_RST <13> USB20_P7 USB20_N7 3 G1
2 <12> CLK_PCIE_WWAN 13
13 14
14
UIM_VPP
10/04 Add 100p(C398) on UIM_RST <13> USB20_N7
4
4 G2
6
2
15 15 16 16
17 18 10/06 Remove C398 ACES_88266-04001
17 18 WXMIT_OFF# CONN@
19 20 WXMIT_OFF# <26>
19 20 R229 1 3G@
21 21 22 22 2 0_0402_5% PLT_RST# <12,18,21,26>
<12> PCIE_FRX_DTX_N1 23 23 24 24
<12> PCIE_FRX_DTX_P1 25 26
25 26
27 27 28 28 9/1 Change R230 R231 from NON3G@ to mount
29 30 R230 1 3G@ 2 0_0402_5%
29 30 FCH_SMCLK0 <7,8,13,21>
31 32 R231 1 3G@ 2 0_0402_5%
<12> PCIE_FTX_C_DRX_N1 31 32 FCH_SMDAT0 <7,8,13,21>
<12> PCIE_FTX_C_DRX_P1 33 34
33 34 USB20_MINI_N
35 35 36 36
USB20_MINI_P
8/22 Update JBT1 Symbol from database (ACES_88266-04001_4P)
37 38
C275 10U_0805_10V6K 3G@ 37 38
+3VS_WWAN 39 39 40 40
1 2 41 42
41 42 WLAN_LED#_R 3G@ 2 WWAN_LED# <21,22>
43 44 1
WWAN_WAKEUP_R# 43 44 R232 0_0402_5% WLAN_LED# <21,22> USB20_MINI_N R246 1 @
45 46 (9~16mA) 2 0_0402_5%
45 46 USB20_MINI_P R248 1 @ USB20_N3 <13>
47 48 2 0_0402_5%
47 48 USB20_P3 <13>
49 50
49 50
51 52
51 52
53 54 USB20_MINI_P R250 1 3G@ 2 0_0402_5%
GND1 GND2 USB20_MINI_N R252 1 3G@ USB20_P9 <13>
2 0_0402_5%
USB20_N9 <13>
PLAST_SSM010-52-B-K 10/31 Add R417~R420 for co-lay USB port3 & port9
9/9 Remove D9
11/01 Change R417 R418 from mount to @ Change R417, R418 to RP9 Change R419, R420 to RP10
change JMIN1 to SP07000QC00 Change R419 R420 from mount to @ SW request (P0VE6-0045)
Michael 2010/12/23 Michael 2010/12/23
3G@ 2010/12/14 Tock Swap USB net of RP10 for layout
C282 2 1 1U_0402_6.3V6K +UIM_PWR Tock 2010/12/24
3 3G@ Change RP9 to R246 , R248 Change RP10 to R250 , R252 3
C283 2 1 0.1U_0402_16V4Z Tock 2010/12/30 Tock 2010/12/30
3G@ PLT_RST#
C284 2 1 56P_0402_50V8
2
3G@ W=20mil JSIM1 9/1 Change R234 from mount to @
C285 2 1 56P_0402_50V8 +UIM_PWR 1 3G@ C479
UIM_RST VCC
2 100P_0402_50V8J
UIM_CLK RST 1
3 CLK
<13> USB20_P4 4 Reserved
5 +3VALW
UIM_VPP GND
6 VPP
UIM_DATA 7
I/O
<13> USB20_N4 8 Reserved

1
56P_0402_50V8

22P_0402_50V8J

3G@ 1 @ 1 9
3G@ CD R234
1

C278 2 1 100P_0402_50V8J UIM_RST 10 10K_0402_5% @


GND
C276

C277

2 11
2 GND
R233

2
C279 2 1 22P_0402_50V8J ACON_SCR4W-8K1000
@ CONN@ 1 2 WWAN_WAKEUP_R#
<26> WWAN_WAKEUP#
2

10K_0402_5% R235 0_0402_5%


@
+UIM_PWR change JSIM1 to SP07000NW00
Modifiy 05/11 2010/12/28 Tock

@
C280 2 1 22P_0402_50V8J UIM_CLK
4 4
8/22 Update JP1 Symbol from database (TAITW_PMPAT7-08GLBS1N14H0_9P)
3G@ Reserve for SIM card does not meet rise time 10/06 Change C278 to 100p
C281 2 1 22P_0402_50V8J and pull-up is needed.

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/BT CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 20 of 37
A B C D E
5 4 3 2 1

D D
EC_TX_P80_DATA R253 1 2 0_0402_5% EC_TX_P80_DATA_R
<26> EC_TX_P80_DATA EC_RX_P80_CLK
<26> EC_RX_P80_CLK
R254 1 2 0_0402_5% EC_TX_P80_CLK_R

Mini-Express Card for WLAN


Change R236, R237 to RP11
Michael 2010/12/23
Change RP11 to R253 , R254
Michael 2010/12/30

+3VS_WLAN
W=40mil +1.5VS_WLAN
W=40mil

1 1 1 1 1 1 +1.5VS 1 2 +1.5VS_WLAN
R336 0_0805_5%
C286 C287 C288 C289 C290 C291
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 47P_0402_50V8J 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2 2 2

8/22 Reserve R336 (0 ohm 0805) Add net +1.5VS_WLAN


C C

change JMIN2 to SP07000QC00


2010/12/14 Tock
9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE# PLT_RST#
J2 1
JUMP_43X79
JMINI2 CONN@ @ C446
1 2 +3VS_WLAN 1 1
<13,18,20> FCH_PCIE_WAKE# 1 2 2 2 +3VS 2
100P_0402_50V8J
3 4
3 4
<20,26> BT_ON# 2 R238 1 5 5 6 6 +1.5VS_WLAN
@ 0_0402_5% 7 8
<13> WLAN_CLKREQ# 7 8
9 10
9 10
<12> CLK_PCIE_WLAN# 11 12 Add C446 on PLT_RST# for switching noise
11 12
<12> CLK_PCIE_WLAN 13
13 14
14 Tock 2010/12/28
15 16
15 16
17 18
17 18
19 19 20 20 WL_OFF# <26>
21 22 PLT_RST# <12,18,20,26>
21 22 Change RP12 to R255 ,R256
<12> PCIE_FRX_DTX_N3 23 24
23 24
<12> PCIE_FRX_DTX_P3 25
25 26
26 Tock 2010/12/30
27 28
27 28 R255 1
29 30 2 0_0402_5% FCH_SMCLK0 <7,8,13,20>
29 30 R256 1
<12> PCIE_FTX_C_DRX_N3 31 32 2 0_0402_5%
31 32 FCH_SMDAT0 <7,8,13,20>
<12> PCIE_FTX_C_DRX_P3 33 33 34 34
35 36
35 36 USB20_N8 <13>
+3VS_WLAN
37
37 38
38
USB20_P8 <13> 9/20 Add R393 R394 for SMBus
39 40
39 40 WWAN_LED#_R
41 42 1 R241 2 9/17 Remove R239,R240
41 42 0_0402_5% WWAN_LED# <20,22>
43 44
43 44

2
B B
1 45 45 46 46 @
47 48 R242
C292 EC_TX_P80_DATA_R 47 48
49 50
10U_0603_6.3V6M EC_TX_P80_CLK_R 49 50 0_0402_5%
51 51 52 52
2

1
1

R243
53
GND1 GND2
54 (9~16mA)
100K_0402_5%
PLAST_SSM010-52-B-K WLAN_LED# <20,22>
2

5/12
6/1
6/12
、 、 、 、
Update WLAN connector(the same as KAV60)
Revised 37 39 41 42 43 to NC
Update connector to DC040006S00
6/26 Update JMINI1 footprint
7/01 update pin 23,25,31,33

A A

Compal Electronics, Inc.


Title
WLAN
WLAN
Size Document Number Rev
CustomP1VE6 Schematics 1.0
LA-6222P
Date: Thursday, March 17, 2011 Sheet 21 of 37
5 4 3 2 1
A B C D E F G H

+3VS
LED PCB CONN

1
MEDIA_LED#
JLED1 R373
W=40mil
+3VALW 1 10K_0402_5%
1 +3VS
<26> PWR_LED# 2
2
<26> PWR_SUSP_LED# 3

2
3

1
1 D 1
<26> BATT_BLUE_LED# 4 4
<26> BATT_AMB_LED# 5 5 2
MEDIA_LED# 6 G
6

5
W=40mil +3VS 7 U8 S Q34

3
7

1
D SSM3K7002FU_SC70-3
8 2

P
8 <19> CARD_LED# B
<20,21> WWAN_LED# 9 9 Y 4 2
10 HDD_LED# 1 G
<20,21> WLAN_LED# 10 <14> HDD_LED# A

G
11 13 S

3
11 GND Q35
12 14

3
12 GND NC7SZ08P5X_NL_SC70-5 SSM3K7002FU_SC70-3

ACES_85201-1205N
CONN@

8/22 Update JP2 Symbol from database (ACES_85201-1605N_16P)


8/24 Update JLED1 Symbol from database (ACES_85201-1205N_12P) & Update pin definition
9/1 Add R373, Q34, Q35 for MEDIA_LED#
9/1 Add LED Circuit (LED2~4(SC597UDB000)LED5(SC5191NB000), R360~R369, Q33)
9/1 Change All LED power to 5V
9/9 Change LED2~4 footprint to LED_HT-297DQ-GQ_4P
9/11 Remove LED portion

2 2

+5VS_HDD
Add C11~C14 from HDD board
2011/01/07 Tock
0.1U_0402_16V4Z 10U_0805_10V6K

1 1 1 1
C12 C11 C13 C14

3 2 2 2 2 3

1000P_0402_50V7K 1U_0402_6.3V6K

SATA HDD Conn. 8/22 Change C298 from 10U 6.3V to 10U 10V
8/22 Reserve R337 R338 Add net +3VS_HDD,+5VS_HDD
9/1 Change Q33 to SB000009610(SSM3K7002FU_SC70-3)
JHDD1 change JHDD1 to SP01000E400 , delete C293 ~ C298
1 2010/12/14 Tock
SATA_ITX_DRX_P0 1
<14> SATA_ITX_DRX_P0 2
SATA_ITX_DRX_N0 2
W=40mil <14> SATA_ITX_DRX_N0 3 3 Modify JHDD1 pin define
4
+3VS 1 2 +3VS_HDD <14> SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_N0 5
4 2010/12/15 Tock
R337 0_0805_5% SATA_DTX_C_IRX_P0 5
<14> SATA_DTX_C_IRX_P0 6
6
7
7
+3VS_HDD 8
8
+5VS 1 2 +5VS_HDD 9
R338 0_0805_5% 9
+5VS_HDD 10 10
11 13
11 GND
W=100mil 12 12 GND 14

ACES_85201-1205N

CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
SATA CONN./LED/B CONN./BATT CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 22 of 37
A B C D E F G H
ON/OFF Button
8/26 Change D11 to SC600000B00 Standard Part
updated SW1 symbol for SN100002K00

6
5
2010/12/06 Tock

G
G
2 4
ON/OFFBTN#
1 3 +3VALW

SW1

2
EVQPLMA15_4P
9/20 Remove R245,R248,D12
R247

100K_0402_5%
D11

1
3 ON/OFF#
FOR EMI ON/OFFBTN# 1
2 51_ON#
ON/OFF# <26>

51_ON# <30>
BAV70W_SOT323-3 place close to PR4
PWR_LED1# C299 1 2 @ 100P_0402_50V8J
2 51_ON#
ON/OFFBTN# C301 1 2 @ 100P_0402_50V8J C300 1
1000P_0402_50V7K C478
1
100P_0402_50V8J
2

Reserve C478 for 51_ON#


Tock 2011/01/07

1
D
EC_ON 2 Q14
<26> EC_ON
G SSM3K7002FU_SC70-3

2
S

3
R249
EC_ON 10K_0402_5%
1

1
C473 8/26 Change Q14 to SB000009610 Standard Part
100P_0402_50V8J
2
9/6 Change D13 from mount to @
10/05 Remove D13 Reserve C473 for EC_ON
Tock 2011/01/07

9/1 Remove LED2 LED3 circuit, Change 70@ to mount 9/24 Change U9 to SA00001TC00

9/20 Add LED2 LED3 Circuit


9/21 Remove LED2 LED3 Circuit
LID Switch

+3VS
W=20mil
change R251 from 51 ohm to 220 ohm +3VALW
2011/03/07 Tock (BLUE)
1
1

change R251 from 220 ohm to 100 ohm C302


0.1U_0402_16V4Z
2011/03/16 Tock R251 2 AH180WG-7_SC59-3
100_0402_1%~N 2 VDD
1
GND
2

OUTPUT 3
LID_SW# <26>
2

10P_0402_50V8J
U9 1
LED2 LED1
@ HT-191NB5-DT BLUE 0603 HT-191NB5-DT BLUE 0603 C303
2
1

PWR_LED1#
PWR_LED1# <26>

10mil

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
ON/OFF / PWR SW/ LID SW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 23 of 37
5 4 3 2 1

Change CP1 to C398 , C419 , C448 , C449 Change CP4 to C461 , C458 , C460 , C459
Change CP2 to C453 , C450 , C452 , C451 Change CP5 to C465 , C462 , C464 , C463
JKB1
To TP/B Conn. 8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P)
Change CP3 to C457 , C454 , C456 , C455 Change CP6 to C469 , C466 , C468 , C467
Tock 2010/12/30 Tock 2010/12/30 26 G2 8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP
25 G1
KSI0 24 8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P)
KSI1 24
23 23
KSO15 C398 1 2 100P_0402_50V8J KSO7 C461 1 2 100P_0402_50V8J Swap KB signal KSI2 22 & Update pin definition
KSO14 C419 100P_0402_50V8J KSO6 C458 100P_0402_50V8J KSO0 22
1 2 1 2 for layout 21 21
KSO13 C448 1 2 100P_0402_50V8J KSO5 C460 1 2 100P_0402_50V8J Tock KSO1 20
KSO12 C449 100P_0402_50V8J KSO4 C459 100P_0402_50V8J KSO2 20
1 2 1 2 2010/12/24 19 19 W=20mil
KSI3 18 JTP1
KSO3 18
D 17 17 1 1 D
KSO4 16 TP_DATA 2
KSO5 16 <26> TP_DATA TP_CLK 2
15 15 <26> TP_CLK 3 3
KSI7 C453 1 2 100P_0402_50V8J KSO3 C465 1 2 100P_0402_50V8J KSO6 14 2 1 +5VS_TP 4
KSO11 C450 100P_0402_50V8J KSI3 C462 100P_0402_50V8J KSO7 14 +5VS 0_0402_5% 4
1 2 1 2 13 13 5 G1

3
KSO10 C452 1 2 100P_0402_50V8J KSO2 C464 1 2 100P_0402_50V8J KSO8 12 R339 6
KSI6 C451 100P_0402_50V8J KSO1 C463 100P_0402_50V8J KSI4 12 G2
1 2 1 2 11 11
KSO9 10 ACES_85201-0405N
KSI5 10 CONN@
9 9
KSI6 8 D14
KSO10 8 @
7 7
KSI5 C457 1 2 100P_0402_50V8J KSO0 C469 1 2 100P_0402_50V8J KSO11 6
KSO9 C454 100P_0402_50V8J KSI2 C466 100P_0402_50V8J KSI7 6
1 2 1 2 5 5
KSI4 C456 1 2 100P_0402_50V8J KSI1 C468 1 2 100P_0402_50V8J KSO12 4

1
KSO8 C455 100P_0402_50V8J KSI0 C467 100P_0402_50V8J KSO13 4 PJDLC05C_SOT23-3
1 2 1 2 3 3
KSO14 2
KSO15 2
1 1
ACES_85202-24051
KSI[0..7] CONN@
KSI[0..7] <26>
KSO[0..15]
8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P)
KSO[0..15] <26> 8/23 Update KB pin definition
INT_KBD Conn.

C
Combo Jack CMBS@ QA36 change RA59 from 750 to 220 ohm C
MMBT3906H_SOT23-3 by vender review for bo bo noise
Tock 2011/03/16

2
+LDO_OUT_3.3V RA14 1 2 0_0402_5% COM_MIC_R 3 1
CMBS@ RA35
1 2.2K_0402_5%
NCMBS@
1

1
CA25

1
10U_0805_10V6K CMBS@ RA30 RA59
2

@ 2 220_0402_5%
100K_0402_5%

Add RA58 for net GPIO_1 CMBS@


RA13
CMBS@
2

2
by vender review for pop issue
1 2 COM_MIC
Tock 2010/12/08
change GPIO_1 to GPIO_0
COM_MIC <17> 11/17 Move HP JACK and MIC JACK Circuit to IO Board.
2K_0402_5%
1

1
Tock 2011/01/03
CMBS@ RA50 1 RA57 change RA57 from 47K to 15K ohm Add net INT_MIC0 on JIO1 pin 2
10K_0402_5% 15K_0402_1% by vender review for bo bo noise Tock 2010/11/26
1 2 CA28 Tock 2011/03/16
<17> GPIO_0 10U_0805_10V6K CMBS@ JIO1
2

2
DA10 RB491D_SC59-3 CMBS@ 2
1 1
CMBS@ INT_MIC0 2
<17> INT_MIC0 2
QA3 RA14 MIC1_L 3
D <17> MIC1_L 3
1

CMBS@ MIC1_R 4
<17> MIC1_R 4
HP_SENSE 1 2 2 BSS138_NL_SOT23-3 +MIC1_VREFO 5
RA52 G MIC_PLUG# 5
<17> MIC_PLUG# 6 6
100K_0402_5% S change RA12 BOM structure to @ <17> COM_MIC
COM_MIC 7
3

B CMBS@ HP_LEFT 7 B
1 by vender review for pop issue <17> HP_LEFT 8 8
1

Tock 2010/12/08 1K_0402_5% HP_RIGHT 9


<17> HP_RIGHT 9
RA58 CA26 +5VS 10
270K_0402_5% 1U_0603_10V6K NCMBS@ HP_SENSE 10
11 11
CMBS@ 2 CMBS@ 12 12
13
2

USB_ON# 13
<25,26> USB_ON# 14 14
+5VALW 15 15
11/17 Add Combo solution circuit for P0VE6 "POPO" noise COM_MIC_PLUG#
16
17
16
Add IO connector
COM_MIC_PLUG# <17> 17
change RA52,DA10,CA26 BOM structure to @ <13> USB_OC0#
USB_OC0# 18 18 Michael 2010/11/18
by vender review for pop issue change RA9 from 20K to 0 ohm 19
USB20_P0 19
Tock 2010/12/08 Tock 2011/03/03 <13> USB20_P0 20 20
6

USB20_N0 21
<13> USB20_N0 USB20_P1 21
<13> USB20_P1 22 22
RA9 QA1A USB20_N1 23
2N7002KDW H_SOT363-6 <13> USB20_N1 23
2 1 2 24 24
25 CONN@
HP_PLUG# 0_0402_5% G1
26
1

HP_PLUG# <17> G2

RA55 ACES_85202-24051
D
3

10K_0402_5%
QA4 2 1 2 COM_MIC
RA36 QA1B BSS138_NL_SOT23-3 G 1
HP_SENSE 1 2 5 2N7002KDW H_SOT363-6 S
3

CA29
0_0402_5% 1U_0603_10V6K
4
1

Add QA4,RA55,CA29,RA36 for Internal Mic 2


A 1 A
RA41 CA49 @ can't record issue . Tock 2011/02/21
20K_0402_5% 0.1U_0402_16V4Z
2 remove CA4 change QA1 , QA2 from SB501380020 <BSS138> to SB00000EO10 <2N7002>. Tock 2011/02/24
2

change CA49 BOM structure to @ Security Classification Compal Secret Data Compal Electronics, Inc.
change RA41 from 47K to 4.7K Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
by vender review for pop issue
Tock 2010/12/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB Conn/TP/IO Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 24 of 37
5 4 3 2 1
A B C D E

1 1

11/17 Move Left Side USB CONN. Circuit to IO board

2 2

+5VALW +USB_VCCC1
Right Side USB CONN.
W=80mils W=80mils
U11 Change C340 to SF000001500
3 3
1 8
2
GND VOUT
7 2010/12/14 Tock
VIN VOUT
3 6
VIN VOUT +USB_VCCC1
EPAD

<24,26> USB_ON# 4 EN FLG 5 USB_OC1# <13> 9/28 Swap L28


1
AP2301MPG-13_MSOP8 W=80mils
9

C338 1
0.1U_0402_16V4Z C339 1 R257
2 @ 1000P_0402_50V7K 0_0402_5%
1
C340 + C341 1 @ 2
2 220U_6.3V_M
SA00003XM00 470P_0402_50V7K
2 2
L28
2 1 USB20_N2_1
JUSB1 <13> USB20_N2 2 1
SGA00002N80
1
USB20_N2_1 VCC USB20_P2_1
2 3 4
USB20_P2_1 D- <13> USB20_P2 3 4
8/25 Change C340 from poly-cap to E-cap (SF000001500) 3
D+
4 WCM-2012-900T_4P
GND
5 GND
6
GND @
7 GND 1 2
8 R258 0_0402_5%
GND
SUYIN_020173GB004M25MZL
CONN@

change JUSB1 to SP060004B00


4 2010/12/14 Tock 4

delete D17 for DFB issue


2011/02/25 Tock

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB PORTS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 25 of 37
A B C D E
5 4 3 2 1

8/23 Pull up 10k (R345) to +3VALW on USB_ON# +3VS


SUSP# place close to PU4 and PU7 8/31 Change EC_MUTE# Pull-up to +3VS(@) +3VALW
1 1
Reserve C403, C443, C444 EC_MUTE# R259 2 @ 1 10K_0402_5%
C475 C476 8/21 Change R262 from 0 ohm 0805 to 0 ohm 0603 for ADP_I, TP_CLK, DATA
100P_0402_50V8J 100P_0402_50V8J Michael 2010/11/18 USB_ON# R345 2 1 10K_0402_5%
2 2
R262 W=40mils L29 W=20mils
Reserve C475,C476 for SUSP# +3VALW 0_0603_5% FBMA-L11-160808-800LMT_0603 ADP_I TP_CLK TP_DATA
Tock 2011/01/07 1 2 +3VALW_EC 1 2 +EC_VCCA 1 1 1 +5VS
1 1 1 1 2 2 1

0.1U_0402_16V4Z
C342

0.1U_0402_16V4Z
C343

0.1U_0402_16V4Z
C344

0.1U_0402_16V4Z
C345

1000P_0402_50V7K
C346

1000P_0402_50V7K
C347
@ C403 @ C443 @ C444 TP_CLK R263 1 2 4.7K_0402_5%
C348 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
D 0.1U_0402_16V4Z 2 2 2 TP_DATA R264 1 2 4.7K_0402_5% D
2 2 2 2 1 1 2

ECAGND
@C349
@ C349 @R265
@ R265
22P_0402_50V8J 33_0402_5%
2 1 2 1 LPC_CLK0_EC 9/23 Update EC pin definition follow P5WE6 8/26 Change D18 to SCS00002G00 Standard Part

111
125
PLT_RST# 10/04 Add 100p(C399) on ACOFF 9/23 Reserve R395 on ACIN

22
33
96

67
U12

9
1
Reserve C420 for PLT_RST# Delete EC_FAN_PWM 10/08 Change D18 to SCS00000Z00

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
C399 +3VALW
C420 Michael 2010/11/18 Tock 2011/01/28
100P_0402_50V8J ACOFF 2 1
R267 2 EC_RST# 2
+3VALW 1 47K_0402_5% R268 2 1 200K_0402_5%
GATEA20 1 21
<13> GATEA20 KB_RST# GATEA20/GPIO00 PWM0/GPIO0F BEEP# 100P_0402_50V8J
C350 2 1 0.1U_0402_16V4Z 2 23 D18
<13> KB_RST# KBRST#/GPIO01 BEEP#/PWM1/GPIO10 BEEP# <17>
SERIRQ 3 PWM Output 26 2 1
<12> SERIRQ LPC_FRAME# SERIRQ# FANPWM0/GPIO12 ACOFF ACIN <31>
<12> LPC_FRAME# 4 27 ACOFF <31>
LPC_AD3 LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 RB751V-40_SOD323-2
5
<12> LPC_AD3 LPC_AD2 LPC_AD3/LAD3
7 LPC_AD2/LAD2
C351 2 1 100P_0402_50V8J ECAGND EC_ACIN C352 2 1 100P_0402_50V8J
+3VALW <12> LPC_AD2 LPC_AD1 BATT_TEMP
8 63 BATT_TEMP <29>
10/1 ENE Recommand <12> LPC_AD1 LPC_AD0 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 @
10 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 64 1 2
<12> LPC_AD0 ADP_I
LPC & MISC ADP_I/AD2/GPI3A
65 ADP_I <31>
R269 1 2 47K_0402_5% KSO1 LPC_CLK0_EC 12 66 AD_BID0 R395 0_0402_5%
<12> LPC_CLK0_EC PLT_RST# CLK_PCI_EC/PCICLK AD3/GPI3B AD_PID0
<12,18,20,21> PLT_RST# 13
PCIRST#/GPIO05 AD Input AD4/GPI42
75 8/23 Delete DAC_BRIG
R270 1 2 47K_0402_5% KSO2 EC_RST# 37 76
EC_SCI# EC_RST#/ECRST# AD5/GPI43 8/25 Delete CHG_ON#
<13> EC_SCI# 20 EC_SCI#/GPIO0E Follow PAWGC
EC_SMI#
38
CLKRUN#/GPIO1D 8/31 Add EN_FAN1 on U12.70
R271 1 @ 2 1K_0402_5% 68 @
DAC_BRIG/DA0/GPO3C EN_FAN1 D19 RB751V-40_SOD323-2
70
EC_SMB_DA1 EN_DFAN1/DA1/GPO3D IREF EN_FAN1 <27> ICH_POK_EC
R266 1 2 2.2K_0402_5% DA Output IREF/DA2/GPO3E
71 1 2
ICH_POK <13>
KSI0 55 72 CHGVADJ IREF <31>
KSI1 KSI0/GPIO30 DA3/GPO3F CHGVADJ <31>
EC_SMB_CK1
11/02 Change C353 to 10p R275 to 22 ohm KSI2
56 KSI1/GPIO31
R272 1 2 2.2K_0402_5% 57 1 2 1 @ 2 +3VS
KSI3 KSI2/GPIO32 EC_MUTE# LID_SW#
58 83 EC_MUTE# <17>
C C353 R275 KSI4 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_ON# R273 0_0402_5% R274 10K_0402_5% C
59 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 84 USB_ON# <24,25> 1
10P_0402_50V8J 22_0402_5% 8/23 Change R271 R279 from mount to @ KSI5 60 85
KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C PWR_LED1#
2 1 1 2 61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 PWR_LED1# <23>
C470
KSI7 62 87 TP_CLK 220P_0402_50V7K Reserve C470 for LID_SW#
KSI[0..7] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <24> 2
Reserve for EMI please close to U12 <24> KSI[0..7] KSO1
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88
TP_DATA <24> Tock 2011/01/07
40
+3VS KSO[0..15] KSO2 KSO1/GPIO21
<24> KSO[0..15]
KSO3
41 KSO2/GPIO22 9/25 Change VLDT_EN to VLDT_EN#
42 97
EC_SMB_CK2 KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 EN_WOL#
R276 1 @ 2 2.2K_0402_5% 43 98 EN_WOL# <18>
Add EDP_BIST and Reserve C390 , R285
+3VALW KSO5 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 VLDT_EN# EDP_BIST
KSO5/GPIO25 Int. K/B
44 99 VLDT_EN# <28> Tock 2010/12/30
R277 @ EC_SMB_DA2 KSO6 ME_EN/SDIMOSI/GPXIOA02 LID_SW# +3VALW
1 2 2.2K_0402_5% 45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 LID_SW# <23>

2
9/5 Change R276 R277 from mount to @ KSO7 46 SPI Device I/F
KSO8 KSO7/GPIO27 @ R285
47 KSO8/GPIO28
R279 1 @ 2 10K_0402_5% EC_SCI# KSO9 48 119 EC_SI_SPI_SO 100K_0402_5%
KSO10 KSO9/GPIO29 SPIDI/MISO EC_SO_SPI_SI EC_SI_SPI_SO <27> LID_SW#
49 120 R278 2 1 100K_0402_5%
KSO11 KSO10/GPIO2A SPIDO/MOSI EC_SPICLK EC_SO_SPI_SI <27>
8/31 EC_SCI# Pull up to +3VALW 50 SPI Flash ROM 126 EC_SPICLK <27>

1
KSO12 KSO11/GPIO2B SPICLK/GPIO58 EC_SPICS#/FSEL#
51 128 EC_SPICS#/FSEL# <27>
KSO13 KSO12/GPIO2C SPICS#
8/23 Delete R280 KSO14
52
KSO13/GPIO2D
53 R390 eDP@
Reserve C436, C437 for SMB KSO15 KSO14/GPIO2E EDP_BIST DMIC_DATA
54 KSO15/GPIO2F GPIO40 73 1 2 DMIC_DATA <9,17>
0_0402_5% +3VALW
Michael 2010/11/18 8/25 Delete KSO16 KSO17 81
KSO16/GPIO48 H_PECI/GPIO41
74
FSTCHG
82
KSO17/GPIO49 GPIO FSTCHG/GPIO50
89 FSTCHG <31>
90 BATT_BLUE_LED# place close to PU2
BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# <22>

2
EC_SMB_CK2 EC_SMB_DA2 91
@ @ EC_SMB_CK1 77
CAPS_LED#/GPIO53
92 BATT_AMB_LED# FSTCHG Project ID
1 1
Battery<29> EC_SMB_CK1 EC_SMB_DA1 78
EC_SMB_CK1/SCL0/GPIO44
EC_SMB_DA1/SDA0/GPIO45
BATT_LOW_LED#/GPIO54
PWR_LED#/GPIO55
93 PWR_LED# BATT_AMB_LED# <22>
PWR_LED# <22> 1 Ra R398 @
C436 C437 <29> EC_SMB_DA1 EC_SMB_CK2 SYSON 0_0402_5%
<4> EC_SMB_CK2 79 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 95 SYSON <28,33>
EC_SMB_DA2 80 121 VR_ON C477
100P_0402_50V8J 100P_0402_50V8J
APU VR_ON <36> C400

1
2 2 @ <4> EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 EC_ACIN AD_PID0
127 100P_0402_50V8J
APU_ALERT#_EC AC_IN/GPIO59 VR_ON 2
C407 1 2 100P_0402_50V8J SM Bus 2 1

1
1
10/05 Add 100p(C407) on APU_ALERT#_EC SLP_S3# 6 100 EC_RSMRST# Reserve C477 for FSTCHG
B <13> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <13> B
SLP_S5# 14 101 EC_LID_OUT# 100P_0402_50V8J Tock 2011/01/07 Rb R399 @ C393 @
<13> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <13>
EC_SMI# 15 102 EC_ON 8.2K_0402_5% 0.1U_0402_16V4Z
EC_XCLK1 EC_XCLK0 <13> EC_SMI# APU_ALERT#_EC EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_PME# EC_ON <23> VGATE 2
<4> APU_ALERT#_EC 16 103

2
GPIO0A EC_SWI#/GPXIOA06 ICH_POK_EC
17 GPIO0B ICH_PWROK/GPXIOA07 104 1
1 1 8/24 Delete Net FAN_SPEED1 18 GPIO 105 BKOFF# @
GPIO0C BKOFF#/GPXIOA08 WL_OFF# BKOFF# <9>
C354 C355 19
SUS_PWR_DN_ACK/GPIO0D GPO RF_OFF#/GPXIOA09 106 WL_OFF# <21>
C423
1

INVT_PWM 25 107 WXMIT_OFF# 100P_0402_50V8J


<9> INVT_PWM FAN_SPEED1 INVT_PWM/PWM2/GPIO11 GPXIOA10 WXMIT_OFF# <20> 2
15P_0402_50V8J 15P_0402_50V8J 28 108
OSC

OSC

2 2 <27> FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB0/GPIO14 GPXIOA11


<20,21> BT_ON# 29 Reserve C423 for VGATE
EC_TX_P80_DATA FANFB1/GPIO15
<21> EC_TX_P80_DATA 30 EC_TX/GPIO16 Michael 2010/11/18
EC_RX_P80_CLK 31 110 VGATE
<21> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 VGATE <13,36>
ON/OFF# APU_ENBKL
NC

NC

<23> ON/OFF# PWR_SUSP_LED#


32
ON_OFF/GPIO18 ENBKL/GPXIOD02
112
EAPD APU_ENBKL <4> PME Follow PAWGC
<22> PWR_SUSP_LED# 34 SUSP_LED#/GPIO19 EAPD/GPXIOD03 114 EAPD <17>
36 GPI 115 EC_PROCHOT# 1 +3VALW
EC_PROCHOT# <4>
2

NUM_LED#/GPIO1A EC_THERM#/GPXIOD04

2
116 SUSP# C447
SUSP#/GPXIOD05 PBTN_OUT# SUSP# <28,33,34>
X1 10/11 Change C354,C355, X1 from @ to mount 117 R281 100P_0402_50V8J
PBTN_OUT#/GPXIOD06 PBTN_OUT# <13>

2
32.768KHZ_12.5PF_Q13MC14610002 118 WWAN_WAKEUP# 100K_0402_5%
R282 EC_XCLK1 EC_PME#/GPXIOD07 WWAN_WAKEUP# <20> 2 R322
122
EC_XCLK0 XCLK1 V18R
<12> SUSCLK 1 @ 2 123 124 Reserve C447 for APU_ENBK 10K_0402_5%

1
0_0402_5% XCLK0 V18R
8/23 Change R282 from mount to @ 1 Tock 2011/01/07
AGND

2 R358 1 C356
GND
GND
GND
GND
GND

1
X1 C354 C355 from @ to mount @
8/26 Change R282 from @ to mount 100K_0402_5% 4.7U_0603_6.3V6K
KB930QF-A1_LQFP128_14X14 2
10/27 Change C356 from 10V_0805 to 6.3V_0603
11
24
35
94
113

69

X1 C354 C355 from mount @ 8/31 Add 100k(R358) pull-down on SUSCLK 20mil <18> LAN_WAKE# 1 @ 2 EC_PME#
SA00003QQ10 L30 R323 0_0402_5%
ECAGND 2 1
Board ID 10/11 Change R282 R358 from mount to @ FBMA-L11-160808-800LMT_0603 1 2
+3VALW R324 @ 0_0402_5%
Analog Board ID definition, EC_PROCHOT# LAN_WAKE# BKOFF#
Please see page 3.

D
SLP_S3# SLP_S5# ON/OFF# 1 1 1 3 1
<13> PCI_PME#
2

A A
R283 change R284 from 0 ohm to 8.2K , 1 1 1 C430 C471 C472 Q29
Ra 100K_0402_5% @ @ 100P_0402_50V8J SSM3K7002FU_SC70-3

G
2011/01/28 Tock 100P_0402_50V8J 100P_0402_50V8J

2
C424 C425 C428 2 2 2 +3VALW @
change R283 from 0 ohm to 100K , 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
1

AD_BID0 2 2 2 Reserve C430 for EC_PROCHOT# Reserve C471,C472 for LAN_WAKE# , BKOFF#
2011/02/11 Tock
Michael 2010/11/18 Tock 2011/01/07
2

1 Reserve C428 for ON/OFF#


C357 Reserve C424, C425, Michael 2010/11/18
Rb R284
8.2K_0402_5%
0.1U_0402_16V4Z for SLP_S3#, SLP_S5#
Security Classification Compal Secret Data Compal Electronics, Inc.
2 Michael 2010/11/18 Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title
EC ENE-KB930
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 26 of 37
5 4 3 2 1
+3VALW

9/2 Change EC_SPICLK to EC_SPICLK_R


R201 1 2 SPI_WP#
2MB SPI ROM
3.3K_0402_5%
Share ROM. 8/31 Remove EC ROM , Add SPI ROM EC_SPICLK_R
R202 1 2SPI_HOLD#
3.3K_0402_5%

1
W=20mil R200
33_0402_5%
+3VALW @

2
C212
1 2
R203 C211
0_0402_5% U7 0.1U_0402_16V4Z 22P_0402_50V8J
EC_SPICS#/FSEL# 1 2 EC_SPICS#/FSEL#_R 1 8 @
<26> EC_SPICS#/FSEL# EC_SI_SPI_SO EC_SPI_SO CS# VCC SPI_HOLD#
1 2 2 7 0_0402_5% R206
<26> EC_SI_SPI_SO DO(IO1) HOLD#(IO3)
SPI_WP# 3 6 EC_SPICLK_R 1 2 EC_SPICLK
33_0402_5% WP#(IO2) CLK EC_SPI_SI EC_SPICLK <26>
4 5 1 2 EC_SO_SPI_SI EC_SO_SPI_SI <26>
R204 GND DI(IO0)
W25Q16BVSSIG_SO8 33_0402_5% R205 EMI
SA00003FO00
Layout Note: Layout Note:
R204 close to U7 R203 R205 R206 close to U12

Delete U17,C382,C386,R355,D20,C383,C384,C385 Add U17,C382,C386,R355,D20,C383,C384,C385


for Fan control IC circuit for Fan control IC circuit
2010/12/15 Tock 2011/01/19 Tock

+5VS
FAN Conn.

2
D20
@ DAN217_SC59
+5VS
C382 2.2U_0603_10V6K
1 2 @

1
1 2 C383

U17 4.7U_0603_6.3V6K
1 8 @
H1 H2 H3 EN GND
2 VIN GND 7 1 2 C384
H_3P2 H_3P2 H_3P2 9/15 Update the Screw Hole +VCC_FAN1 3 6
EN_FAN1_R VOUT GND 4.7U_0603_6.3V6K
3P2 x 3 (APU) <26> EN_FAN1 1 2 4 VSET GND 5
9/20 Add H20 (H_3P4X3P2N) R355 330_0402_5%
APL5607KI-TRG_SO8
1

10/07 Change H13 from GND to LANGND @


1 1 2 C385
+3VS
@ @ @ 10/07 Change H13 from LANGND to GND C386 40mil
0.01U_0402_16V7K 1000P_0402_50V7K
2 +VCC_FAN1

1
H4 R290
H_3P0N 10K_0402_5%
40mil JFAN1
3P0N x 1

2
+5VS 1 2 +VCC_FAN1 +VCC_FAN1 1
1

R289 0_0603_5% 1
<26> FAN_SPEED1 2 2
@ 1 3
C360 3
@ @ 4
10U_0805_10V6K GND
5
2 GND
H8 H9 Update the Screw Hole ACES_50273-0030N-001
H_2P3 H_2P3
2010/12/16 Tock CONN@
2P3 x 2
Update the Screw Hole
1

2010/12/22 Tock
@ @ 8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition
8/24 Delete R290
FM1 FM2 FM3 FM4
H6 H7 H10 H11
8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition
H_2P5 H_2P5 H_2P5 H_2P5 @ @ @ @ FIDUCIAL_C40M80 8/25 Add R290 10k pull-up tp +3VS
1

2P5 x 4
8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit)
1

@ @ @ @ change JFAN1 footprint from ACES_85205-04001_4P to ACES_50273-0030N-001_3P , 2011/01/28 Tock ,

H12 H15
delete EC_FAN_PWM and R356,R357 , 2011/01/28 Tock ,
H_0P6X2P3 H_0P6X2P3

0P6X2P3 x 2
1

@ @

H13 H14
H_3P0X4P0N H_3P0X4P0N
3P0X4P0N x 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title


@ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw / EC ROM /FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 27 of 37
A B C D E

+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS 10/27 Change R291 Q18 from @ to mount
U14
Remove C365 10U U15
Remove C368 10U
Remove C364 10U +5VALW +5VS Michael 2010/11/18 Remove C367 10U +3VALW +3VS Michael 2010/11/18 Remove C361 10U +1.5V Q15 +1.5VS Remove C362 10U
Michael 2010/11/18 AP4800BGM-HF_SO-8 Michael 2010/11/18 AP4800BGM-HF_SO-8 Michael 2010/11/18 AO3413L_SOT23-3 Michael 2010/11/18
8 1 8 1 3 1

D
7 2 1 7 2 1 1

1
6 3 6 3

G
5 C366 5 C369 C363

2
1U_0603_10V6K R292 1U_0603_10V6K R293 1U_0603_10V6K R291
1 2 2 2 1
470_0603_5% 470_0603_5% 470_0603_5%

4
@ @

1 2

1 2

2
+VSB +VSB +5VALW
D D
SB548000210 SB548000210 SB000006R10

1
D
2 SUSP 2 SUSP
1

1
G G 2 SUSP
R294 S Q16 @ R295 S Q17 @ R296 Q18 G

3
82K_0402_5% SSM3K7002FU_SC70-3 120K_0402_5% SSM3K7002FU_SC70-3 200K_0402_5% SSM3K7002FU_SC70-3 S

3
R297
2

2
+5VS_GATE 1 2 +5VS_GATE_R +3VS_GATE 1 R350 2+3VS_GATE_R change R295 from 200K to 120K +1.5VS_GATE 2 R298 1 +1.5VS_GATE_R
1 1 Tock 2011/01/03 1 10/29 Change R298 from 0 ohm to 100k
1

1
D 20K_0402_5% D 0_0402_5% D 100K_0402_5%
SUSP 2 SSM3K7002FU_SC70-3 C370 SUSP 2 C371 SUSP# 2 C373
G Q19 0.1U_0603_25V7K G 0.1U_0603_25V7K G 0.1U_0402_16V4Z
2 Q20 SSM3K7002FU_SC70-3 2 Q21 S SSM3K7002FU_SC70-3 2
S S 9/27 Change Q21.2 from SUSP# to SUSP
3

3
9/27 Change R296.1 from +5VALW to +VSB 10/31 Change C373 from 0603_25V to 0402_16V
+1.1ALW to +1.1VS 9/27 Change Q15 to U19(SB00000GV00)
2011/02/11 Change Q15 to SB000006R10
Remove C374 10U +1.1VALW U16 +1.1VS Remove C375 10U
AP4800BGM-HF_SO-8 10/12 Change R402 from mount to @ 9/28 Change Q21.2 from SUSP to SUSP# +5VALW
Michael 2010/11/18 Michael 2010/11/18
+5VALW
10/12 Change R400 R403 from @ to mount +5VALW 9/28 Change R296.1 from +VSB to +5VALW
8 1

1
7 2 1 9/28 Change U19 to Q15(SB934130020)

1
2 6 3 2
5 C376 9/28 Remove C372 R302 @

1
1U_0603_10V6K R300 100K_0402_5% R303
2 470_0603_5% 100K_0402_5%
4

2
@ +1.1VS_ON# 1 @ 2 SUSP R400 SUSP
<35> SUSP
2

2
100K_0402_5% SYSON#
SB548000210 R402 0_0402_5% 10/04 Add 100p(C403) on SUSP

2
1

+VSB D
2 +1.1VS_ON# 1 2 VLDT_EN#
VLDT_EN# <26> 10/06 Remove C403
G
1

1
SSM3K7002FU_SC70-3 S Q22 @ R403 0_0402_5% D @ D
3

C404 1 2 100P_0402_50V8J 2 SYSON 2


<26,33,34> SUSP# <26,33> SYSON
R304 G G

1
47K_0402_5% 10/04 Add 100p(C404) on VLDT_EN# Q30 S Q31 S

3
C408 1 2 100P_0402_50V8J R404 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
2

+1.1VS_GATE 2 R351 1 +1.1VS_GATE_R 10/06 Change C404 on +1.1VS_ON# 10K_0402_5%


1
1

D 0_0402_5%

2
+1.1VS_ON# 2 C378 10/27 Add C408(100P) on SUSP# close to PR70
G 0.1U_0603_25V7K
Q24 2
S 9/27 Change R302 from @ to mount, remove R301
3

SSM3K7002FU_SC70-3
8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3)
10/31 Change C361 C362 from mount to @
10/12 Change R294 to 100k 8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6)
9/27 Change R304.1 from +5VALW to +VSB
3 10/12 Change R295, R296 to 200k 3
8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8)
10/12 Change R304 to 47k
Change Q25 package to SOT363-6 Change Q27 package to SOT363-6
Remove Q26 Remove Q28 10/12 Change R294 to 82k 8/23 Remove R305 R299 Add R350 R351 for Sequence
Michael 2010/11/18 Michael 2010/11/18
10/12 Change R297 to 20k
8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3)
+1.8VS +1.05VS +1.5V +0.75VS
8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part
1

1
1

R306 R308 R309


8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part
470_0603_5% 470_0603_5% R307 470_0603_5%
@ @ 470_0603_5% @ 8/26 Change U14, U15, U16 to SB00000GV00 Standard Part
2

@
2

9/3 Delete C377(DIS@)


6

@ @ @ Q27B @
Q25A Q25B Q27A

SUSP SUSP SYSON# SUSP


9/23 Reserve R400~403, Q36 for VLDT_EN
2 5 2 5

2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 9/25 Remove R401 Q36 on VLDT_EN


1

2N7002DW-T/R7_SOT363-6

4 9/25 Add 10k(R404) PD on SUSP# 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 28 of 37
A B C D E
A B C D

1
VMB 1

PL2
PJP2 HCB2012KF-121T50_0805
VMB
1 1
2
1 2 BATT+ PH1 under CPU botten side :
2 B/I
3 3
4 TS
CPU thermal protection at 92 degree C
4 EC_SMCA
5 5 Recovery at 72 degree C

1
6 EC_SMDA PC8
6 PC7

1
7 7 0.01U_0402_25V7K
PR6 1000P_0402_50V7K
8

2
8 1K_0402_1%
GND 9
GND 10 VL
@

2
SUYIN_200275MR008G15QZR

1
PC9 PR7 PR8
0.1U_0402_10V7K VL 10K_0402_1% 22.1K_0402_1%

2
PR9

2
2
6.49K_0402_1% PU1
2 1 @ PR10 1 8
+3VALW 100K_0402_1% VCC TMSNS1
2 GND RHYST1 7 2 1

1
1
100_0402_1%

1K_0402_1%

<31> MAINPW ON 3 6 PR11


OT1 TMSNS2
2

PR14
100_0402_1%

15K_0402_1%
PR13

2 2
4 OT2 RHYST2 5 2 1
PR12

G718TM1U_SOT23-8 @ PR15
2

47K_0402_1%
1

BATT_TEMP <25>

1
PH2 @ PH1
EC_SMB_CK1 <25>
100K_0402_1%_NCP15W F104F03RC 100K_0402_1%_NCP15W F104F03RC

2
EC_SMB_DA1 <25>

PQ2
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
3 3
0.22U_0603_25V7K
100K_0402_1%
1

PC10
1

1
PR16

PC11 @
VL @ 0.1U_0603_25V7K
2

2
2

PR17
2

1 2
PR18 22K_0402_1%
100K_0402_1%
1

D
PR19
1 2 2 PQ3
<31,33> POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

PC12
.1U_0402_16V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 29 of 37
A B C D
A B C D

VIN

2
PD1
RLS4148_LL34-2

1
1 1

1
VIN PR1 PR2
PL1 PQ1 68_1206_5% 68_1206_5%
HCB2012KF-121T50_0805
DC_IN_S1 TP0610K-T1-E3_SOT23-3
1 2

2
CONN@ PD2
ACES 88266-04001 2 1 N1 3 1
BATT+ VS

1000P_0402_50V7K

1000P_0402_50V7K
<BOM Structure>

100P_0402_50V8J
RLS4148_LL34-2

100P_0402_50V8J

1
1

1
1

1
2 PR3 PC6

PC4

1
PC1

PC2

PC3
2
5 GND 3 3 100K_0402_1% 0.22U_0603_25V7K PC5
6 GND 4 4

2
2

2
0.1U_0603_25V7K

2
PJP1 PR4
<22> 51_ON# 1 2
SP02000GC00 22K_0402_1%

PR5
2
0_0603_5% 2

1 2 +3VLP
+CHGRTC

@ PJ1 @ PJ2
+3VALW P 2 2 1 1 +3VALW +1.1VALW P 2 2 1 1 +1.1VALW
1

1
1

JUMP_43X118 JUMP_43X118
PC241 PC242
2

@ PC248 .1U_0402_16V7K @ PC254 .1U_0402_16V7K


2

3 3

.1U_0402_16V7K .1U_0402_16V7K

@ PJ4
@ PJ3 2 1
+1.05VSP 2 1 +1.05VS
1

+5VALW P 2 2 1 1 +5VALW
1

JUMP_43X118
1

JUMP_43X118 PC244
2

PC243 @ PC255 .1U_0402_16V7K


2

@ PC252 .1U_0402_16V7K .1U_0402_16V7K


2

.1U_0402_16V7K

@ PJ5 @ PJ6
+VSBP 2 2 1 1 +VSB +0.75VSP 2 2 1 1 +0.75VS
1

1
1

JUMP_43X39 JUMP_43X79
PC245 PC246
2

@ PC253 .1U_0402_16V7K @ PC256 .1U_0402_16V7K


2

.1U_0402_16V7K .1U_0402_16V7K

@ PJ7
+1.8VSP 2 2 1 1 +1.8VS
1

JUMP_43X118
PC247
2

@ PC257 .1U_0402_16V7K
2

.1U_0402_16V7K

4 @ PJ9 4

+1.5VP 2 2 1 1 +1.5V
1

JUMP_43X118
PC258 PC249
.1U_0402_16V7K .1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/VIN DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 30 of 37
A B C D
5 4 3 2 1

Iada=0~2.105A(40W/19V=2.105A)
PL18
CP = 85%*Iada ; CP = 1.789A 1.2UH_1231AS-H-1R2N=P3_2.9A_30%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
ADP_I = 19.9*Iadapter*Rsense 2 1

1
PC237

PC250

PC251
PQ5
P2 AON7403L_DFN8-5 P3 PR20 B+ @ PL3
CHG_B+ AON7403L_DFN8-5

2
PD3 PQ4 0.05_1206_1% @ @ @ HCB2012KF-121T50_0805
VIN 2 1 1 1 4 2 1 1
2 5 2 5
SX34_SMA2 3 2 3 CSIN 3

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
CSIP

4
D D

1
PC14

PC15

PC16
VIN

2
PC13 PR21
1 2
VIN

2
1

5600P_0402_25V7K
47K_0402_1%

1
1

2
6251VDD
0.1U_0603_25V7K
PR22

1
200K_0402_1% PR23 PR25

2
PC17
ACSETIN PR24
200K_0402_1% 10K_0402_1%
2

191K_0402_1%

2.2U_0603_6.3V6K
PD4

1 1
RB751V-40_SOD323-2

1000P_0402_25V8J

2
1
PC18
ACSETIN

1 1
3

1
PR27

1
PC19
100K_0402_1%
PR26 PR28
2 PQ7 2 1 2BATT_ON
PR29 10_1206_5% 14.3K_0402_1% DTC115EUA_SC70-3

2
10K_0402_1%

2
<25> FSTCHG 2 1 PU2
1

1
PC20 @

3
PQ6 1 24 DCIN 2 1 PC21
1

VDD DCIN
1

1
DTA144EUA_SC70-3 2200P_0402_50V7K

2
0.1U_0603_25V7K
PR30 PR31
BATT_ON 2 2 23 ACPRN
PQ8 150K_0402_1% 100K_0402_1% ACSET ACPRN
DTC115EUA_SC70-3 PR32 20_0402_5%
2

2
6251_EN 3 22 1 2 CSON PQ10
6

D EN CSON

2
PC22 AON7408L_DFN8-5
3

5
2 0.047U_0402_16V7K
G 4 21 1 2 CSOP

1
CELLS CSOP
PR33 20_0402_5%
S PQ9A PC23
1

C
DMN66D0LDW -7_SOT363-6 1 2 5 20 PR34 2 1 20_0402_5%
C
ICOMP CSIN

2
PC25 4
PQ9B PC24 PR35 6800P_0402_25V7K
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 19 1 2

1
VCOMP CSIP PL4
3

D
10K_0402_1% PR36 2_0402_5% PR38
5 0.01U_0402_25V7K PR37 10UH_VMPI0703AR-100M-Z01_3.5A_20% BATT+

3
2
1
G
<25> ADP_I 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
47K_0402_1%

1
5
S PC26 2 3
4

PR40 1 2 6251VREF 8 17 DH_CHG


47K_0402_1% PR39 VREF UGATE @ PR41

AON7408L_DFN8-5
0.05_1206_1%
PACIN 62K_0402_1% PC27 4.7_1206_5%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1 2 .1U_0402_16V7K PR42
<25> IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1

2
CHLIM BOOT

1
0_0603_5% 4
1

1
0.1U_0603_25V7K

PQ11

PC29

PC30

PC205

PC204
PR43 PD5

1
0.01U_0402_25V7K

6251VREF 1 2 6251ACLIM 10 15 6251VDDP @ PC28


ACLIM VDDP
1

PQ12 SD103AW S SOD323-2

2
4.7K_0402_1%
1

680P_0603_50V7K
DTC115EUA_SC70-3 2 6251VDD @ @
PC31

2
3
2
1
ACOFF 2 PR44 11 14 DL_CHG
<25> ACOFF VADJ LGATE PR45 4.7_0603_5%

2
100K_0402_1%
2

PC32

PR46

20K_0402_1%
2

12 13 4.7U_0603_6.3V6M

1
GND PGND
3

2
ISL6251AHAZ-TR5283_QSOP24

B B
PR47
<25> CHGVADJ 1 2
15.4K_0402_1%
2

Charging Voltage PR48 Vth,rise(typical) = ((191K/14.3K)+1)*1.26


BATT Type CV mode CC=0.25~3.52A 31.6K_0402_1% 6251VDD
= 18.089V
(0x15)
1

IREF=0.7224*Icharge Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K


= 17.44V
Normal 3S LI-ON Cells PR51
12600mV 12.60V IREF=0.43V~3.24V
1

10K_0402_1%
PR49 1 2 ACIN <25>
47K_0402_1% PR50
Ki 10K_0402_1%
Vchlim=Iref*(PR39/(PR39+PR44))
2

PACIN
=Iref*(100K/(80.6K+100K))
1

=Iref*0.617
Ichanrge=(165mV/PR38)*(Vchlim/3.3V) PQ13
=(165m/50m)*(1/3.3V)*Iref*0.617 DTC115EUA_SC70-3
1

=0.617*Iref ACPRN 2 PR52


Iref=1.62*Ichanrge =>Ki=1.62
14.3K_0402_1%
2
3

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
A A
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
Security Classification Compal Secret Data Compal Electronics, Inc.
A=Vref*(R/(R+514K))=0.052 Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title
Kv=9.451
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 31 of 37
5 4 3 2 1
5 4 3 2 1

2VREF

D D

1
PC33
1U_0402_6.3V6K

2
+3VALW Vo= (2*13.7K/20K)+2=3.37V +5VALW Vo= (2*30K/19.1K)+2=5.141V

PR53 PR54
13.7K_0402_1% 30K_0402_1%
1 2 1 2

PR55 PR56
B++ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++
PL5
HCB2012KF-121T50_0805

ENTRIP1
ENTRIP2
B+ 1 2 +3VLP PR57 PR58
130K_0402_1% 143K_0402_1%
1 2 1 2
2200P_0402_50V7K

2200P_0402_50V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PQ14

PC39

PC40

PC37
PC240
1

AON7408L_DFN8-5
PC35

PC36
PC239

4.7U_0603_6.3V6K
5

1
PU3 PQ15

2
1

5
AON7408L_DFN8-5

PC38

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
2

C C
25

2
P PAD
4
7 VO2 VO1 24 POK <29,33> 4

PC41 8 VREG3 PGOOD 23 PC42


PR59 PR60
1
2
3

0.1U_0603_25V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 0.1U_0603_25V7K

3
2
1
BOOT2 BOOT1
PL6 0_0603_5% 0_0603_5% PL7
UG_3V 10 21 UG_5V
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% UGATE2 UGATE1 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 PHASE2 PHASE1 20 1 2
5

5
1

1
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR61 @

SKIPSEL
PR62 @

VREG5
4.7_1206_5% 4.7_1206_5%

220U_6.3V_M
1 1

GND

VIN

NC
EN
4 4
2

2
+ +

PC44
PC43
220U_6.3V_M PR63 RT8205EGQW _W QFN24_4X4 PQ17

13

14

15

16

17

18
1

1
PC45 @ 499K_0402_1% FDMC7692S_MLP8-5
2 PC46 @ 2
1 2
B++
1
2
3

3
2
1
680P_0603_50V7K PQ16 680P_0603_50V7K
2

2
FDMC7692S_MLP8-5

1
100K_0402_5%
1
VL

PR64
PC47

1
1U_0402_6.3V6K
PC48
B 2 B
4.7U_0603_6.3V6K

2
ENTRIP1 ENTRIP2 B++

2
D D
6

2 5
PQ18A G G PQ18B

1
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 PC49
S S
2VREF
1

0.1U_0603_25V7K

2
PR65
VL 2 1 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
100K_0402_1% (2)SMPS2=375KHZ (+3VALWP)
1

<29> MAINPW ON

PR66 +3.3VALWP +5VALWP


VS 1 2 2
Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A
100K_0402_1%
f=375KHz, L=4.7UH,Rentrip2=130K ohm f=300KHz, L=4.7UH,Rentrip1=143K ohm
0.1U_0402_10V7K
42.2K_0402_1%

PQ19
1

Rdson=14.5~17.9m ohm (IRFH3707) Rdson=14.5~17.9m ohm (IRFH3707)


1

DTC115EUA_SC70-3
PR67

PC50

1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A


Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V
2

Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A
2

A A
Iocp=7.415A~10.613A (7.415A>7.224A -> OK) Iocp=8.569~12.065A (8.569>8.4 -> OK)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 32 of 37
5 4 3 2 1
A B C D

PU4
SY8033BDBC_DFN10_3X3 PL8

4
@ PJ10 1UH_FDV0630-1R0M-P3_10.3A_20%
+5VALW 2 1 10 2 LX_1.8VS 2 1 +1.8VSP

PG
2 1 PVIN LX
1 1

JUMP_43X39

68P_0402_50V8J
9 PVIN LX 3

1
1

1
4.7_0603_5%

PC52
PC51 8 SVIN

PR68
22U_0805_6.3VAM PR69
6 FB=0.6Volt 20.5K_0402_1% <Vo=1.8V> VFB=0.6V

22U_0805_6.3VAM

22U_0805_6.3VAM
2

2
FB
5
Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V

2
EN

1
NC

NC
TP

PC54
PC53
2
FB_1.8VS
Ipeak=2A, Imax=1.4A

11

2
PR70

680P_0603_50V7K
<25,27,33> SUSP# 1 2 EN_1.8VS

1
PC55
200K_0402_1%
PR71

1
@

2
10K_0402_1%

1
PR72 PC56

2
499K_0402_1% 0.22U_0402_10V6K

2
2
2 2

PL9
HCB2012KF-121T50_0805
1 2 B+

2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
PQ20

5
AON7408L_DFN8-5

1
PC61

PC62
PC60
PC59

2
PR74
255K_0402_1%
4
1 2
PR75
<25,27> SYSON 1 2 PR77
BST_1.5V 1 2
0_0402_5%
1

3
2
1
0_0603_5%
1

PR76 PL10
15

14
PC63 @
1

30K_0402_5% PU5 PC64 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%


.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP
EN_SKIP

TP

BST
2
2

2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
3 12 LX_1.5V
OUT LX

1
PR78 PR73
+5VALW 1 2 4 VCC VFB=0.75V ILIM 11 1 2 +5VALW
@ PR79 1
15K_0402_1% 4.7_1206_5%
100_0603_5% + PC65
5 FB VDD 10
330U_2.5V_M

2
1

PC58 6 9 DL_1.5V 4
3
PGOOD DL 3
AGND

PGND

2
4.7U_0603_6.3V6K

2
PC67 PQ21
2

1
4.7U_0603_6.3V6K FDMC7692S_MLP8-5 @ PC66
G5603RU1U_TQFN14_3P5X3P5 680P_0603_50V7K
7

3
2
1

2
PR80
1 2
5.36K_0402_1%
1

PR81
5.1K_0402_1%
<Vo=1.5V> VFB=0.75V
2

V=0.75*(1+5.36K/5.1K)=1.538V
G5603 RT8209B TPS51117 RT8209M

Cout ESR=25m ohm


Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) OCP setting 6.821A 7.235A 8.000A 8.178A
Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A

4
G5603 RT8209B TPS51117 RT8209M 4

Temperature
Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ ℃
Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title
Vtrip_max (SPEC) 200mV 200mV 200mV 200mV 1.8VSP/1.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 33 of 37
A B C D
A B C D

PL11
HCB2012KF-121T50_0805
1.1VALW _B+ 2 1 B+

2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC68

PC69

PC70

PC71
<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.99K/10K)=1.124V

2
Cout ESR=25m ohm
PR82
1

255K_0402_1% 4
Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) 1

1 2 Ipeak=4.02A, Imax=2.814A, Iocp > 4.824A


PR83 PR85
0_0402_5% 0_0603_5%
1 2 1 2 PQ22
<29,31> POK

3
2
1
AON7408L_DFN8-5

1
BST_1.1V ALW

1
PR84 PC72 PL12 G5603 RT8209B TPS51117 RT8209M

15

14
PC73

1
30K_0402_5% .1U_0402_16V7K PU6 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
@ @ 1 2 1 2

EN_SKIP

TP

BST
+1.1VALW P

2
2 2 13 DH_1.1VALW 0.1U_0603_25V7K OCP setting 5.799A 6.183A 6.845A 6.976A
TON DH

4.7_1206_5%
PR87 3 12 LX_1.1VALW
OUT LX

@ PR86
100_0603_1%

330U_2.5V_M
1

FDMC7692S_MLP8-5
+5VALW 1 2 4 VCC VFB=0.75V ILIM 11 1 2 +5VALW
+

PC74
PR88

2
PQ23
5 10 13K_0402_1%
FB VDD
1

1
DL_1.1VALW 2

680P_0603_50V7K
6 PGOOD DL 9 4

AGND

PGND
PC75

@ PC77
4.7U_0603_6.3V6K
2

2
PC76
G5603RU1U_TQFN14_3P5X3P5 4.7U_0603_6.3V6K

3
2
1
PR89
4.99K_0402_1%
1 2
2 2
1

PR90
10K_0402_1% PL13
HCB2012KF-121T50_0805
2

1.05VALW _B+ 2 1 B+

2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC78

PC79

PC80

PC81
5

2
PR91
255K_0402_1% 4
1 2
PR92 PR93
200K_0402_1% 0_0603_5%
1 2 1 2 PQ24
<25,27,32> SUSP#

3
2
1
AON7408L_DFN8-5
1

BST_1.05V ALW
1

PR94 PC82 PL14


15

14

PC83
1

30K_0402_5% .1U_0402_16V7K PU7 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%


@ <BOM Structure> 1 2 1 2
EN_SKIP

TP

BST

+1.05VSP
2
2

2 13 DH_1.05VALW 0.1U_0603_25V7K
TON DH

4.7_1206_5%
3 3

PR95 3 12 LX_1.05VALW
OUT LX

@ PR97
100_0603_1%

330U_2.5V_M
1

FDMC7692S_MLP8-5
+5VALW 1 2 4 VCC VFB=0.75V ILIM 11 1 2 +5VALW <Vo=1.05V> VFB=0.75V
+

PC84
PR96
V=0.75*(1+3.57K/8.25K)=1.074V

2
PQ25
5 10 15K_0402_1%
FB VDD
1

1
DL_1.05VALW 2

680P_0603_50V7K
6 PGOOD DL 9 4
AGND

PGND

PC85 Cout ESR=25m ohm


1

@ PC87
4.7U_0603_6.3V6K
Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707)
2

2
PC86
G5603RU1U_TQFN14_3P5X3P5 4.7U_0603_6.3V6K Ipeak=5.5A, Imax=3.85A, Iocp > 6.6A
7

3
2
1
PR98
3.57K_0402_1% G5603 RT8209B TPS51117 RT8209M
1 2
1

PR99
OCP setting 6.524A 7.003A 7.768A 7.881A
8.25K_0402_1%
2

4 4

G5603 RT8209B TPS51117 RT8209M


Temperature
Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ ℃
Security Classification Compal Secret Data Compal Electronics, Inc.
Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VALWP/1.0VSP
Vtrip_max (SPEC) 200mV 200mV 200mV 200mV AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 34 of 37
A B C D
5 4 3 2 1

D D

+1.5V

1
PJ11

1
JUMP_43X118
@

22
C PU8 C
1
VIN NC
8 +3VALW
2 GND NC 7

1
PC89

1
PC88 3 6 1U_0402_6.3V6K
4.7U_0603_6.3V6K PR100 VREF VCNTL

2
1K_0402_1% 4 5
VOUT NC
9

2
TP
APL5336KAI-TRL_SOP8P8

.1U_0402_16V7K
PR101
+0.75VSP
1

1
300K_0402_5% D
1 2 2 PR102
<27> SUSP

1
PC90
G 1K_0402_1%
S PC91
3
1

PQ26 10U_0603_6.3V6M

2
PC92 SSM3K7002FU_SC70-3
.1U_0402_16V7K
2

For shortage changed

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 35 of 37
5 4 3 2 1
A B C D E

PL15
CPU_B+ HCB2012KF-121T50_0805

PC93 2 1 B+
33P_0402_50V8J

2200P_0402_50V7K
4.7U_0805_25V6-K

0.1U_0603_25V7K

68U_25V_M_R0.44
4.7U_0805_25V6-K
2 1 PQ27

5
AON7408L_DFN8-5 1

1
PC95

PC97

PC98

PC99
2 1 2 1 +

PC96
PR103 PC94

2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 @ 2
PR104
1 2_0603_5% PC100 1
1 2 1000P_0402_50V7K PL16
+5VALW 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
2 1

3
2
1
PHASE_NB 1 2 +APU_CORE_NB
PR106 PR105

1
PC101 22K_0402_1% 2.2_0603_1%
BOOT_NB @PR107

220U_D2_2VY_R15M
0.1U_0603_16V7K 2 1 1 2 1 2
PR110 PR108 4.7_1206_5% 1

2
0_0402_5% 10_0402_5% PC102

PC103
2 1 1 2 +APU_CORE_NB 0.22U_0603_10V7K +

1 2
@ PC121 LGATE_NB 4
1 2 100P_0402_50V8J @ PC104
CPU_B+ 2
2 1 APU_VDDNB_RUN_FB_H <4> 680P_0603_50V7K
PR109

2
2_0603_5% @ PC122

3
2
1
+5VS +3VS 2 1 APU_VDDNB_RUN_FB_L <4>

1
PC105 PR139 PQ28
0.1U_0603_25V7K 100P_0402_50V8J 10_0402_5% FDMC7692S_MLP8-5
2 1 1 2

2
PR111 CPU_B+
0_0402_5% PR112
1

1
+3VS 2 1 PHASE_NB
PR113 @ PR114 17.8K_0402_1% PQ29

2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0_0402_5% 105K_0402_1% LGATE_NB AON7408L_DFN8-5

5
PHASE_NB
2

2
1

1
PC106

PC107

PC108

PC109

PC110
@ UGATE_NB
PR115 PR116

2
105K_0402_1% 10K_0402_1% UGATE0 4
1

48

47

46

45

44

43

42

41

40

39

38

37
2

@ PR117 PU9
2 105K_0402_1% PHASE0 2

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
VIN

VCC
<12,25> VGATE PR118 PL17

3
2
1
2.2_0603_1% 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
2

<12> FCH_PWRGD 1 2 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +APU_CORE


@ PR119 100K_0402_5% OFS/VFIXEN BOOT_NB
1 2 2 35 BOOT0 PC111
<11> H_PWRGD_L PGOOD BOOT0

5
PR120 100K_0402_5% 0.22U_0603_10V7K

1
ISL6265_PWROK 3 34 UGATE0
<4> APU_SVD PWROK UGATE0

2
@ PC124
@PC124 @ PR122
2 1 2 1 4 33 PHASE0 4.7_1206_5% PR123
PR121 SVD PHASE0 7.5K_0402_1%
APU_SVC <4>
100P_0402_50V8J 0_0402_5%2 1 5 32 4

1 2
PR124 SVC PGND0 +5VALW
<25> VR_ON

1
100P_0402_50V8J

@ PR125 PR126 0_0402_5% 6 31 LGATE0 @PC112


@PC112 PC113
ENABLE LGATE0
1

90.9K_0402_1% 26.1K_0402_1% ISL6265CHRTZ-T_TQFN48_6X6 680P_0603_50V7K 2 1


PC123

2 1 2 1 7 30

3
2
1

2
RBIAS PVCC PQ30 0.1U_0603_16V7K
2

8 29 FDMC7692S_MLP8-5
OCSET LGATE1

1
PC114 2 1
9 28 1U_0603_16V6K
VDIFF0 PGND1 LGATE0 PR127

ISN0
ISP0
10 27 1.69K_0402_1%
FB0 PHASE1
11 26
COMP0 UGATE1
12 25
VW0 BOOT1
COMP1
VDIFF1
VSEN0

VSEN1
RTN0

RTN1
ISN0

ISN1
ISP0

VW1

ISP1
FB1

TP
VSEN1

13

14

15

16

17

18

19

20

21

22

23

24

49
3 ISP0 3
PR128 ISN0
2

VSEN1

10_0402_1%
ISN0
ISP0

+APU_CORE 1 2 PR129
0_0402_5%

PR130
1

0_0402_5%
2 1 VSEN0
<4> APU_VDD0_RUN_FB_H
2 1

@ PC119
@PC119
100P_0402_50V8J

2 1

<4> APU_VDD0_RUN_FB_L @ PC120


@PC120
PR131 100P_0402_50V8J
10_0402_1%
2 1 2 1 RTN0

0_0402_5%
PR132

DIFF_0 VW0

PR134 PC115 7.87K_0402_1% 6.49K_0402_1%


255_0402_1% 4700P_0402_25V7K PR133 PR140
2 1 2 1 2 1 COMP0 2 1 2 1 2 1
+3VS
PC116 PC117
4 100P_0402_50V8J 1000P_0402_50V7K 4

PR135 PR137
1K_0402_5% PR136 PC118 6.81K_0402_1%
2 1 2 1 2 1 2 1

54.9K_0402_1% 1200P_0402_50V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
1

@ PR138 Issued Date 2010/08/12 2012/08/12 Title


36.5K_0402_1%
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 36 of 37
A B C D E
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Add PC248 for +3VALWP PC252 for +5VALWP PC253 for +VSBP
D PC254 for +1.1VALWP PC255 for +1.05VSP PC256 for +0.75VSP D
Modify DCIN/VIN DECTOR power sequence 1 30 PC257 for +1.8VSP 20101228 EVT
1
Modify charger power sequence 1 31 delete PC234 20101228 EVT
2
Modify 3VALWP/5VALWP power sequence 1 32 delete PC34 20101228 EVT
3
Chang PD5 from SCS00000Z00 (RB751V-40_SOD323-2
Modify charger power sequence 1 31 20110104 EVT
4 to SCS00005I00 (SD103AWS SOD323-2)

Chang PD3 from SCS00001I80 ( B340A SMA ) to SCS00000W00 (SX34_SMA2)


Modify charger power sequence 1 31 20110106 EVT
5 Chang PQ4&PQ5 fromSB00000KI00(SI7121DN-T1-GE3 1P POWERPAK1212-8) to
SB00000KZ00(AON7403L_DFN8-5)
Chang PL6 &PL7 from SH00000F900(4.7UH_FDVE0630-H-4R7M=
Modify 3VALWP/5VALWP power sequence 1 32 P3_5.5A_20%) to SH00000MB00(4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%) 20110110 EVT
6
Chang PL10 from SH00000F800(2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%)
Modify 1.8VSP/1.5VP power sequence 1 33 to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) 20110110 EVT
7
Chang PL12 &PL14 from SH00000F800(2.2UH_FDVE0630-H-2R2M=
Modify 1.1VALWP/1.05VSP power sequence 1 34 P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) 20110110 EVT
C 8 C

Chang PL16 &PL17 from SH00000F800(2.2UH_FDVE0630-H-2R2M=


Modify CPU_CORE power sequence 1 36 P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) 20110110 EVT
9
Chang PR112 from SD034237280 (23.7k_0402_1%) to SD034178280 (17.8k_0402_1%)
Modify CPU_CORE power sequence 1 36 Chang PR123 from SD000002680 (6.98k_0402_1%) to SD034750180 (7.5k_0402_1%) 20110110 EVT
10 Chang PR127 from SD034187180 (1.87k_0402_1%) to SD00000JB80 (1.69k_0402_1%)

Modify 1.8VSP/1.5VP power sequence 2 33 add PC258 to +1.5V output capacitor (co-lay higt from 4.5 20110208 DVT
11 to 2.5) for thermal issue

Modify 1.1VALWP/1.05VSP power sequence 2 34 add PC259 to +1.1VALWP output capacitor (co-lay higt 20110208 DVT
12 from 4.5 to 2.5) for thermal issue

Modify 1.8VSP/1.5VP power sequence 3 33 delete co-lay PC258 for +1.5V output capacitor 20110225 PVT
13
Modify 1.1VALWP/1.05VSP power sequence 3 34 delete co-lay PC259 for +1.1VALW output capacitor 20110225 PVT
14
Modify charger power sequence 3 31 delete co-lay PJ32 20110226 PVT
15 modify PQ4 PQ5 footprint from AON7403L_DFN8-5 to SIS412DN-T1-GE3_POWERPAK8-5
B B

Modify charger power sequence 3 31 change charger IC from G5209 to ISL6251 20110226 PVT
16 change output choke from 8.2u to 10u

Modify DCIN/VIN DECTOR power sequence 3 30 Add PC258 for +1.5V jump by RF test 2010302 PVT
17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 17, 2011 Sheet 37 of 37
5 4 3 2 1
www.s-manuals.com

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