310616106137

EXPT. NO.
9 STUDY OF TMS320C6748
DATE:
AIM:
To study the features and architecture of the TMS320C6748

processor, and to learn to work with the kit and the IDE.
DESCRIPTION:
The TMS320C6748 fixed- and floating-point DSP is a low-power applications

processor based on a C674x DSP core. This DSP provides significantly lower
power than other members of the TMS320C6000™ platform of DSPs.
The device enables original-equipment manufacturers (OEMs) and original-

design manufacturers (ODMs) to quickly bring to market devices with robust
operating systems, rich user interfaces, and high processor performance
through the maximum flexibility of a fully integrated, mixed processor
solution.
This new board reduces design work with freely downloadable and duplicable
board schematics and design files. A wide variety of standard interfaces for
connectivity and storage enable you to easily bring audio, video and other
signals onto the board.
BASIC ARCHITECTURE:
The device DSP core uses a 2-level cache-based architecture. The level 1
program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data
cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program
cache (L2P) consists of a 256-KB memory space that is shared between
program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. Although the DSP L2 is accessible by
other hosts in the system, an additional 128KB of RAM shared memory is
available for use by other hosts without affecting DSP performance.
For security-enabled devices, TI’s Basic Secure Boot lets users protect
proprietary intellectual property and prevents external entities from
modifying user-developed algorithms. By starting from a hardware-based
“root-of-trust”, the secure boot flow ensures a known good starting point for
code execution. By default, the JTAG port is locked down to prevent
emulation and debug attacks; however, the JTAG port can be enabled during
the secure boot process during application development. The boot modules
are encrypted while sitting in external nonvolatile memory, such as flash or
EEPROM, and are decrypted and authenticated when loaded during secure
boot. Encryption and decryption protects customers’ IP and lets them
securely set up the system and begin device operation with known, trusted
code.
Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot
image validation. Basic Secure Boot also uses AES-128 for boot image
encryption. The secure boot flow employs a multilayer encryption scheme
which not only protects the boot process but offers the ability to securely
upgrade boot and application software code. A 128-bit device-specific cipher
key, known only to the device and generated using a NIST-800-22 certified
random number generator, is used to protect customer encryption keys.
When an update is needed, the customer uses the encryption keys to create
a new encrypted image. Then the device can acquire the image through an
external interface, such as Ethernet, and overwrite the existing code. For
more details on the supported security features or TI’s Basic Secure Boot,
refer to the TMS320C674x/OMAP-L1x Processor Security User’s Guide
(SPRUGQ9).
INTERFACES:
The peripheral set includes: a 10/100 Mbps Ethernet media access controller
(EMAC) with a management data input/output (MDIO) module; one USB2.0
OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one
multichannel audio serial port (McASP) with 16 serializers and FIFO buffers;
two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial
peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-
purpose timers each configurable (one configurable as a watchdog); a
configurable 16-bit host-port
interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins,
with each bank containing 16 pins with programmable interrupt and event
generation modes, multiplexed with other peripherals; three UART interfaces
(each with RTS and CTS); two enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP)
module peripherals which can be configured as 3 capture inputs or 3 APWM
outputs; two external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals; and
a higher speed DDR2/Mobile DDR controller.
The EMAC provides an efficient interface between the device and a network.
The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100
Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is
available for PHY configuration. The EMAC supports both MII and RMII
interfaces.
The SATA controller provides a high-speed interface to mass data storage

devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II
(3.0 Gbps).
The uPP provides a high-speed interface to many types of data converters,

FPGAs, or other parallel devices. The uPP supports programmable data
widths between 8- to 16-bits on both channels. Single-data rate and double-
data rate transfers are supported as well as START, ENABLE, and WAIT
signals to provide control for a variety of data converters.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral
devices and communicate with external processors.
The device has a complete set of development tools for the DSP. These tools
include C compilers, a DSP assembly optimizer to simplify programming and
scheduling, and a Windows® debugger interface for visibility into source
code execution.
The LCDK does not have an onboard emulator. An external emulator from TI,
such as the XDS200 or a third-party emulator will be required to start
development.
PACKAGE CONTENT:
C6748 LCDK
SPECIFICATIONS:
Processor
TI TMS320C6748 DSP Application Processor 456-MHz C674x

Fixed/Floating Point DSP
456-MHz ARM926EJ RISC CPU (OMAP-L138 only) On-Chip RTC
Memory
128 MB DDR2 SDRAM running at 150MHz 128 MB 16-bit wide
NAND FLASH
1 Micro SD/MMC Slot

Interfaces
One mini-USB Serial Port (on-board serial to USB)
One Fast Ethernet Port (10/100 Mbps) with status

LEDs One USB Host port (USB 1.1)
One mini-USB OTG port (USB

2.0) One SATA Port (3Gbps)
One VGA Port (15 pin D-SUB)
One LCD Port (Beagleboard XM

connectors) One Composite Video Input
(RCA Jack)
One Leopard Imaging Camera Sensor Input (36-pin ZIP

connector) Three AUDIO Ports (1 LINE IN & 1 LINE OUT & 1
MIC IN)
14-pin JTAG header (No onboard emulator; external emulator is required)
TMS320C6748 DETAILED SPECIFICATIONS:
• 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
• C674x Instruction Set Features
Superset of the C67x+ and C64x+

ISAs Up to 3648 MIPS and 2746
MFLOPS
Byte-Addressable (8, 16, 32, and 64 Bit

Data) 8-Bit Overflow Protection
Bit-Field Extract, Set, Clear

Normalization, Saturation, Bit-
Counting Compact 16-Bit
Instructions
• C674x Two-Level Cache Memory

Architecture 32KB of L1P Program
RAM/Cache
32KB of L1D Data RAM/Cache
256KB of L2 Unified Mapped

RAM/Cache Flexible RAM/Cache
Partition (L1 and L2)
∙ Enhanced Direct Memory Access Controller 3

(EDMA3): 2 Channel Controllers
3 Transfer Controllers
64 Independent DMA Channels

16 Quick DMA Channels
Programmable Transfer Burst Size
∙ TMS320C674x Floating-Point VLIW DSP Core
Load-Store Architecture with Nonaligned Support

64 General-Purpose Registers (32-Bit)
Six ALU (32- and 40-Bit) Functional Units

Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit)
and DP (IEEE Double Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per Clock, Four DP

Additions Every Two Clocks
Supports up to Two Floating-Point (SP or DP) Reciprocal

Approximation (RCPxP) and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per Cycle
Two Multiply Functional Units
Mixed-Precision IEEE Floating-Point Multiply Supported up to:
O 2 SP x SP → SP Per Clock
O 2 SP x SP → DP Every Two Clocks

O 2 SP x DP → DP Every Three
Clocks O 2 DP x DP → DP Every Four
Clocks
Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies,
four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per

Clock Cycle, and Complex Multiples
Instruction Packing Reduces Code Size

All Instructions Conditional
Hardware Support for Modulo Loop Operation Protected

Mode Operation
Exceptions Support for Error Detection and Program Redirection
• Software Support TI
DSP BIOS™
Chip Support Library and DSP Library
• 128KB of RAM Shared Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
• Two External Memory Interfaces:

EMIFA
NOR (8- or 16-Bit-Wide Data)

NAND (8- or 16-Bit-Wide Data)
16-Bit SDRAM with 128-MB Address Space
DDR2/Mobile DDR Memory Controller with one of the following:

16-Bit DDR2 SDRAM with 256-MB Address Space
16-Bit mDDR SDRAM with 256-MB Address Space
• Three Configurable 16550-Type UART Modules:

With Modem Control Signals
16-Byte FIFO
16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with

Secure Data I/O (SDIO) Interfaces
• Two Master and Slave Inter-Integrated Circuits (I2C Bus™)
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data
Bus for High Bandwidth
• Programmable Real-Time Unit Subsystem (PRUSS)

Two Independent Programmable Real-Time Unit (PRU) Cores
32-Bit Load-Store RISC Architecture
4KB of Instruction RAM Per Core

512 Bytes of Data RAM Per Core
PRUSS can be Disabled via Software to Save Power
Register 30 of Each PRU is Exported from the Subsystem in

Addition to the Normal R31 Output of the PRU Cores.
Standard Power-Management Mechanism

Clock Gating
Entire Subsystem Under a Single PSC Clock Gating Domain

Dedicated Interrupt Controller
Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• USB 2.0 OTG Port with Integrated PHY (USB0)

USB 2.0 High- and Full-Speed Client
USB 2.0 High-, Full-, and Low-Speed Host

End Point 0 (Control)
End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):

Two Clock Zones and 16 Serial Data Pins
Supports TDM, I2S, and Similar Formats
DIT-Capable
FIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):

Supports TDM, I2S, and Similar Formats
AC97 Audio Codec Interface
Telecom Interfaces (ST-Bus, H100) 128-
Channel TDM
FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):

IEEE 802.3 Compliant
MII Media-Independent Interface
RMII Reduced Media-Independent Interface

Management Data I/O (MDIO) Module
• Video Port Interface (VPIF):
Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and
12-Bit) Video Capture Channels
Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
• Universal Parallel Port (uPP):
High-Speed Parallel Interface to FPGAs and Data Converters

Data Width on Both Channels is 8- to 16-Bit Inclusive
Single-Data Rate or Dual-Data Rate Transfers
Supports Multiple Interfaces with START, ENABLE, and WAIT

Controls
• Serial ATA (SATA) Controller:
Supports SATA I (1.5 Gbps) and SATA II (3.0

Gbps) Supports All SATA Power-Management
Features
Hardware-Assisted Native Command Queueing (NCQ) for up to 32

Entries
Supports Port Multiplier and Command-Based Switching
• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit

Timers)
• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-

Bit General-Purpose Timers)
• Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
Dedicated 16-Bit Time-Base Counter with Period and Frequency

Control
6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-

Edge Asymmetric Outputs
Dead-Band Generation
PWM Chopping by High-Frequency Carrier

Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width

Modulator (APWM) Outputs
Single-Shot Capture of up to Four Event Time-Stamps
• Packages:
361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-
mm Ball Pitch
361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
• Commercial, Extended, or Industrial Temperature

WORKING WITH THE KIT AND THE IDE:
• Launch Code Composer Studio 6.0.1 from the Desktop, otherwise

click on Start -> All Programs -> Texas Instruments -> Code
Composer Studio
6.0.1 (Make sure kit is turned on before opening the program).
• Choose the location for the workspace, where your project will be
saved.
• Go to File -> New -> CCS Project.
• Specify the name of the project in the space provided.
• Provide target number 6748 and select LCDKC6748.
• Choose the Texas Instruments XDS100v2 USB Emulator.
• Click on Empty Project in the Project Template Section, and then click
on Finish.
• To write a program, follow either of the given

procedures: Create a new C file:
Go to File -> New -> Source File.
Specify the arbitrary source file name with “.c” extension.

It should be in the source folder (current project name).
Type your C Code and save.

Add an existing C file:
Right click on the project name in the workspace and

choose the add files option.
Browse for the required C file and click on OK.
• Go to Project -> Build project. If your code doesn’t have any errors
and warnings, a message will be printed in the console window
showing the message: **** Build Finished ****. Otherwise errors or
warnings are displayed, if any.
• After building the project successfully, connect the kit with the
system using the JTAG emulator and power the kit. Connect
additional components if necessary.
• Click on Debug in the Run tab or press F11 on the keyboard.
• After all background tasks finish completing, click on Resume in the

Run tab or press F8 on the keyboard.
• Output is displayed in the Console Window.
• To generate any graphs, click on the Tools tab -> Graphs and select
the required type of graph. Specify its properties in the given window
and click on OK. The graph is displayed in a separate window.
Result:
Thus the features and architecture of TMS320C6748 was studied

and the procedure to work with the kit and IDE was learnt.
EXPT. NO. 10 GENERATION OF SIGNALS
DATE:
AIM
To generate a sine wave using the TMS320C6748 kit.
APPARATUS REQUIRED
TMS320C6748 kit with included accessories
A PC with Code Composer Studio 6.0.1 IDE
ALGORITHM
Include necessary header files.
Initialise a frequency variable and a loop counter.
Initialise a floating point array to store values.
In the main function, create a loop which stores sine wave values in
the array for each iteration.
Compile the program and observe the output.
PROGRAM
#include
<stdio.h>
#include<math
> #define freq
500 float
m[128];
void main()
{
int i=0;
for(i=0;i<127;
i++)
m[i]=sin(2*3.14*freq*i/24000);
printf("%f\n",m[i]);
}
}
OUTPUT
RESULT
Thus a sine wave was generated using TMS320C6748 kit and the output
was observed and verified.
EXPT. NO. 11 LINEAR CONVOLUTION
DATE:
AIM
To perform linear convolution using the TMS320C6748 kit.
APPARATUS REQUIRED:
ALGORITHM:
Initialise length of x[n] and h[n].
Specify the sequence of x[n] and h[n].
Using a for loop, calculate y[n]=x[k]*h[n-k] for 0≤k≤n and

0≤n≤(sum of length of sequences-1).
PROGRAM
#include<stdio.h>
#define Length1 4
#define Length2 3
float x[Length1+Length2-1]={1,2,3,4,0,0};
float h[Length1+Length2-1]={5,6,7,0,0,0};
float y[Length1+Length2-1];
void main()
{
int n, k;
for(n=0; n<(Length1+Length2-1); n++)

{
y[n]=0;
for(k=0; k<=n; k++)
y[n]+=x[k]*h[n-k];
}
printf("Convolution Output =\n");
for(n=0; n<(Length1+Length2-1);
n++) printf("%f\n", y[n]);
}
OUTPUT
RESULT
Thus linear convolution was performed using TMS320C6748 kit and

the output was observed and verified.
EXPT. NO. 12 CIRCULAR CONVOLUTION
DATE:
AIM
To perform circular convolution using TMS320C6748 kit.
APPARATUS REQUIRED
ALGORITHM
Get the length of x[n] and h[n].
Get the sequences x[n] and h[n].
If the length of the sequences are unequal, pad the smaller

sequence with zeroes.
Fold the second sequence h[n] to h[-n].
Perform circular convolution by multiplying each corresponding

element of the sequences.
Perform circular shift, and create a loop to display the result.

PROGRAM
#include<stdio.h>
int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[30];
void main()
{
printf("Enter the length of the first sequence:\n");
scanf("%d",&m);y
printf("Enter the length of the second sequence:\n");
scanf("%d",&n);
printf(" Enter the first

sequence:\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf(“Enter the second

sequence:\n"); for(j=0;j<n;j++)
scanf("%d",&h[j]);
if(m-n!=0) /*If length of both sequences are not equal*/
if(m>n) /* Pad the smaller sequence with zero*/
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y[0]=0;
a[0]=h[0];
for(j=1;j<n;j++) /*folding h(n) to h(-n)*/
a[j]=h[n-j];
for(i=0;i<n;i++) /*Circular convolution*/
y[0]+=x[i]*a[i];
for(k=1;k<n;k++)
y[k]=0;
for(j=1;j<n;j++)
x2[j]=a[j-1]; /*circular shift*/

x2[0]=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];
}
}
printf("The circular convolution is:\n"); /*Display the result*/
for(i=0;i<n;i++)
printf("%d \t",y[i]);
}
Output:
RESULT:
Thus circular convolution was performed using TMS320C6748 kit and

EXPT. NO. 13 DISCRETE FOURIER TRANSFORM
DATE:
AIM
To perform discrete Fourier transform using the TMS320C6748 kit.
APPARATUS REQUIRED
ALGORITHM
Initialise arrays for storing real and imaginary part of the output.
Initialise the input array, and get the input sequence.
Using a loop, calculate real part and imaginary part for each
index as follows: sumre=sumre+x[n]*cos(2*pi*k*n/N) and
sumim=sumim-x[n]* sin(2*pi*k*n/N).
Store the two results in two separate arrays.
Display the result in the form of a complex number Re+iIm.

PROGRAM
#include<stdio.h>
#include
<math.h
>
int N,k,n,i;
float pi=3.1416,sumre=0, sumim=0,out_real[8]={0.0}, out_imag[8]={0.0};
int x[32];
void main(void)
{
printf(" enter the length of the sequence\n");
scanf("%d",&N);
printf(" enter the sequence\n"); for(i=0;i<N;i++)

scanf("%d",&x[i]);
for(k=0;k<N;k++)
sumre=0;
sumim=0;
for(n=0;n<N;n++)
sumre=sumre+x[n]* cos(2*pi*k*n/N); sumim=sumim-

x[n]* sin(2*pi*k*n/N);
}
out_real[k]=sumre;
out_imag[k]=sumim;
printf("X([%d])=\t%f\t+\t%fi\n",k,out_real[k],out_imag[k]);
OUTPUT
RESULT
Thus discrete Fourier transform was performed using TMS320C6748 kit

and the output was observed and verified.
EXPT. NO. 14 FAST FOURIER TRANSFORM
DATE:
AIM
To perform Fast Fourier transform using the

TMS320C6748 kit and display its magnitude spectrum.
APPARATUS REQUIRED
ALGORITHM
1. Include necessary header files.
2. Initialise arrays for storing real and imaginary part of the

output, twiddle factors.
3. Compute magnitudes and perform bit reversal accordingly.
4. Compile the program and observe the output.
Program:
#include <math.h>
#define PTS 64 //# of points for FFT
#define PI 3.14159265358979
typedef struct {float real,imag;}

COMPLEX;
void FFT(COMPLEX *Y, int n);
//FFT prototype float iobuffer[PTS];
//as input and output buffer float
x1[PTS]; //intermediate buffer
short i; //general purpose index
variable
short buffercount = 0; //number of new

samples in iobuffer short flag = 0; //set to 1 by
ISR when iobuffer full COMPLEX w[PTS];
//twiddle constants stored in w COMPLEX
samples[PTS]; //primary working buffer
main()
{
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of

twiddle constants w[i].imag =-sin(2*PI*i/(PTS*2.0)); //Im
component of twiddle constants }
for (i = 0 ; i < PTS ; i++) //swap buffers
iobuffer[i] = sin(2*PI*10*i/64.0);/*10- > freq, 64 -> sampling freq*/
samples[i].real=0.0;
samples[i].imag=0.0;
}
for (i = 0 ; i < PTS ; i++) //swap buffers
samples[i].real=iobuffer[i]; //buffer with new data
for (i = 0 ; i < PTS ; i++)
samples[i].imag = 0.0; //imag

components = 0
FFT(samples,PTS); //call function
FFT.c
for (i = 0 ; i < PTS ; i++) //compute magnitude
x1[i] = sqrt(samples[i].real*samples[i].real+
samples[i].imag*samples[i].imag);
} //end of main
//FFT FUNCTION
void FFT(COMPLEX *Y, int N) //input sample array, # of points
COMPLEX temp1,temp2; //temporary

storage variables int i,j,k; //loop counter
variables
int upper_leg, lower_leg; //index of upper/lower

butterfly leg int leg_diff; //difference between
upper/lower leg
int num_stages = 0; //number of FFT stages
(iterations) int index, step; //index/step
through twiddle constant i = 1; //log(base2) of
N points= # of stages
do
{
num_stages +=1;
i = i*2;
}while (i!=N);
leg_diff = N/2; //difference between

upper&lower legs step = (PTS*2)/N;
//step between values in twiddle.h for (i =
0;i < num_stages; i++) //for N-point FFT
{
index = 0;
for (j = 0; j < leg_diff; j++)
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real +
(Y[lower_leg]).real; temp1.imag =
(Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real -
(Y[lower_leg]).real; temp2.imag =
(Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real =
temp2.real*(w[index]).real -
temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
index += step;
leg_diff = leg_diff/2;
step *= 2;
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data
k = N/2;
while (k <= j)
{
j = j - k;
k=k/2;
}
j = j + k;
if (i<j)
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}}
return;
}
OUTPUT
RESULT
Thus Fast Fourier transform was performed using TMS320C6748

kit and the output was observed and verified.
EXPT. NO. 15 IMPLEMENTATION OF IIR FILTERS
DATE:
AIM
To implement low pass IIR filter using the TMS320C6748 kit.
APPARATUS REQUIRED
ALGORITHM
Get the order and the cutoff frequency of the filter.
Substitute the values in the filter transfer function and store it in an

array.
Display the array.
PROGRAM
#include<stdio.h>
#include
<math.h
> int
i,w,wc,c,
N; float
H[100];
float
mul(float,
int); void
main()
printf("\nEnter order of IIR LP

Filter:"); scanf("%d",&N);
printf("\nEnter the Cutoff

Freq "); scanf("%d",&wc);
for(w=0;w<100;w++)
{
H[w]=1/sqrt(1+mul((w/(float)wc),2*N));
printf("H[%d]=%f\n",w,H[w]);
float mul(float a,int x)
for(i=0;i
<x-
1;i++)
a*=a;
return(a);
}
OUTPUT
For order 2 and cut off 100Hz
RESULT
Thus IIR low pass filter was implemented using TMS320C6748 kit and
EXPT. NO. 16 IMPLEMENTATION OF FIR FILTERS
DATE:
AIM
To implement low pass FIR filter using the TMS320C6748 kit.
APPARATUS REQUIRED
ALGORITHM
Initialise sampling frequency and cutoff frequency.
Calculate the coefficient and display write a loop for displaying

the coefficients.
PROGRAM
#include<stdio.h>
#include<math.h>
#define PI 3.14
void main()
{
const int sampf=10000;
const int cutf=1000;
float value,a,b,output;
int nyqf,n,c0;
int *coeff;
coeff = (int *)0xc0001000;
nyqf=sampf/2;
c0=cutf/nyqf;
for(n=-5;n<6;n++)
{
if(n==0)
output = 0.5;
else
a = (n * PI)/2;
b=n * PI;
value = sin(a);
output = value/b;
printf("\n The Fir Low pass filter coefficient : %f",output);
}
OUTPUT
The Fir Low pass filter coefficient : 0.063694

The Fir Low pass filter coefficient : -0.000254
The Fir Low pass filter coefficient : -inf
RESULT
Thus FIR low pass filter was implemented using TMS320C6748 kit and
CONTENT BEYOND THE SYLLABUS
EXPT. NO. 17 IMAGE PROCESSING

DATE:
AIM
To perform median filtering and histogram equalisation on a given

image using MATLAB.
APPARATUS REQUIRED
A PC with MATLAB software
ALGORITHM
Median filtering:
Read the image file.
Introduce salt and pepper noise in the image.
Define the box and median filters, and vary the boundaries of
the filters by changing matrix dimensions.
Observe the output images.

Histogram equalisation:
Read the image file.
Perform histogram equalisation on the image.
Observe the output image and graph, and compare with

the original image and graph.
PROGRAM
%Media
filtering
clc
Clear all;
Close all;
a=imread('horse.jpg');
%Addition of salt and

pepper noise
b=imnoise(a,'salt &
pepper',0.05); %Defining
the box and median filters
h1=1/9*ones(3,3);
h2=1/25*ones(5,5);
c1=conv2(b,h1,'same');
c2=conv2(b,h2,'same');
c3=medfilt2(b,[3 3]);
subplot(3,3,1),imshow(a),title('Original image')
subplot(3,3,2),imshow(b),title('Salt & pepper
noise') subplot(3,3,3),imshow(uint8(c1)),title('3 x
3 smoothing')
subplot(3,3,4),imshow(uint8(c2)),title('5 x 5
smoothing')
subplot(3,3,5),imshow(uint8(c3)),title('3x 3
Median filter')
Median filter')
Median filter')
Median filter')
%Histogram
equalisation clc
Clear all;
Close all;
a=imread('babyincradle.
png'); %perform
histogram equalization
b=histeq(a);
subplot(2,2,1),imshow(a),title('original image')
subplot(2,2,2),imshow(b),title('After histogram
equalization')
subplot(2,2,3),imhist(a),title('original histogram')
subplot(2,2,4),imhist(b),title('After histogram equalization')
RESULT
Thus median filtering and histogram equalisation was performed on the

given image and the output was verified.
CONTENT BEYOND THE SYLLABUS
EXPT. NO. 18 AUDIO PROCESSING
DATE:
AIM
To read an audio file and perform autocorrelation on its

voiced and unvoiced portion using MATLAB.
APPARATUS REQUIRED
A PC with MATLAB software
ALGORITHM
Read the audio file and sample it at a given sampling frequency.
Select 2 parts of the audio file.
Perform autocorrelation on the selected portions.
Observe the output.
PROGRAM
fs=8000;
x=audioread('Hello.wav');
ss1=x(1:700);
[ac1,lags1]=xcorr(ss1);
ss4=x(1800:1860);
[ac4,lags4]=xcorr(ss4);
subplot(2,2,1);
plot(ss1);
legend('Voiced speech');
subplot(2,2,2);
plot(lags1,ac1);
xlim([lags1(1),ac1(end)]);
legend('Autocorrelation of voiced
speech'); subplot(2,2,3);
plot(ss4);
legend('Unvoiced
speech');
subplot(2,2,4);
plot(lags4,ac4);
xlim([lags1(1),lags
1(end)]);
legend('Autocorrelation of unvoiced speech');

RESULT
Thus autocorrelation was performed on the voiced and unvoiced

portion of the audio file and the output was observed and verified.

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EXPT. NO.

To study the features and architecture of the TMS320C6748

The TMS320C6748 fixed- and floating-point DSP is a low-power applications

The device enables original-equipment manufacturers (OEMs) and original-

The SATA controller provides a high-speed interface to mass data storage

The uPP provides a high-speed interface to many types of data converters,

TI TMS320C6748 DSP Application Processor 456-MHz C674x

456-MHz ARM926EJ RISC CPU (OMAP-L138 only) On-Chip RTC

1 Micro SD/MMC Slot

One mini-USB Serial Port (on-board serial to USB)

One Fast Ethernet Port (10/100 Mbps) with status

One mini-USB OTG port (USB

One VGA Port (15 pin D-SUB)

One LCD Port (Beagleboard XM

One Leopard Imaging Camera Sensor Input (36-pin ZIP

14-pin JTAG header (No onboard emulator; external emulator is required)

TMS320C6748 DETAILED SPECIFICATIONS:

• 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP

• C674x Instruction Set Features

Superset of the C67x+ and C64x+

Byte-Addressable (8, 16, 32, and 64 Bit

Bit-Field Extract, Set, Clear

• C674x Two-Level Cache Memory

32KB of L1D Data RAM/Cache

256KB of L2 Unified Mapped

∙ Enhanced Direct Memory Access Controller 3

64 Independent DMA Channels

Programmable Transfer Burst Size

∙ TMS320C674x Floating-Point VLIW DSP Core

Load-Store Architecture with Nonaligned Support

Six ALU (32- and 40-Bit) Functional Units

Supports up to Four SP Additions Per Clock, Four DP

Supports up to Two Floating-Point (SP or DP) Reciprocal

Two Multiply Functional Units

Mixed-Precision IEEE Floating-Point Multiply Supported up to:

O 2 SP x SP → DP Every Two Clocks

Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies,

four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per

Instruction Packing Reduces Code Size

Hardware Support for Modulo Loop Operation Protected

Exceptions Support for Error Detection and Program Redirection

• Two External Memory Interfaces:

NOR (8- or 16-Bit-Wide Data)

16-Bit SDRAM with 128-MB Address Space

DDR2/Mobile DDR Memory Controller with one of the following:

16-Bit mDDR SDRAM with 256-MB Address Space

• Three Configurable 16550-Type UART Modules:

16x or 13x Oversampling Option

• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with

• Two Master and Slave Inter-Integrated Circuits (I2C Bus™)

• Programmable Real-Time Unit Subsystem (PRUSS)

4KB of Instruction RAM Per Core

PRUSS can be Disabled via Software to Save Power

Register 30 of Each PRU is Exported from the Subsystem in

Standard Power-Management Mechanism

Entire Subsystem Under a Single PSC Clock Gating Domain

Dedicated Switched Central Resource

• USB 1.1 OHCI (Host) with Integrated PHY (USB1)

• USB 2.0 OTG Port with Integrated PHY (USB0)

USB 2.0 High-, Full-, and Low-Speed Host

End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX

• One Multichannel Audio Serial Port (McASP):

FIFO Buffers for Transmit and Receive

• Two Multichannel Buffered Serial Ports (McBSPs):

if(m-n!=0) /If length of both sequences are not equal/