Analysis of Three Phase Three Level Diode

Clamped Inverter based on Fuzzy Logic control

Strategy for 690Volt Application
J.Chelladurai2, P.Muthuraj1
Electrical & Electronics engineering Department,
PSG College of Technology, Coimbatore, Tamil Nadu, India
2jcd@eee.psgtech.ac.in
1muthumohan256@hotmail.com

Abstract — This paper proposes the analysis of a three phase
three level diode clamped multilevel inverter for 690V
application. Using the fuzzy logic control strategy for balancing
the DC-link voltage of a capacitors has been implemented. Also
generated reference voltage signals based on load voltage. Twelve
Pulse Diode Bridge Rectifier is used as a source for multilevel
inverter. Multi-Carrier based PWM technique is used for
generating gate pulses for switches. The system for 690V AC has
been obtained by using MATLAB/Simulink. The effect of Total
Harmonic Distortion (THD) on the output voltage has been
analyzed.
Index Terms—Multilevel Inverters, Diode Clamped Inverter,
Fuzzy Logic Control, Total Harmonic Distortion.
. resulting complexity of the mechanical structure of the DC-
I. INTRODUCTION
The three level Neutral-Point-Clamped inverter has been first
presented by Nabae et al. in 1981 [1] using bipolar power
transistors. Later this topology was successfully applied in
designing inverters for traction applications operating from
750 V DC and industrial inverters connected to the 690 V AC
mains before 1700 V IGBTs became available [2]. Today this
topology is used in many designs of variable speed drives
operating on medium voltage and using GTOs, IGCTs or high
voltage IGBTs [3]. In the aforementioned applications the
three level topology has been chosen because either the
voltage rating or the power rating exceeds the level that could
be covered by standard two level topology without series
connection of devices.
Compared to the two level topology with series connection the
three level approach here provides improved spectral
performance at little additional expenses. But there are also
recent designs applying the topology to a general purpose
drive connected to the low voltage mains [4], an application
that easily can be covered by the standard topology. Here the
three-level design is favoured because it reduces the stress that
the inverter causes to machine windings and bearings. Other
low voltage/low power applications where three level
inverters are considered today are transformer-less UPS
systems and PV inverters. While in a drives application the
inductance for smoothing the output current is provided for
free by the machine these applications need dedicated filters.
Three level topology allows to reduce the size and the cost of
the filter by better spectral performance of the output voltage
and the option to increase the switching frequency without too
much penalty in switching loss.
Typical issues to deal with when designing three-level
converters are the complex loss calculation [5] and ensuring
voltage balance on the DC-link [6]. When three level inverters
are built using dual modules or single switch modules it is
difficult to keep the commutating inductance within
reasonable limits for both relevant commutation loops. The
link is a significant challenge [3]. When three level topology
is adapted to low power applications one important economic
requirement is to keep the control and driving effort low and
to consider some specific requirements for protection.
The basic three types of multilevel topologies used are,
(1) Diode clamped multilevel inverters,
(2) Flying capacitors multilevel inverter,
(3) Cascaded inverter with separate DC sources.
Up to now these topics have only been sparsely covered in
literature.
II. .SYSTEM ARCHITECTURE
The proposed entire system is shown in Fig.1. It consists of
a Twelve Pulse Diode Bridge rectifier and a Three-level Diode
Fig. 1. Block Diagram of the Entire System
 Clamped Inverter. Both Rectifier and Inverter are coupled
using DC-link capacitors (C1, C2) with their conversion
formula.
DC-link voltage or individual capacitor voltages is/are
balanced by using Fuzzy logic controller. Output obtained
from controller use to generate gate pulses for each leg of the
inverter.
A. Twelve Pulse Converter:
The 12-pulse method [7] has been used for reduced
harmonic distortion. In these case two set of non-linear load
are fed by two phase shifted transformer winding with the
using of twelve pulse converter 5th and 7th harmonics can be
cancellation on primary side of transformer.
The Generalized harmonic order from twelve pulse rectifier Fig.3.Diode Clamped Three level Inverter
can be calculated using
H= np±1 Table.II. Number of States of NPC Inverter
Where, Topology No. of No. of No. of different
n = order of harmonics, Levels possible states
p = number of pulses for the converter. states
So, that 11th and 13th harmonics are present. 12-pulse rectifier 3 27 19
5th, 7th 90% cancelled still has 11th, 13th, 17th, 19th etc. 4 64 37
shown in Fig.2. NPC 5 125 61
n n3 n3-(n-1)3

I Principle of Operation:
The Fig.4 shows the modes of opoeration of a single leg
Diode Clamped Inverter.The each mode shows that the level
of voltages generated at the output terminal.

Fig.2. Twelve-Pulse Converter

B. Three Level Diode Clamped Inverter:
The diode clamped multilevel inverter [8] uses capacitors
in series to divide up the DC bus voltage into a set of voltage Fig.4.Voltage Generation from NPC Inverter a) Vdc output
levels. To produce m levels of the phase voltage, an m level potential b)Vdc/2 output potential c) 0 output potential
diode clamp inverter needs (m-1) capacitors on the dc bus. In C. Gate Pulses for NPC Inverter:
this paper, diode clamped multilevel inverters topology is Modulation strategies are responsible for synthesizing
used shown in Fig 3. reference control signals and for keeping all voltage sources
The Three level NPC Inverter parameters and it’s switching balanced. For Power Converters with DC voltage sources
states are shown in Table I and Table II. output voltage is represented by short voltage pulses of
different width.
Table.I. Three Level NPC Inverter Carrier based Pulse Width modulation (CB-PWM) [9] for
Topology No. of No. of No. of No. of more than two level converters requires more carrier signals.
Levels IGBT’s Diodes Capacitors For n-level converter minimum (n-1) carrier signals are
3 12 6 4 needed. Each carrier signal is responsible for a pair of
4 18 18 9 switches. One switch is controlled directly by the rectangular
NPC 5 24 24 16 signal and second one is controlled by negative sequence.
n 6(n-1) 3(n-1)(n-2) (n-1)2 Multiple carrier signals in multilevel converters creates
various possibilities of mutual locations of those signals.
In General, the multilevel modulation is classified into three Table. IV. Knowledge Rule Base for Reference Voltage
are, Generation
• Fundamental Switching Frequency (FSF), LOAD
• Mixed Switching Frequency (MSF) VOLTAGES LOW MEDIUM HIGH
• High Switching Frequency PWM (HSF) A,B,C
Simple Space Vector and Selective Harmonic Elimination LOW MIN MAX MAX
will come under FSF and Hybrid Multilevel Modulation will MEDIUM MAX MAX MAX
come under MSF. HIGH MAX MAX MAX
Then, HSF PWM technique are classified as,
• Phase Shifted Carriers (PSC)
• Level Shifted Carriers (LSC) III. RESULTS AND DISCUSSIONS
1. Phase Disposition (PD)
1) Twelve Pulse Diode Bridge Rectifier:
2. Phase Opposite Disposition (POD)
3. Alternative Phase Opposite Disposition (APOD) 𝑉𝑑𝑐 = 3.3042 𝑉𝑚
In this Paper, The above three variants of Level Shifted CB- 2) NPC Inverter:
PWM have been analyzed and for implementation Phase
Disposition method is used. 𝑉𝑑𝑐
𝑉𝑟𝑚𝑠 = 1.22 ∗ ∗𝑀
2
D. Fuzzy Logic Control:
Fuzzy Logic Controller (FLC) is introduced by Zadeh in 𝑉𝑟𝑚𝑠 = 1.22 ∗ 1131/2 ∗ 1
1965. It is one of the most successful applications of fuzzy set
theory. It’s major feature is the use of linguistic variables 𝑉𝑟𝑚𝑠 = 689.31 𝑉
rather than numerical variables. The general structure of the
FLC is shown in Fig. 5 Table. IV. System Specifications
. As depicted, the FLC [10] is composed by a fuzzification, a Input Voltage 415 V
knowledge base, an inference engine and a de-fuzzification.
DC-Link Voltage 1131 V
Inverter output Voltage(RMS) 690 V
Modulation Index 0.90 – 0.95
DC-Link Capacitors (C1,C2) 600 µF
Switching frequency (Inverter) < 5 kHz

Fig.5. Structure of FLC Output filter L= 2 mH, C=13.37 µF

Fuzzy logic controllers have been an interesting and good AC Load R= 75 KW(max)
alternative in more power electronics application. Their
advantages are robustness, non-requirement of a mathematical
model, and acceptance of non-linearity. To benefit from these 3) Fuzzy Logic Implementation:
advantages, a new fuzzy logic controller is proposed for use
in the three-level (NPC) inverter. The new controller is
designed to maintain the DC link voltage of the capacitors
constant and also based on the load variation to maintain the
output voltage constant using fuzzy rules.
Fuzzy logic control is the evaluation of a set of simple
linguistic rules to determine the control action. The desired
inverter switching signals of the three-level NPC inverter are
determined based on load Voltage. The rules used are shown
in Table. III. and Table IV.
Table. III. Knowledge Rule Base for capacitors balancing
C!,C2
Balance LOW EQUAL HIGH
LOW - EQUAL EQUAL
EQUAL EQUAL EQUAL EQUAL
HIGH EQUAL EQUAL -
 IV. ANALYSIS
1) Total Harmonic Distortion (3-Level):

Table. IV. THD Comparison with other types of Multilevel

Inverters at 10KW
Inverter
S No. Configuration V, THD I, THD
1 Two level inverter 74.34% 6.75%
2 Diode clamped 35.05% 22.17%
three level inverter
3 Flying Capacitor 64.11% 64.01%
three level inverter
Fig.6.FLC for Generation of reference signal and DC 4 Cascaded H bridge 97.81% 41.37%
Voltage Balancing. three level inverter

3.1) FLC MODEL IN MATLAB:

2) Phase Disposition:

Table. V. THD for Phase Disposition with Different

Modulation Index at 10KW
MI Vo, 3rd 5th 7TH 9TH V,
rms (V) (V) (V) (V) THD
fund %
Fig.7 Input Member Function for. DC-Link Voltage (V)
balancing 0.5 445.8 10.03 1.78 2.23 0.09 60.77
0.6 492.6 11.88 2.73 2.13 2.44 44.63
0.7 558.3 14.12 3.41 2.36 0.53 40.43
0.8 627.3 17.24 4.01 2.53 1.24 38.63
0.9 686 19.79 5.97 2.97 2.24 36.36

V. SIMULATION RESULTS
Fig.8.Input Member Function for Generation of A-Phase
Reference Signal The analysis of the proposed system is further discussed
and verified in this section through simulations in the closed
loop conditions using MATLAB / Simulink model. Table IV
indicates the values of the parameters used in the simulations.
The results obtained is shown below,

Fig.9.Surface for DC-Link Voltage Balancing

Fig.10.Surface for Generation of A-Phase Reference Signal .Fig.11.DC-Link Voltage


Fig.12.NPC Inverter output voltage at 10 KW
Fig.13.NPC Inverter output voltage at 75 KW
Fig.14.a) & b) Vc1 and Vc2 without FLC c) & d) Vc1
and Vc2 with FLC
VI. CONCLUSION
The Diode Clamped Inverter for 690 V AC output was
finally achieved with various loads (10 KW, 75 KW) and their
respective Total Harmonic Distortion (THD = 36.36%) was
shown at the modulation index of 0.9.
The advanced Fuzzy Logic Controller was successfully
implemented for DC link Voltage of the Capacitors and also
based on load voltage reference signals for each phase have
been generated using MATLAB/Simulink.
VII. REFERENCES
:
[1] Nabae A.; Takahashi I.; Akagi, H.: A new neutral-point-clamped
PWM inverter, IEEE Transactions on Industry Applications,
Vol.IA-17, No.5. Sep./Oct. 1981, pp. 518-523.
[2] Tadros, Y.; Salama, S.; Schütze T.: Threelevel IGBT inverters for
industrial drives and traction applications, EPE Journal, Vol. 4,No.
2, June 1994
[3] Wu, B. et al.: Multilevel voltage-source converter topologies for
industrial medium voltage drives, IEEE Transactions on Industrial
Electronics, Vol. 54, No. 6, Dec. 2007
[4] Krug, H.-P.; Kume, T.; Swamy M.: Neutralpoint clamped three-
level general purpose inverter – features, benefits and
applications- , Power Electronics Specialists Conference
2004,p. 323-328
[5] Tomta, G.; Nielsen, R.; Analytical eqautions for three level NPC
converters, EPE 2001
[6] Pou,J.; Boroyevich D.; Pindado R.: Effects of imbalances and
nonlinear load on the voltage balance of a neutral-point-
clamped inverter, IEEE Transactions on Power
Electronics, Vol. 20, No. 1, Jan. 2005
[7] Madhuri Saxena1, Sanjeev Gupta2.; Simulation of Multipulse
Converter for Harmonic Reduction using Controlled Rectifier. ;
International Journal of Science and Research (IJSR), India Online
ISSN: 2319-7064
[8] José Rodríguez, Senior Member, IEEE, Jih-Sheng Lai, Senior
Member, IEEE, and Fang Zheng Peng, Senior Member, IEEE.;
Multilevel Inverters: A Survey of Topologies, Controls, and
Applications.; IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002
[9] P. K. Chaturvedi, Shailendra Jain, and Pramod Agrawal, Member,
IEEE.; A Study of Neutral Point Potential and Common Mode
Voltage Control in Multilevel SPWM Technique.; Fifteenth
National Power Systems Conference (NPSC), IIT Bombay,
December 2008
[10] M. Balamurugan, M. Gnana Prakash, S. Umashankar.; Neutral
Point Potential Balance of Three Phase Three Level Diode
Clamped Inverter.; WSEAS TRANSACTIONS on SYSTEMS