GP GANDHINAGAR EC DEPARTMENT AE(3331102)

EXPERIMENT NO. – 2

AIM: TO TEST COLPITTS OSCILLATOR FOR VARIABLE FREQUENCY.

APPARATUS: Colpitts Oscillator Trainer kit, CRO, Connecting Probes.

THEORY:
The Colpitts circuit, like other LC oscillators, consists of a gain
device (such as a bipolar junction transistor, field effect transistor, operational
amplifier, or vacuum tube) with its output connected to its input in a feedback
loop containing a parallel LC circuit (tuned circuit) which functions as a band
pass filter to set the frequency of oscillation.
A Colpitts oscillator is the electrical dual of a Hartley oscillator,
where the feedback signal is taken from an "inductive" voltage divider
consisting of two coils in series (or a tapped coil). Fig. shows the common-base
Colpitts circuit. L and the series combination of C1 and C2 form the parallel
resonant tank circuit which determines the frequency of the oscillator. The
voltage across C2 is applied to the base-emitter junction of the transistor, as
feedback to create oscillations. The frequency of oscillation is approximately
the resonant frequency of the LC circuit, which is the series combination of the
two capacitors in parallel with the inductor.

CIRCUIT DIAGRAM :

PROCEDURE:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

1. Connect the circuit as shown in the circuit diagram.

2. Check the circuit for biasing condition.
3. After connecting the feedback network .check the output.
4. Check for the sinusoidal waveform at output. Note down the
frequency of the output waveform and check for any deviation from the
designed value of the frequency.
5. Change C1 and C2 and again find frequency and compare.
6. Calculate the theoretical frequency of the circuit using the
formulae.

OBSERVATION TABLE:

C1 C2 L Theoritical Practical
Frequency (Hz) Frequency
(Hz)
24nF 240nF 340mH
34nF 340nF 340mH

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO. – 3
AIM: TO TEST HARTLEY OSCILLATOR FOR VARIABLE FREQUENCY.

APPARATUS:Hartley Oscillator Trainer Kit, CRO, Decade Inductance Boxes,

Connecting Probes.

THEORY:

The Hartley oscillator is an electronic oscillator circuit in which

the oscillation frequency is determined by a tuned circuit consisting
of capacitors and inductors, that is, an LC oscillator. The circuit was invented in
1915 by American engineer Ralph Hartley. The distinguishing feature of the
Hartley oscillator is that the tuned circuit consists of a single capacitor in
parallel with two inductors in series (or a single tapped inductor), and
the feedback signal needed for oscillation is taken from the center connection of
the two inductors.
The frequency of oscillation is approximately the resonant
frequency of the tank circuit. If the capacitance of the tank capacitor is C and the
total inductance of the tapped coil is L then

If two uncoupled coils of inductance L1 and L2 are used then

CIRCUIT DIAGRAM :

PROCEDURE:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
1. Connect the circuit as shown in the circuit diagram.
2. Check the circuit for biasing condition.
3. After connecting the feedback network .check the output.
4. Check for the sinusoidal waveform at output. Note down the
frequency of the output waveform and check for any deviation from the
designed value of the frequency.
5. Calculate the theoretical frequency of the circuit using the
formulae.
6. Compare theoretical and practical value.

OBSERVATION TABLE : KEEPING C=1uF

Sr L1 L2 Theoretical Practical
No. Frequency frequency(KHz)
(KHz)

1 0.5mH 0.5mH
2 1mH 1mH

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO. – 4

AIM: TO TEST WIEN BRIDGE OSCILLATOR FOR VARIABLE FREQUENCY.

APPARATUS: Wein Bridge Oscillator Trainer Kit, Power Supply, CRO,

Connecting wires.

THEORY:
The wein bridge oscillator is a standard circuit for generating low
frequencies in the range of 10 Hz to about 1MHz.The method used for getting
+ve feedback in wein bridge oscillator is to use two stages of an RC-coupled
amplifier. Since one stage of the RC-coupled amplifier introduces a phase shift
of 180 deg, two stages will introduces a phase shift of 360 deg. At the frequency
of oscillations f the +ve feedback network shown in fig makes the input &
output in the phase. The frequency of oscillations is given as

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are made as per the circuit diagram

2. Feed the output of the oscillator to a C.R.O by making adjustments
in the Potentiometer connected in the +ve feedback loop, try to obtain a
stable sine Wave.
3. Measure the time period of the waveform obtained on CRO. &
calculate the Frequency of oscillations. Repeat the procedure for
different values of capacitance.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

OBSERVATION TABLE:

Sr
No. Resistor Capacitor Theoretical Practical
Value Value Frequency frequency(KHz)
(KHz)

1
2
3
4

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO.– 5

AIM: TO TEST UJT AS A RELAXATION OSCILLATOR.

APPARATUS: UJT as a Relaxation Oscillator Trainer Kit, Power Supply, CRO,

Connecting wires.

THEORY:
UJT relaxation oscillator is a type of RC (resistor-capacitor)
oscillator where the active element is a UJT (uni-junction transistor). UJT is an
excellent switch with switching times in the order of nano seconds. It has a
negative resistance region in the characteristics and can be easily employed in
relaxation oscillators. The UJT relaxation oscillator is called so because the
timing interval is set up by the charging of a capacitor and the timing interval is
ceased by the the rapid discharge of the same capacitor.
UJT (uni junction transistor). From the name itself, the UJT or uni junction
transistor is a semiconductor device that has only one junction. The UJT has
three terminals designated B1, B2 and E.

UJT parameters:

RBBO : It is the resistance between the terminals B1 and B2.

RBBO= RB1 +RB2.
Intrinsic standoff ratio (η) : It is the ratio of RB1 to the sum of RB1 and RB2.
It can be expressed as
η = RB1/(RB1+RB2) or
η = RB1/RBBO.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CIRCUIT DIAGRAM :

The circuit diagram of a UJT relaxation oscillator is given shown

above. R1 and R2 are current limiting resistors. Resistor R and capacitor C
determines the frequency of the oscillator. The frequency of the UJT relaxation
oscillator can be expressed by the equation
F = 1/ (RC ln(1/(1-η))
where η is the intrinsic standoff ratio and ln stand for natural logarithm.

When power supply is switched ON the capacitor C starts

charging through resistor R. The capacitor keeps on charging until the voltage
across it becomes equal to 0.7V plus ηVbb. This voltage is the peak voltage
point ”Vp” denoted in the characteristics curve (Fig:2). After this point the
emitter to RB1 resistance drops drastically and the capacitors starts
discharging through this path. When the capacitor is discharged to the valley
point voltage “Vv” the emitter to RB1 resistance climbs again and the capacitor
starts charging. This cycle is repeated and results in a sort of sawtooth
waveform across the capacitor. The saw tooth

WAVEFORM :
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

PROCEDURE:

1. Connections are made as per the circuit diagram

2. Switch on the Power Supply.
3. Measure the time period of the waveform obtained on CRO. &
calculate the Frequency of oscillations.
4. Repeat the procedure for different values of R & C.

OBSERVATION TABLE:

Sr.no. Resistor Capacitor Theoretical Practical

value value frequency frequency
( KHz) (KHz)

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

EXPERIMENT: 6

AIM: TO STUDY BASICS OF IC 741(OP-AMP).

APPARATUS: IC 741, CRO, Function Generator, connecting leads.

THEORY:
The term operational amplifier or "op-amp" refers to a class of
high-gain DC coupled amplifiers with two inputs and a single output. The
modern integrated circuit version is typeset by the famous 741 op-amp. Some
of the general characteristics of the IC version are:

1. High gain, on the order of a million

2. High input impedance, low output impedance
3. Used with split supply, usually +/- 15V
4. Used with feedback, with gain determined by the feedback
network.

The operational amplifier (op-amp) was designed to perform mathematical

operations. Although
Now superseded by the digital computer, op-amps are a common feature of
modern analogue electronics.
The op-amp is constructed from several transistor stages, which commonly
include a differential input
stage, an intermediate-gain stage and a push-pull output stage. The differential
amplifier consists of a matched pair of bipolar transistors or FETs. The push-
pull amplifier transmits a large current to the load and hence has a small output
impedance.

The op-amp is a linear amplifier with Vout / Vinp. The DC open-loop

voltage gain of a typical op-amp is 103 to 106. The gain is so large that most
often feedback is used to obtain a specific transfer function and control the
stability. Cheap IC versions of operational amplifiers are readily available,
making their use popular in any analog circuit. The cheap models operate from
DC to about 20 kHz, while the high-performance models operate up to 50 MHz.
A popular device is the 741 op-amp. It is usually available as an IC in an 8-pin
dual, in-line package (DIP).
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Internal Structure of IC 741.

Pin Diagram of IC 741

IC 741 Specifications
Supply voltage ± 22v max
Input impedance 2 Megohm typically
Input current 100 nA approx
Output impedance 75 ohms approx
Output Current 13 mA max
Output voltage ± 13v
(Vs = ±15v)
Open loop gain > 100,000
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

EXPERIMENT NO. – 7

AIM: TO DESIGN AND REALIZE INVERTING AMPLIFIER USING 741 OP-

AMP.

APPARATUS: CRO, Function Generator, Bread Board, 741 IC, ±12V

supply, Resistors 1KΩ, 10KΩ, and Connecting leads.
THEORY:
An inverting amplifier using opamp is a type of amplifier
using opamp where the output waveform will be phase opposite to the
input waveform. The input waveform will be amplifier by the factor Av
(voltage gain of the amplifier) in magnitude and its phase will be inverted.
In the inverting amplifier circuit the signal to be amplified is applied to the
inverting input of the opamp through the input resistance R1. Rf is the
feedback resistor. Rf and Rin together determine the gain of the amplifier.
Inverting operational amplifier gain can be expressed using the equation
Av = – Rf/R1. Negative sign implies that the output signal is negated. The
circuit diagram of a basic inverting amplifier using opamp is shown below.
CIRCUIT DIAGRAM :

The input and output waveforms of an inverting amplifier using opamp

is shown below. The graph is drawn assuming that the gain (Av) of the
amplifier is 2 and the input signal is a sine wave. It is clear from the graph
that the output is twice in magnitude when compared to the input (Vout =
Av x Vin) and phase opposite to the input.
Practical inverting Amplifier using IC 741
A simple practical inverting amplifier using 741 IC is shown below. uA 741
is a high performance and of course the most popular operational amplifier.
It can be used in a verity of applications like integrator, differentiator,
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
voltage follower, amplifier etc. uA 741 has a wide supply voltage range
(+/-22V DC) and has a high open loop gain. The IC has an integrated
compensation network for improving stability and has short circuit
protection.
Signal to be amplified is applied to the inverting pi (pin2) of the IC. Non
inverting pin (pin3) is connected to ground. R1 is the input resistor and Rf
is the feedback resistor.
Rf and R1 together sets the gain of the amplifier. With the
used values of R1 and Rf the gain will be 10 (Av = -Rf/R1 = 10K/1K = 10).
RL is the load resistor and the amplified signal will be available across it.
POT R2 can be used for nullifying the output offset voltage. If you are
planning to assemble the circuit, the power supply must be well regulated
and filtered. Noise from the power supply can adversely affect the
performance of the circuit. When assembling on PCB it is recommended to
mount the IC on the board using an IC base.

In the inverting amplifier only one input is applied and that is to the
inverting input (V2) terminal. The Non inverting input terminal (V1) is
grounded.

Since, V1=0 V& V2=Vin

Vo= -A Vin
The negative sign indicates the output voltage is 1800 out of phase with
respect to the input and amplified by gain A.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

PROCEDURE:
1) Connect the circuit for inverting amplifier on a breadboard.
2) Connect the input terminal of the op-amp to function generator and
output T erminal to CRO.
3) Feed input from function generator and observe the output on CRO.
4) Draw the input and output waveforms on graph paper.

Observation Table :

Inverting Amplifier
Sr. Vin R1 Rf Vout Gain Av
No.
1
2
3
4
TEG AIRCU T AN A PLI A O
S 1510
OUTPUT WAVEFORM :

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO.– 8

AIM: TO DESIGN AND REALIZE NON-INVERTING AMPLIFIER USING 741

OP-AMP.

APPARATUS: CRO, Function Generator, Bread Board, 741 IC,

±12Vsupply, Resistors 1KΩ, 10KΩ, and Connecting leads.

THEORY:
Non-inverting amplifier using 741:

The input is applied to the non-inverting input terminal and the Inverting
terminal is connected to the ground.

V1= Vin & V2=0 Volts

Vo= A Vin

The output voltage is larger than the input voltage by gain A & is in phase
with the input signal.

PROCEDURE:

1. Connect the circuit for non inverting amplifier on a

breadboard.
2. Connect the input terminal of the op-amp to function
generator and output terminal to CRO.
3. Feed input from function generator and observe the output on
CRO.
4. Draw the input and output waveforms on graph paper.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Observation Table :

Non-Inverting Amplifier
Sr. No. Vin R1 Rf Vout Gain Av
1
2
3
4

Output Waveform:

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO: 9

A I M : T O DESIGN AND VERIFY THE OPERATIONS OF OP AMP

ADDER (SUMMING) AND SUBTRACTOR CIRCUIT USING 741 OP-AMP.

APPARATUS: CRO, Function Generator, Bread Board, 741 IC, ±12V

supply, Resistors, and Connecting leads.

THEORY:
Adder (Summing Amplifier):

Op-amp may be used to perform summing operation of several input

signals in inverting in inverting and non-inverting mode. The input signals
to be summed up are given to inverting terminal or non-inverting
terminal through the input resistance to perform inverting and non-
inverting summing operations respectively.

If the input to the inverting amplifier is increased, the resulting circuit is

known as adder. Output is a linear summation of number of input
signals. Each input signal produces a component of the output signal
that is completely independent of the other input signal. When there are
two inputs i.e.
Vo= - (V1+V2)
This is the inverted algebraic sum of all the inputs. If we connect the inputs
to non inverting terminal then the adder is non inverting adder.

Subtractor:
The basic difference amplifier can be used as a subtractor.
The signals to be subtracted are connected to opposite polarity inputs
i.e. in inverting or non-inverting terminals of the op-amp.

A circuit that finds the difference between two signals is called a

subtractor. The two inputs are applied at the inverting & non inverting
terminal of op-amp. If all external resistance are equal in value, so the
gain of the amplifier is equal to 1. The output voltages of the
differential amplifier with a gain of unity is,

Vo= - (R/R (Va-Vb) Vo= - (Va-Vb)

GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CIRCUIT DIAGRAM:

PROCEDURE:

1. Apply two different sine waves signal to the input of the adder
and subtractor.
2. Give the input amplitude of 5v peak to peak and frequency of 1
kHz.
3. Verify the output on CRO.

OBSERVATION TABLE:
Sr. No. V1 V2 Theoretical Practical Remarks
V0=V1+V2 V0 (values
matched or
not)
1
2
3
4

Sr. V1 V2 Theoretical Practical Remarks

No. V0=V1-V2 V0 (values
matched or
not)
1
2
3
4
Table: AIRCU T AN A PLI A O
S 151
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

EXPERIMENT NO: 10

AIM: TO STUDY BASICS OF IC 555(TIMER IC) .

APPARATUS:IC 555, CRO, Function Generator, connecting leads.

THEORY:
The 555 timer IC is an integrated circuit (chip) used in a variety of timer,
pulse generation, and oscillator applications. The 555 can be used to provide
time delays, as an oscillator, and as a flip-flop element. Derivatives provide up
to four timing circuits in one package.
Depending on the manufacturer, the standard 555 package includes 25
transistors, 2 diodes and 15 resistors on a silicon chip installed in an 8-pin mini
dual-in-line package (DIP-8).
CIRCUIT DIAGRAM:
IC 555 Pin Diagrm of IC 555

Internal Structure of IC 555

GP GANDHINAGAR EC DEPARTMENT AE(3331102)

The connection of the pins for a DIP package is as follows:

Pin Name Purpose
1 GND Ground reference voltage, low level (0 V)
The OUT pin goes high and a timing interval starts when
2 TRIG this input falls below 1/2 of CTRL voltage (which is
typically 1/3 of VCC, when CTRL is open).
This output is driven to approximately 1.7 V below +VCC or
3 OUT
GND.
A timing interval may be reset by driving this input to GND,
but the timing does not begin again until RESET rises
4 RESET
above approximately 0.7 volts. Overrides TRIG which
overrides THR.
Provides "control" access to the internal voltage divider
5 CTRL
(by default, 2/3 VCC).
The timing (OUT high) interval ends when the voltage at
6 THR
THR is greater than that at CTRL (2/3 VCC if CTRL is open).
Open collector output which may discharge a capacitor
7 DIS
between intervals. In phase with output.
Positive supply voltage, which is usually between 3 and 15
8 VCC
V depending on the variation.

Specifications

These specifications apply to the NE555. Other 555 timers can have different
specifications depending on the grade (military, medical, etc.).
Supply voltage (VCC) 4.5 to 15 V
Supply current (VCC = +5 V) 3 to 6 mA
Supply current (VCC = +15 V) 10 to 15 mA
Output current (maximum) 200 mA
Maximum Power dissipation 600 mW
Power consumption (minimum operating) 30 mW@5V, 225 mW@15V
Operating temperature 0 to 70 °C

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

GEXPERIMENT NO: 11

AIM: TO STUDY IC 555 AS ASTABLE MULTIVIBRATOR.

APPARATUS: IC 555, CRO, Function Generator, Bread Board, Resistors,

capacitor and connecting leads.

THEORY:

Multivibrator:
A circuit designed to have zero, one, or two stable output
states.There are three types of multivibrators:

 Astable (or Free-Running ultivibrators)

 Monostable (or One-Shot)
 Bistable (or Flip- Flop)

1) Astable multivibrator – A switching circuit that has no stable output

state. The astable multivibrator is a rectangular wave oscillator. Also
referred to as a free-running multivibrator.

The IC555 timer is a 8 pin IC that can be connected to external

components for astable operation. The simplified block diagram is drawn.
The OP-AMP has threshold and control inputs. Whenever the threshold
voltage exceeds the control voltage, the high output from the OP –AMP will
set the flip-flop. The collector of discharge transistor goes to pin 7. When
this pin is connected to an external trimming capacitor, a high Q output
from the flip flop will saturate the transistor and discharge the capacitor.

When Q is low the transistor opens and the capacitor charges. The
complementary signal out of the flip-flop goes to pin 3 and output. When
external reset pin is grounded it inhibits the device. The on – off feature is
useful in many application. The lower OP- AMP inverting terminal input is
called the trigger because of the voltage divider. The non-inverting input has
a voltage of +Vcc/3, the OP-Amp output goes high and resets the flip flop.

The output frequency is,

f = 1.44/(RA + RB)C
The duty cycle is,

D = RB / (RA + 2RB) * 100%

The duty cycle is between 50 to 100% depending on RA and RB.

GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CIRCUIT DIAGRAM:

PROCEDURE:

Astable multivibrator:

1) Connect the circuit using the component values as per the

design.
2) Observe and sketch the capacitor voltage wave form (pin-6)
and output waveform (pin-3) measure the frequency and duty cycle of
the output wave form
3) Connect the circuit of fig using component values as per the
design and repeat the step 2 by adjusting both the potential meters
for duty cycle of 10%, 50% and 90% with a frequency of 1 kHz.

WAVE FORMS:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO: 12

AIM: STUDY OF IC 555 AS MONOSTABLE MULTIVIBRATOR.

APPARATUS:IC 555, CRO, Function Generator, Bread Board, Resistors,

capacitor and connecting leads.

THEORY:

Multivibrator -A circuit designed to have zero, one, or two stable

output states. There are three types of multivibrators:

1) Astable (or Free-Running Multivibrators)

2) Monostable (or One-Shot)
3) Bistable (or Flip- Flop)

Monostable multivibrator – A switching circuit with one stable output

state. Also referred to as a one-shot. The one-shot produces a signal
output pulse when it receives a valid input trigger signal.

This circuit is a monostable multivibrator, or one-shot, made with a 555

timer chip. Click the logic input on the left (the "H"), and the output goes
high for a short time, and then it goes low again.

A timing interval starts when the trigger input ("tr") is brought low.
When this happens, the 555 output goes high. This causes the capacitor to
be charged until it reaches 6.67V. Then, the timing interval ends, the
output goes low, and the capacitor is discharged through the "dis"input.

The capacitor in front of the trigger input causes the monostable to

be negative-edge triggered. If the capacitor is replaced with a wire, and the
logic input is held low too long, then the 555's output will start to oscillate.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
CIRCUIT DIAGRAM:

PROCEDURE:
1) Connect the circuit using the component values as per the
design.
2) Set the square wave 2.5V peak and 1KHz trigger input on
function generator.
3) Apply the trigger input at pin-2 through capacitor C1. Observe
both trigger input and the output of the multivibrator on CRO
simultaneously and sketch the waveforms.
4) Repeat the step 3 for trigger input of 2KHz frequency.

WAVE FORMS:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
CONCLUSION:

GEXPERIMENT NO: 13

AIM: TO STUDY ABOUT DIFFERENT POWER AMPLIFIERS.

THEORY :
Amplifier receives a signal from some pickup transducer or other input
source and provides larger version of the signal. In small signal amplifiers the
main factors are usually amplification, linearity and magnitude of gain.

Classes of Power Amplifiers:

Amplifier classes represent the amount the output signal varies over one
cycle of operation for a full cycle of input signal. So the following classes of PA
are defined as

 Class A
 Class B
 Class AB
 Class C
 Class D

Class A amplifier:

Class A amplifying devices operate over the whole of the input cycle such
that the output signal is an exact scaled-up replica of the input with no clipping.
Class A amplifiers are the usual means of implementing small signal amplifiers.
They are not very efficient. a theoretical maximum of 50% is obtainable with
inductive output coupling and only 25% with capacitive coupling.

In a Class A circuit, the amplifying element is biased so the device is

always conducting to some extent, and is operated over the most linear portion
of its characteristic curve Because the device is always conducting, even if there
is no input at all, power is drawn from the power supply. This is the chief
reason for its inefficiency.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Class B:

Class B amplifiers only amplify half of the input wave cycle. As such
they create a large amount of distortion, but their efficiency is greatly improved
and is much better than Class A. Class B has a maximum theoretical efficiency of
78.5% (i.e., π/4). This is because the amplifying element is switched off
altogether half of the time, and so cannot dissipate power. • A single Class B
element is rarely found in practice, though it can be used in RF power amplifier
where the distortion levels are less important. However Class C is more
commonly used for this.

Class AB:
A practical circuit using Class B elements is the complementary pair
or "push–pull" arrangement. Here, complementary or quasi-complementary
devices are used to each amplify the opposite halves of the input signal, which
is then recombined at the output. This arrangement gives excellent efficiency,
but can suffer from the drawback that there is a small mismatch at the "joins"
between the two halves of the signal.. • Class AB sacrifices some efficiency over
class B in favor of linearity, so will always be less efficient (below 78.5%). It is
typically much more efficient than class A.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Class C:

Class C amplifiers conduct less than 50% of the input signal and the
distortion at the output is high, but high efficiencies (up to 90%) are possible.
Some applications (for example, megaphones) can tolerate the distortion. A
much more common application for Class C amplifiers is in RF transmitters,
where the distortion can be vastly reduced by using tuned loads on the
amplifier stage. The input signal is used to roughly switch the amplifying device
on and off, which causes pulses of current to flow through a tuned circuit.

Class D:
Class D amplifiers are much more efficient than Class AB power
amplifiers. As such, Class D amplifiers do not need large transformers and
heavy heatsinks, which means that they are smaller and lighter in weight than
an equivalent Class AB amplifier. All power devices in a Class D amplifier are
operated in on/off mode. These amplifiers use pulse width modulation,

Comparison of Amplifier classes:

GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
TEG AIRCU T AN A PLI A O
EXPERIMENT NO: 14
AIM: TO STUDY TRANSFORMER COUPLED CLASS-A POWER AMPLIFIER.
THEORY:
Transformer coupled class A amplifier
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

EXPERIMENT NO. 15
AIM: TO STUDY AND DETERMINE THE EFFICIENCY OF PUSH-PULL
POWER AMPLIFIER.
THEORY:

Series fed class A amplifiers

It is a fixed bias circuit.

DC bias operation

 The DC bias set by Vcc and Rb.

 Collector current IC=Βib.
 Collector –emitter voltage.
 VCE=VCC-ICRC.

Load line

Power considerations:

 The power into an amplifier is provided by the power supply

 With no input supply, current drawn is collector bias current ICq.
 pi(dc)=VCCICq
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Output power:

The output voltage and current varying around the bias point provide ac power
to the load.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Class B Amplifier operation:

Class B operation is provided when the dc bias leaves the transistor biased Just
off, the transistor turning on when the ac signal is applied. This is essentially no
bias and conducts for only one half cycles. To obtain output for full cycle, it is
required to use two transistors and have each conduct on opposite half-cycles,
the combined operation providing a full cycle of output on opposite half cycles
of output signal. Since one part of the circuit pushes the signal high during one
half cycles and other part pulls the signal low during the other half cycle, the
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
circuit is referred to as push-pull circuit. Class B operation provides greater
efficiency than was possible using single transistor in class A operation.
Class B push-pull:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)
EXPERIMENT NO. 16

AIM: TO STUDY ABOUT PUSH-PULL POWER AMPLIFIER.

THEORY:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

WORKING:
Every transistor will conduct for half cycle. Single input signal is applied to the
base of both transistors NPN transistor will be biased in conduction for positive
half cycle of the input. During negative half cycle PNP transistor is biased into
conduction when input goes to negative.
Disadvantages
• One disadvantage is that the need of two separate voltage supplies.
• Cross over distortion in the output signal.
• This cross over distortion is referred to as the nonlinearity in the output
signal during cross over from positive to negative or vice-versa. This is due to
the fact that, none of the transistors are on near zero input and thus output
does not follow input.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Complementary symmetry push-pull circuit using Darlington transistors:

• This circuit provides higher output current and lower output resistance.
• Here the load resistance is matched by low output resistance of the driving
source.

Quasi complementary push-pull transformer less power amplifier:

• In practical circuit it is preferred to use npn for both high-current-output

devices.
• Practical means of obtaining complementary operation while using same,
matched transistors for the output is provided by a quasi complementary
circuit.
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

Here push-pull operation is achieved by using complementary transistors (Q1

and Q2) before the matched NPN output transistors (Q3 and Q4).Q1 and Q3
forms a Darlington connection. Q2 and Q4 form a feedback connection, which
similarly provides low impedance to drive the load. Resistor R2 can be
adjusted to minimize cross over distortion by adjusting the dc bias condition.
This is the most popular form of power amplifier used today.

CONCLUSION:
GP GANDHINAGAR EC DEPARTMENT AE(3331102)

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