Professional Documents
Culture Documents
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
PREFACE
Purpose of This Manual .................................................................. xv
Intended Audience .......................................................................... xv
Manual Contents ........................................................................... xvi
What’s New in This Manual ........................................................... xvi
Technical or Customer Support ..................................................... xvii
Supported Processors ..................................................................... xvii
Product Information .................................................................... xviii
Analog Devices Web Site ........................................................ xviii
VisualDSP++ Online Documentation ....................................... xix
Technical Library CD ............................................................... xix
Related Documents ................................................................... xx
Notation Conventions .................................................................... xxi
INDEX
• Other features
D JTAG ICE 14-pin header
D Blackfin power measurement jumpers
For information about the hardware components of the EZ-Board, refer
to “ADSP-BF518F EZ-Board Hardware Reference” on page 2-1.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the ADSP-BF51x Blackfin Processor Hardware Reference and
Blackfin Processor Instruction Set Reference) that describe your target
architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
• Chapter 1, “Using ADSP-BF518F EZ-Board” on page 1-1
Describes EZ-Board functionality from a programmer’s perspective
and provides an easy-to-access memory map.
• Chapter 2, “ADSP-BF518F EZ-Board Hardware Reference” on
page 2-1
Provides information on the EZ-Board hardware components.
• Appendix A, “ADSP-BF518F EZ-Board Bill Of Materials” on
page A-1
Provides a list of components used to manufacture the EZ-Board.
• Appendix B, “ADSP-BF518F EZ-Board Schematic” on page B-1
Provides the resources to allow EZ-Board board-level debugging or
to use as a reference design. Appendix B is part of the online Help.
Supported Processors
This evaluation system supports Analog Devices ADSP-BF518F Blackfin
embedded processors.
Product Information
Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.
File Description
.htm or Dinkum Abridged C++ library and FLEXnet License Tools software documenta-
.html tion. Viewing and printing the .html files requires a browser, such as Internet
Explorer 6.0 (or higher).
.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the
.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).
Technical Library CD
The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals, Visu-
alDSP++ software manuals, and hardware tools manuals for the following
processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and
ADSP-219x.
To order the technical library CD, go to http://www.analog.com/proces-
sors/technical_library, navigate to the manuals page for your
processor, click the request CD check mark, and fill out the order form.
Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.
Related Documents
For information on product related development software, see the follow-
ing publications.
VisualDSP++ Assembler and Preprocessor Manuals Description of the assembler function and
commands.
VisualDSP++ C/C++ Complier and Library Man- Description of the complier function and
ual for Blackfin Processors commands for Blackfin processors.
VisualDSP++ Linker and Utilities Manual Description of the linker function and com-
mands.
VisualDSP++ Device Drivers and System Services Description of the device drivers’ and system
Manual for Blackfin Processors services’ functions and commands.
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example Description
Close command Titles in reference sections indicate the location of an item within the
(File menu) VisualDSP++ environment’s menu system (for example, the Close com-
mand appears on the File menu).
{this | that} Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that] Optional items in syntax descriptions appear within brackets and sepa-
rated by vertical bars; read the example as an optional this or that.
[this,…] Optional item lists in syntax descriptions appear within brackets delim-
ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.
.SECTION Commands, directives, keywords, and feature names are in text with
letter gothic font.
Example Description
Note: For correct operation, ...
L
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
a
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
[
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
Package Contents
Your ADSP-BF518F EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF518F EZ-Board
• VisualDSP++ Installation Quick Reference Card
• CD containing:
D VisualDSP++ software
D ADSP-BF518F EZ-Board debug software
D USB driver files
D Example programs
D ADSP-BF518F EZ-Board Evaluation System Manual
• Universal 5.0V DC power supply
• 256 MB SD card
• 7-foot Ethernet patch cable
• Two 6-foot 3.5 mm male-to-male audio cables
• 18-inch SMA to SMA coaxial cable
If any item is missing, contact the vendor where you purchased your
EZ-Board or contact Analog Devices, Inc.
Default Configuration
The ADSP-BF518F EZ-Board board is designed to run outside your per-
sonal computer as a stand-alone unit. You do not have to open your
computer case.
The EZ-Board evaluation system contains ESD (electrostatic discharge) sensi-
tive devices. Electrostatic charges readily accumulate on the human body and
equipment and can discharge without detection. Permanent damage may
occur on devices subjected to high-energy discharges. Proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
Store unused EZ-Board in the protective shipping package.
When removing the EZ-Board from the package, handle the board care-
fully to avoid the discharge of static electricity, which can damage some
components. Figure 1-1 shows the default jumper and switch settings,
connector locations, and LEDs used in installation. Confirm that your
board is in the default configuration before using the board.
EZ-Board Installation
For correct operation, install the software in the order presented in the
VisualDSP++ Installation Quick Reference Card. Substitute instructions in
step 3 with instructions in this section.
There are two options to connect the EZ-Board hardware to a personal
computer (PC) running VisualDSP++ 5.0: via an Analog Devices emula-
tor or via a standalone debug agent module. The standalone debug agent
allows a debug agent to interface to the ADSP-BF518F EZ-Board. The
standalone debug agent is shipped with the kit.
a wall
The debug agent can be used only when power is supplied from the
adaptor.
1. Attach the standalone debug agent to connectors P1 (labeled JTAG)
and ZP1 on the backside of the EZ-Board, watching for the keying
pin of P1 to connect correctly. Plug the 5V adaptor into connector
J3 (labeled 5V).
2. Plug one side of the provided USB cable into the USB connector of
the standalone debug agent. Plug the other side of the cable into a
USB port of the PC running VisualDSP++ 5.0 update 5 or later.
3. Verify that the yellow USB monitor LED on the standalone debug
agent (LED4, located on the back side of the board) is lit. This signi-
fies that the board is communicating properly with the host PC
and ready to run VisualDSP++.
down the Ctrl key while starting VisualDSP++. Do not release the
Ctrl key until the Session Wizard appears on the screen. Go to
step 3.
2. To connect to a new EZ-KIT Lite session, start Session Wizard by
selecting one of the following.
• From the Session menu, New Session.
• From the Session menu, Session List. Then click New Ses-
sion from the Session List dialog box.
• From the Session menu, Connect to Target.
3. The Select Processor page of the wizard appears on the screen.
Ensure Blackfin is selected in Processor family. In Choose a target
processor, select ADSP-BF518F. Click Next.
4. The Select Connection Type page of the wizard appears on the
screen. For standalone debug agent connection, select EZ-KIT Lite
and click Next. For emulator connection select Emulator, and click
Next
5. The Select Platform page of the wizard appears on the screen.
For standalone debug agent connection, ensure that the selected
platform is ADSP-BF518F EZ-KIT Lite via Debug Agent. For
emulator connection, choose the type of emulator that is connected.
Specify your own Session name for the session or accept the default
name.
The session name can be a string of any length; although, the box
displays approximately 32 characters. The session name can
include space characters. If you do not specify a session name,
VisualDSP++ creates a session name by combining the name of the
selected platform with the selected processor. The only way to
change a session name later is to delete the session and open a new
session.
Click Next.
6. The Finish page of the wizard appears on the screen. The page dis-
plays your selections. Check the selections. If you are not satisfied,
click Back to make changes; otherwise, click Finish. VisualDSP++
creates the new session and connects to the EZ-Board. Once con-
nected, the main window’s title is changed to include the session
name set in step 5.
L Toor select
disconnect from a session, click the disconnect button
Session–>Disconnect from Target.
To delete a session, select Session –> Session List. Select the ses-
sion name from the list and click Delete. Click OK.
Memory Map
The ADSP-BF518F processor has internal static random access memory
(SRAM) used for instructions and data storage. See Table 1-1. The inter-
nal memory details can be found in the ADSP-BF51x Blackfin Processor
Hardware Reference.
The ADSP-BF518F EZ-Board includes four types of external memory:
synchronous dynamic random access memory (SDRAM), serial peripheral
interconnect (SPI) flash, parallel flash, and eMMC. See Table 1-2. For
more information about a specific memory type, go to the respective sec-
tion in this chapter.
SDRAM Interface
The ADSP-BF518F processor connects to a 64 MB Micron
MT48LC32M16A2TG-75 chip through the external bus interface unit
(EBIU). The SDRAM chip can operate at a maximum clock frequency of
80 MHz, which is the ADSP-BF518F processor limitation.
With a VisualDSP++ session running and connected to the EZ-Board via
the USB standalone debug agent, the SDRAM registers are configured
automatically each time the processor is reset. The values are used when-
ever SDRAM is accessed through the debugger (for example, when
viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, select Target
Options from the Settings menu in VisualDSP++ and uncheck Use XML
reset values. For more information on changing the reset values, refer to
the online Help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the Visu-
alDSP++ online Help for “reset values”.
Flash memory is pre-loaded with boot code for the power-on-self test
(POST) program. For more information, refer to “Power-On-Self Test”
on page 1-24. Flash memory also is preloaded with configuration flash
information, which contains board revision, BOM revision, and other
data.
By default, the EZ-Board boots from the 16-bit parallel flash memory.
The processor boots from flash memory if the boot mode select switch
(SW1) is set to position 1 (see “Boot Mode Select Switch (SW1)” on
page 2-8).
Flash memory code can be modified. For instructions, refer to the online
Help and example program included in the EZ-Board installation
directory.
For more information about the parallel flash device, refer to the Num-
onyx Web site: http://www.numonyx.com/.
eMMC Interface
The ADSP-BF518F processor is equipped with a removable storage inter-
face (RSI), which allows the 2 Gb Micron eMMC device to be attached
gluelessly to the processor. The eMMC device is attached via the proces-
sor’s specific RSI control and data lines. The eMMC device shares pins
with the secure digital (SD) interface, push buttons, analog-to-digital con-
verter (ADC) and expansion interface II.
The RSI signals can be disconnected from the eMMC device by turning
switches SW20 and SW21 all OFF. See “eMMC Enable Switch (SW20–21)”
on page 2-15 for more information.
For more information about the eMMC device, refer to the Micron Web
site: http://www.micron.com/.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the eMMC device.
SD Interface
The ADSP-BF518F processor has a secure digital interface. The SD inter-
face consists of a clock pin, a command pin, and a four-bit data bus. The
SD interface of the processor connects gluelessly to the on-board SD con-
nector. The SD interface is attached via the processor’s specific RSI
control and data lines. The interface shares pins with the eMMC interface,
codec, and expansion interface II. The memory can be written to in both
one-bit and four-bit modes. For more information, refer to “SD Connec-
tor (J13)” on page 2-26. An example program is included in the EZ-Board
installation directory to demonstrate how to setup and access the SD
interface.
SPI Interface
The ADSP-BF518F processor has two serial peripheral interface (SPI)
ports with multiple chip select lines. The SPI0 port connects directly to
serial flash memory, audio codec, Ethernet IC, and the expansion
interface II.
Serial flash memory is a 16 Mb ST M25P16 device, which is selected
using the SPISEL2 line of the processor.
SPI flash memory is factory programmed with Das U-Boot—the universal
boot loader. Das U-Boot (U-Boot for short) is open source firmware for
embedded processors, including the ADSP-BF518F Blackfin processors.
U-Boot can load files from a variety of peripherals, such as a serial connec-
tion, an Ethernet network connection, or flash memories. U-Boot is
executed at system reset, which automatically loads up another application
(such as the Linux kernel or a stand alone application). U-Boot can parse
many types of files on many types of storage devices.
If the processor pins are needed for the expansion interface II, disconnect
the rotary encoder switch via the three-position rotary enable switch
(SW19). For more information, see “Encoder Enable Switch (SW19)” on
page 2-14.
An example program is included in the EZ-Board installation directory to
demonstrate how to set up and access the rotary encoder interface.
Ethernet Interface
The ADSP-BF518F processor has an integrated Ethernet MAC with
media independent interface (MII) which connects to an external PHY.
The EZ-Board provides a Micrel KSZ8893M Integrated 3-Port 10/100
Managed Switch with PHYs, fully compliant with IEEE 802.3u standards.
The KSZ8893M chip supports 10BASE-T and 100BASE-TX operations.
The part is attached gluelessly to the processor.
The Ethernet signals are shared with the PPI signals connected to the
expansion interface II.
The Ethernet mode is set by three switches. Switch SW7 controls the con-
figuration of the port 1 connector. SW7 configures the flow control,
duplex, speed, and auto-negotiation. Switch SW18 controls the configura-
tion of the port 2 connector. SW18 configures the flow control, duplex,
speed, auto-negotiation, auto MDI/MDI-X, and MDI/MDI-X settings.
Switch SW8 controls the Ethernet IC configuration. SW8 configures the
flow control, hardware pin overwrite, and serial bus mode. See “Ethernet
Port 1 Configuration Switch (SW7)” on page 2-11, “Ethernet Port 2 Con-
figuration Switch (SW18)” on page 2-14, and “Ethernet Configuration
Switch (SW8)” on page 2-11 for more information.
The Ethernet chip is pre-loaded with a MAC address. The MAC address
for the EZ-Board is stored in the configuration flash section of the parallel
flash memory and can be found on a sticker on the bottom side of the
board.
The PHY portion of the Ethernet chip connects to a Pulse HX1188 mag-
netics, then to standard RJ-45 Ethernet connectors (J14 and J15). For
more information, see “Ethernet Connectors (J14–15)” on page 2-27.
Example programs are included in the EZ-Board installation directory to
demonstrate how to use the Ethernet interface.
Audio Interface
The audio interface of the EZ-Board consists of a low-power stereo codec,
SSM2602, with an integrated headphone driver and associated passive
components. There are two inputs, a stereo line in, and a mono micro-
phone, as well as two outputs, a headphone, and a stereo line out. The
codec has integrated stereo ADCs, digital-to-analog converters (DACs),
and requires minimal external circuitry.
The codec connects to the ADSP-BF518F processor via the processor’s
serial port 0. The SPORT0 is disconnected from the codec by turning switch
SW15 OFF, which enables SPORT0 for the SD/eMMC interface or the expan-
sion interface II. See “SPORT0 ENBL Switch (SW15)” on page 2-13 for
more information.
The control interface of the codec is selected by switching SW16 between
the 2-wire interface (TWI) and SPI. The board’s default is SPI mode.
Refer to“SPI/TWI Switch (SW16)” on page 2-13 for more information.
Mic gain values of 14 dB, 0 dB, or –6 dB are selectable through switch
SW5. For more information, see “MIC Gain Switch (SW5)” on page 2-10.
J4 and J5 are 3.5 mm connectors for the audio portion of the board. J5
connects the mic on the top portion and line-in on the bottom. J4 con-
nects the headphone on the top portion and line-out on the bottom. If
there is no 3.5 mm cable plugged into the bottom of either J4 or J5, the
signals are looped back inside the connector. For more information, see
“Dual Audio Connectors (J4–5)” on page 2-26.
For testing, SW6 positions 1&2 connect the MICIN signal to either the left
or right headphone. Do not connect the left and right to the MICIN signal
at the same time—only position 1 or 2 of SW6 should be ON at the same
time. For more information, see “Mic/HP LPBK, Audio Mode Switch
(SW6)” on page 2-10.
The EZ-Board is shipped with two 3.5 mm cables, which allow you to run
the example programs provided in the EZ-Board installation directory and
learn about the audio interface.
ADC Interface
The ADC interface of the EZ-Board consists of a dual, 12-bit, high-speed,
low-power, successive approximation analog-to-digital converter. The
device contains two converters, each preceded by a 3-channel multiplexer,
a low-noise, wide-bandwidth track, and holds an amplifier that can handle
input frequencies in excess of 30 MHz. There are four differential and
four single-ended inputs on the EZ-Board that are accessed via SMA
connectors.
The ADC connects to the ADSP-BF518F processor via the processor’s
serial port 1. SPORT1 is disconnected from the ADC by turning switch SW4
OFF, which enables SPORT1 for the expansion interface II or for the
multi-function pins, in which case the port’s signals can be used for the
RSI or as push buttons. See “SPORT1 Enable Switch (SW4)” on page 2-9
for more information.
The ADC range is controlled by jumper JP4. This jumper selects whether
the input range for the ADC is 2.5V or 5 V. The max voltage range for a
signal connected to the SMA connector is 0–5V. Any voltage outside of
this range can damage the EZ-Board. For more information, see “ADC
Range Jumper (JP4)” on page 2-17.
Jumpers JP17–28 are used to connect the SMA connector to the ADC
input. When there is no input connected to the SMA connector, the
jumper should have the shunt installed on pins 2&3. This setting con-
nects the signal going to the ADC input to ground and keeps the noise
level low. When an input signal is connected to the SMA connector, the
shunt should be installed on position 1&2. For more information, see
“ADC Channel Select Jumpers (JP17–28)” on page 2-19.
For testing, switches SW22–23 connect an audio output signal from the
codec to the input channels of the ADC. Do not connect to the SMA con-
nectors and have these switches ON at the same time. For more
information, see “Mic/HP LPBK, Audio Mode Switch (SW6)” on
page 2-10.
UART Interface
The ADSP-BF518F processor has two built-in universal asynchronous
receiver transmitters (UARTs). UART0—1 share the processor’s pins with
other peripherals on the EZ-Board.
UART0 has full RS-232 functionality via the Analog Devices 3.3V
ADM3202 line driver and receiver (U21). When using UART0, do not set
switch SW10 position 4 to ON. This setting enables UART loopback and
should be installed only when running the POST program.
UART0 and UART1 are connected to the expansion interface II connectors.
For more information, see “Expansion Interface II Connectors (P2 and
P4)” on page 2-27.
RTC Interface
The ADSP-BF518F processor has a real-time clock (RTC) and a watchdog
timer. Typically, the RTC interface is used to implement a real-time
watchdog or a life counter of the time elapsed since the last system reset.
The EZ-Board is equipped with a Panasonic CR1632 lithium coin and 3V
battery supplying 125 mAh. The 3V battery and 3.3V supply of the board
connect to the RTC power pin of the processor. When the EZ-Board is
powered, the RTC circuit uses the board power to supply voltage to the
RTC pin. When the EZ-Board is not powered, the RTC circuit uses the
lithium battery to maintain power to the RTC pin. After removing the
mylar, the battery lasts for about one year with the EZ-Board unpowered.
Example programs are included in the EZ-Board installation directory to
demonstrate the RTC features.
JTAG Interface
The JTAG connector (P1) allows the standalone debug agent to connect a
debug session to the ADSP-BF518F processor. The debug agent operates
only when the external 5V wall adaptor is used (J3). When operating the
EZ-Board from a battery or USB bus power, the debug agent is not
powered.
The standalone debug agent can be removed, and an external emulator
can be attached to the EZ-Board. Be careful not to damage the connectors
when removing the debug agent. The emulator connects to P1 on the back
side of the board. See “EZ-Board Installation” on page 1-4 for more
information.
For more information about emulators, contact Analog Devices or go to:
http://www.analog.com/processors/blackfin/evaluationDevelop-
ment/crosscore/.
Expansion Interface II
The expansion interface II allows an Analog Devices EZ-Extender or a
custom-design daughter board to be tested across various hardware plat-
forms that have the same expansion interface.
The expansion interface II implemented on the ADSP-BF518F EZ-Board
consists of four connectors, three of which are 0.1 in. shrouded headers
(P2—4), and the last of which is a Samtec QMS series header (J1). The con-
nectors contain a majority of the ADSP-BF518F processor signals. For
pinout information, go to “ADSP-BF518F EZ-Board Schematic” on
page B-1. The mechanical dimensions of the expansion connectors can be
obtained by contacting Technical or Customer Support.
For more information about daughter boards, visit the Analog Devices
Web site at:
http://www.analog.com/processors/blackfin/evaluationDevelop-
ment/crosscore/.
L Analog Devices does not support and is not responsible for the
effects of additional circuitry.
Power Measurements
Several locations are provided for measuring the current draw from vari-
ous power planes. Precision 0.1 ohm shunt resistors are available on the
VDDINT, VDDEXT, VDDMEM, and VDDFLASH voltage domains.
For current draw measuments, the associated jumper (P8—11) should be
removed. Once the jumper is removed, the voltage across the resistor can
be measured using an oscilloscope. Once voltage is measured, current can
be calculated by dividing the voltage by 0.1. For the highest accuracy, a
differential probe should be used for measuring voltage across the resistor.
For more information, see “VDDINT Power Jumper (P8)” on page 2-19,
“VDDEXT Power Jumper (P9)” on page 2-19, “VDDMEM Power
Jumper (P10)” on page 2-20, and “VDDFLASH Power Jumper (P11)” on
page 2-20.
Power-On-Self Test
The power-on-self-test program (POST) tests all EZ-Board peripherals
and validates functionality as well as connectivity to the processor. Once
assembled, each EZ-Board is fully tested for an extended period of time
with a POST. All EZ-Boards are shipped with the POST preloaded into
one of its on-board flash memories. The POST is executed by resetting the
board and pressing the proper push button(s). The POST also can be used
as a reference for a custom software design or hardware troubleshooting.
Note that the source code for the POST program is included in the Visu-
alDSP++ installation directory along with the readme text file, which
describes how the EZ-Board is configured to run a POST.
Example Programs
Example programs are provided with the ADSP-BF518F EZ-Board to
demonstrate various capabilities of the product. The programs are
installed with the VisualDSP++ software and can be found in the
<install_path>\Blackfin\Examples\ADSP-BF518F EZ-Board directory.
Refer to the readme file provided with each example for more
information.
System Architecture
This section describes the processor’s configuration on the EZ-Board
(Figure 2-1).
64 MB 4 MB
SDRAM Flash
(32M x 16) (2M x 16 )
32.768 KHz SD
3.3 Volts 3.3 Volts
Oscillator
3.3 volt Connector
eMMC
RTC EBIU RSI
2GB
JTAG
IDC Conn
Port
UP/DN
CNTR
14 Pin 0.1
Rotary
High Speed I/O
Low Speed Group
Micrel ADSP-BF518F
Low Speed
Low Speed
Group 2A
Group 1A
Processor
MAC
LEDs KSZ8893
400 MHz
1B
(8)
3.3 Volts 176-lead LQFP LEDs (3)
GPIO
PBs (2)
RJ45 RJ45
UARTs CLKIN SPI SPORT TWI SPORT
16 Mb
SPI Flash
3.3 Volts
12 bit 4
RS-232 25 MHz SSM2602 3 Channel A/D Differential
TX/RX Oscillator Codec AD7266 Inputs
3.3 Volts 3.3 Volts
3.3 Volts
4 Single
Ended
RS-232 Inputs
Female
12 MHz
Mic Aud Head Aud
Oscillator
In In Out Out
3.3 Volts
Programmable Flags
The processor has 40 general-purpose input/output (GPIO) signals spread
across three ports (PF, PG, and PH). The pins are multi-functional and
depend on the ADSP-BF518F processor setup. The following tables show
how the programmable flag pins are used on the EZ-Board.
• PF programmable flag pins – Table 2-1
• PG programmable flag pins – Table 2-2
• PH programmable flag pins – Table 2-3
L entire
The selected position of is marked by the notch down the
SW1
rotating portion of the switch, not the small arrow.
0 Reserved
1 (ON) ~AMS0
2 (ON) ~AMS1
3 (ON) ~AMS2
4 (ON) ~AMS3
send a high (1) to the processor. The GPIO enable switch (SW2) discon-
nects the push buttons from the corresponding push button signals. Refer
to “PB Enable Switch (SW2)” on page 2-8 for more information.
Jumpers
This section describes functionality of the configuration jumpers.
Figure 2-2 shows the jumper locations.
to parallel flash. When using SPI flash, the available memory that is acces-
sible on parallel flash is reduced from 4 MB to 3 MB. By default, JP16 is
not installed.
LEDs
This section describes the on-board LEDs. Figure 2-4 shows the LED
locations.
LED1 PH3
LED2 PH5
LED3 PH6
Connectors
This section describes connector functionality and provides information
about mating connectors. The connector locations are shown in Figure 2-5.
Connectors shown with a dotted line are on the backside of the PCB
Mating Connector
Mating Cable
SD Connector (J13)
Mating Connector
Mating Connector
1 1 74LVC14A U6 TI 74LVC14AD
SOIC14
1 1
2 2
ADSP-BF518F EZ-BOARD
SCHEMATIC
3 3
A B C D
A B C D
3.3V
A[1:19]_Z
U12 D[0:15]_Z
A1_Z 107 76 D0_Z
A1 D0
A2_Z 106 74 D1_Z
A2 D1
A3_Z 105 73 D2_Z
A3 D2
A4_Z 103 72 D3_Z
A4 D3
A5_Z 102 71 D4_Z R4 R5
A5 D4 U12 1.2K 1.2K
A6_Z 101 70 D5_Z 0402 0402
A6 D5
A7_Z 97 69 D6_Z
A7 D6
1 A8_Z 96 66 D7_Z 19
1
A8 D7 ETXD2 PF0/ETXD2/PPID0/SPI1_SSEL2/TACLK6
A9_Z 94 65 D8_Z 18 173 R314 33
A9 D8 ERXD2 PF1/ERXD2/PPID1/PWM_AH/TACLK7 PJ0/SCL 0402 SCL
A10_Z 93 64 D9_Z 13 172 R313 33
A10 D9 ETXD3 PF2/ETXD3/PPID2/PWM_AL PJ1/SDA 0402 SDA
A11_Z 92 62 D10_Z 12
A11 D10 ERXD3 PF3/ERXD3/PPID3/PWM_BH/TACLK0
A12_Z 91 61 D11_Z 11
A12 D11 ERXCLK PF4/ERXCLK/PPID4/PWM_BL/TACLK1
A13_Z 86 60 D12_Z 10
A13 D12 ERXDV PF5/ERXDV/PPID5/PWM_CH/TACI0 162
A14_Z 85 58 D13_Z 6 PH0/DR1PRI/SPI1_SS/RSI_DATA4 PB1/DR1PRI/MMC_D4_Z
A14 D13 COL PF6/COL/PPID6/PWM_CL/TACI1 161
A15_Z 84 57 D14_Z 5 PH1/RFS1/SPI1_MISO/RSI_DATA5 PB2/RFS1/MMC_D5_Z
A15 D14 SPI0_SSEL1 PF7/SPI0_SSEL1/PPID7/PWM_SYNC 160
A16_Z 81 56 D15_Z 4 PH2/RSCLK1/SPI1_SCK/RSI_DATA6 RSCLK1/MMC_D6_Z
A16 D15 MDC PF8/MDC/PPID8/SPI1_SSEL4 159
A17_Z 80 3 PH3/DT1PRI/SPI1_MOSI/RSI_DATA7 ADC_A0/LED1/MMC_D7/OTP_EN_Z
A17 MDIO PF9/RMIIMDIO/PPID9/TMR2 156
A18_Z 78 108 174 PH4/TFS1/AOE/SPI0_SSEL3/CUD SPI0_SSEL3/CUD_Z
A18 ABE1#/SDQM1 ABE1#/SDQM1_Z ETXD0 PF10/ETXD0/PPID10/TMR3 155
A19_Z 77 109 171 PH5/TSCLK1/ARDY/ECLK/CDG CDG/ADC_A1/LED2_Z
A19 ABE0#/SDQM0 ABE0#/SDQM0_Z ERXD0 PF11/ERXD0/PPID11/PWM_AH/TACI3 154
168 PH6/DT1SEC/UART1_TX/SPI1_SSEL1/CZM CZM/ADC_A2/LED3_Z
ETXD1 PF12/ETXD1/PPID12/PWM_AL 153
119 167 PH7/DR1SEC/UART1_RX/TMR7/TACI2 DR1SEC_Z
SCKE_Z SCKE ERXD1 PF13/ERXD1/PPID13/PWM_BH
113 166
SWE_Z SWE ETXEN PF14/ETXEN/PPID14/PWM_BL
110 120 165
SA10_Z SA10 AMS1 AMS1_Z RMII_PHYINT PF15/RMII_PHYINT/PPID15/PWM_SYNC
114 123
SCAS_Z SCAS AMS0 AMS0_Z
115 48
SRAS_Z SRAS MIICRS/HWAIT PG0/MIICRS/RMIICRS/HWAIT/SPI1_SSEL3
118 47
SMS_Z SMS 121 ERXER PG1/ERXER/DMAR1/PWM_CH
3.3V ARE ARE_Z 39
143 122 MIITXCLK PG2/MIITXCLK/RMIIREF_CLK/DMAR0/PWM_CL
DSP_CLKIN CLKIN AWE AWE_ZR3 38
2 144 33 DR0PRI/SD_D0_Z PG3/DR0PRI/RSI_DATA0/SPI0_SSEL5/TACLK3 2
XTAL 0402 37
125 RSCLK0/SD_D1_Z PG4/RSCLK0/RSI_DATA1/TMR5/TACI5
CLKOUT CLKOUT 36
RFS0/SD_D2_Z PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK
141 34
DSP_RTXI RTXI TFS0/SD_D3_Z PG6/TFS0/RSI_DATA3/TMR0/PPIFS1
R1 140 117 33
10K DSP_RTXO RTXO GND TEST DT0PRI/SD_CMD_Z PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2
0402 135 32
PG PG TSCLK0/SD_CLK_Z PG8/TSCLK0/RSI_CLK/TMR6/TACI6
31
TP10 UART0_TX_Z PG9/DT0SEC/UART0_TX/TMR4
147 130
NMI EXT_WAKE R199 WAKE 28
TP9 UART0_RX_Z PG10/DR0SEC/UART0_RX/TACI4
127 33
NMI NC 0402 27
146 150 AMS2_Z PG11/SPI0_SS/AMS[2]/SPI1_SSEL5/TACLK2
RESET RESET CLKBUF CLKBUF 26
SPI0_SCK_Z PG12/SPI0_SCK/PPICLK/TMRCLK
ADSP-BF518F 25
LQFP176_SOCKET SPI0_MISO_Z PG13/SPI0_MISO/TMR0/PPIFS1
21
SPI0_MOSI_Z PG14/SPI0_MOSI/TMR1/PPIFS2/PWM_TRIPB
R325 33 20
R202 AMS3/SPI0_SEL2 0402 PG15/SPI0_SSEL2/PPIFS3/AMS[3]
0
0402
3.3V "BOOT MODE" 3.3V
SW1
3.3V 42 1 C
BMODE0 2
3 1
41 2
54 BMODE1
TRST TRST 4 0
R11 40 4
10K 55 BMODE2 5 7
0402 TMS TMS 6
3 R12 51 3
C1 U19 4 33 R9 EMU EMU SWT027
0.01UF VDD 0402 0 53 ROTARY
0402 1 3 0402 TCK TCK
OE OUT DSP_CLKIN 50
GND TDO TDO R7 R8 R6
25MHZ 2 52 4.7K 4.7K 4.7K
OSC003 TDI TDI 0402 0402 0402
ADSP-BF518F
LQFP176_SOCKET
3.3V
A B C D
A B C D
VDDEXT
1 1
VDDEXT
C7 C37 C6 C5 C4 C39 C8 C22 C23 C21 C24 C38
U12 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0805 0805 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
7 1
VDDEXT1 GND1
24 2
VDDEXT2 GND2
35 15
VDDEXT3 GND3
49 22
VDDEXT4 GND4
128 43
VDDEXT5 GND5
129 44
VDDEXT6 GND6
136 45
VDDEXT7 GND7
145 46
VDDEXT8 GND8 VDDMEM
148 67
VDDEXT9 GND9
158 83
VDDEXT10 GND10
VDDMEM 170 87
VDDEXT11 GND11
88
GND12
59 89 C10 C16 C9 C25 C19 C18 C20 C17 C27 C26
VDDMEM1 GND13 10UF 10UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
68 90 0805 0805 0402 0402 0402 0402 0402 0402 0402 0402
VDDMEM2 GND14
75 99
VDDMEM3 GND15
82 111
VDDMEM4 GND16
95 131
VDDMEM5 GND17
2 104 132 2
VDDMEM6 GND18
112 133
VDDINT VDDMEM7 GND19
124 134
VDDMEM8 GND20
137
GND21
14 139
VDDINT1 GND22
23 149 VDDINT
VDDINT2 GND23
30 151
VDDINT3 GND24
63 157
VDDINT4 GND25
79 163
VDDINT5 GND26
98 169 C15 C14 C13 C12 C11 C31 C30 C32 C29 C33 C28 C36
VDDINT6 GND27 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
100 175 0805 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
VDDINT7 GND28
116 176
VDDINT8 GND29
138 177
VDDINT9 GND30
152
VDDFLASH VDDINT10
3.3V 164
VDDINT11
D1
MA3X717E 16
20MA VDDFLASH1
DIO005 17
VDDFLASH2
29 VDDFLASH
J12 VDDFLASH3
126
2 1 VDDFLASH4
3 C34 3
0.01UF 142
0402 VPPOTP VDDOTP VDDRTC
BATT_COIN16MM C41 C42 C43 C44 C45
BATTHOLDER 10UF 0.1UF 0.1UF 0.1UF 0.1UF
9 0805 0402 0402 0402 0402
VDDOTP
8
VPPOTP
"RTC BATTERY"
ADSP-BF518F
C40 C35 LQFP176_SOCKET
0.1UF 0.01UF
0603 0402
A B C D
A B C D
(2M x 16)
U14
3.3V A[1:19]
D[0:15]_ZZ
A1 23 2 D0_ZZ
A0 DQ0
1 A2 24 4 D1_ZZ 1
A1 DQ1
A3 25 5 D2_ZZ
SW3: FLASH ENABLE A2 DQ2
J5
U5 A4 26 7 D3_ZZ
A[1:19] D[0:15] A3 DQ3
VDD
A1 G2 G3 D0 A5 29 8 D4_ZZ
POS. FROM TO DEFAULT ALTERNATE FUNCTION / OFF MODE A0 D0 A4 DQ4
A2 F2 K3 D1 A6 30 10 D5_ZZ
A1 D1 A5 DQ5
1 DSP (U12) FLASH (U5) ON Expansion Interface A3 E2 G4 D2 A7 31 11 D6_ZZ
A2 D2 A6 DQ6
A4 C2 K4 D3 A8 32 13 D7_ZZ
2 DSP (U12) FLASH (U5) ON Expansion Interface A3 D3 A7 DQ7
A5 D2 K5 D4 A9 33 42 D8_ZZ
A4 D4 A8 DQ8
3 DSP (U12) FLASH (U5) ON Expansion Interface A6 F3 G5 D5 A10 34 44 D9_ZZ
A5 D5 A9 DQ9
A7 E3 K6 D6 22 45 D10_ZZ
4 DSP (U12) FLASH (U5) ON Expansion Interface, SPI FLASH CS A6 D6 SA10 A10 DQ10
A8 C3 G6 D7 3.3V A12 35 47 D11_ZZ
A7 D7 A11 DQ11
A9 D6 H3 D8 A13 36 48 D12_ZZ
A8 D8 A12_NC DQ12
A10 C6 J3 D9 50 D13_ZZ
A9 D9 DQ13
A11 E6 H4 D10 A18 20 51 D14_ZZ
3.3V A10 D10 BA0 DQ14
A12 F6 J4 D11 A19 21 53 D15_ZZ
A11 D11 BA1 DQ15
A13 D7 H5 D12
A12 D12 C54
A14 C7 J6 D13 0.01UF 16 19
A13 D13 0402 SWE WE CS SMS
A15 E7 H6 D14 17 37
A14 D14 SCAS CAS CKE SCKE
A16 F7 J7 D15 18 38
A15 D15/A-1 SRAS RAS CLK CLKOUT
A17 G7
R13 R14 R15 R16 R17 R269 A16
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K A18 D3 15
0402 0402 0402 0402 0402 0402 A17 ABE0#/SDQM0 DQML
2 A19 E4 39 2
A18 ABE1#/SDQM1 DQMH
F5
A19
F4 MT48LC32M16A2TG-75
A20 TSOP54
"FLASH ENBL" U23
3.3V
1
4 D5
2 RESET
SW3 H7
SN74LVC1G08 BYTE
1 8
ON
AMS0 SOT23-5
1
C4
U25 RY/BY~
2 7 1
AMS1
2
4 H2
U13 CE
3 6 1 2
AMS2
3
4 J2
SN74LVC1G08 OE
4 5 2 C47 C48 C49 C50 C51 C52 C53
AMS3/SPI0_SEL2 SOT23-5
4
K7GND1
GND2
VPP/WP~
U24
K2
1 M29W320EB
4 TFBGA63_80
2
SN74LVC1G08
SOT23-5
RESET
ARE
AWE
JP3
3 1 SJ1 3.3V 3
SHORTING
"FLASH WP" 2 JUMPER
DEFAULT=NOT INSTALLED 16 Mb SPI FLASH
IDC2X1
SJ9
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
C58
0.01UF
C57
0.01UF
C56
0.01UF
C55
0.01UF
R19
10K
ANALOG 20 Cotton Road
Nashua, NH 03063
0402 0402 0402 0402 0402 C46
4 0.01UF
0402 DEVICES PH: 1-800-ANALOGD 4
A B C D
A B C D
PS_5V 3.3V
AVDD32
VDD31
3 3 U2
3
MSOP8 MSOP8
VDRIVE
C160 C165
SJ13
1 10PF IDC3X1 10PF IDC3X1 3.3V 1
SHORTING
R215 0805 R221 0805
JUMPER
0 0
DEFAULT=2&3
0402 0402 30
7 DOUTA DOUTA
AGND AGND
SJ17
SHORTING
V1+ VA1
DOUTB
28
DOUTB
"ADC RANGE"
8
JUMPER V1- VA2
C161 C164 27 JP4
DEFAULT=2&3 SCLK ADC_SCLK
10PF 10PF 9 1
0805 AGND 0805 AGND V2+ VA3 26
SJ16 CS ADC_CS
10 2
SHORTING V2- VA4
J19 J21
JUMPER
SMA SMA 11 IDC2X1_SMT
DEFAULT=2&3 VSE1 VA5
R217 R225
0 0 12 21
SJ14 VSE2 VA6 RANGE RANGE
0402 R219 0402 R223
U29 U31 SHORTING
1 5 10 1 5 10 22
JUMPER SGL/DIFF~
0603 JP18 0603 JP23
DEFAULT=2&3
7 1 7 1 18 25
V3+ VB1 A0 ADC_A0/LED1/MMC_D7/OTP_EN
SJ15
2 6 2 2 6 2 17 24 SJ2
V1- V2- SHORTING V3- VB2 A1 CDG/ADC_A1/LED2 SHORTING
AD8022 AD8022 JUMPER
3 3 16 23 JUMPER
MSOP8 MSOP8 DEFAULT=2&3 V4+ VB3 A2 CZM/ADC_A2/LED3
C162 C167 DEFAULT=INSTALLLED
10PF IDC3X1 10PF IDC3X1 15
R218 0805 R224 0805 V4- VB4 2
0 0 14 REF_SELECT Install for a range of 2 X Vref (0-5V)
0402 0402 VSE3 VB5 4 DCAPA
13 DCAPA Remove for a range of Vref (0-2.5V)
AGND AGND VSE4 VB6 20 DCAPB
DCAPB
C163 C166
10PF 10PF
0805 AGND 0805 AGND
29DGND1
DGND2
6AGND1
19AGND2
1AGND3
C59 C60 R26
J22 J25 +12V 0.47UF 0.47UF 10K
SMA SMA 0805 0805 0402
5
R228 R235
0 0
0402 R226 0402 R237
U30 U32
1 3 10 1 3 10
0603 JP19 0603 JP22
2 1 1 1 1 2
2 2 2 2 2 2 C189 C190 C191 C192 C193 C194
V3+ V4+ 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
AD8022 AD8022
3 3 0402 0402 0402 0402 0402 0402
MSOP8 MSOP8
C169 C174
10PF IDC3X1 10PF IDC3X1
R227 0805 R236 0805 AGND AGND
0 0
0402 0402
AGND AGND
3.3V PS_5V AVDD_ADC
C168 C175 -12V
10PF 10PF
0805 AGND 0805 AGND AGND
J23 J24
SMA SMA
R231 R232
0 0
0402 R229 0402 R234
U30 U32
1 5 10 1 5 10 C211 C212 C213 C216 C215 C214 C61 C62 C64 C63 C66 C65
0603 JP20 0603 JP21 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 10UF 0.1UF 10UF 0.1UF
7 1 7 1 0402 0402 0402 0402 0402 0402 0805 0402 0805 0402 0805 0402
2 6 2 2 6 2
V3- V4-
AD8022 AD8022
3 3
MSOP8 MSOP8
C171 C172
10PF IDC3X1 10PF IDC3X1
R230 0805 R233 0805
0 0
0402 0402
AGND
AGND AGND
J17
C170 C173 SMA AGND
10PF 10PF R210
0805 AGND 0805 AGND 0
0402 R208
3 U33 3
1 3 10
0603 JP28
1 1
SW22 SW23
SJ21
1 12 1 12 2 2 2
ON
ON
JUMPER AD8022
2 11 2 11 3
SMA_V2+ SMA_V2- DEFAULT=2&3 MSOP8
2
C157 SW4
3 10 3 10 10PF IDC3X1 1 8
ON
SMA_V3+ SMA_V3- SJ20 PB1/DR1PRI/MMC_D4 DOUTA
3
1
R209 0805
SHORTING
4 9 4 9 0 2 7
SMA_V4+ SMA_V4- JUMPER DR1SEC DOUTB
4
2
0402
DEFAULT=2&3
5 8 5 8 3 6
SMA_VSE1 SMA_VSE3 RSCLK1/MMC_D6 ADC_SCLK
5
3
AGND
SJ18
6 7 6 7 4 5
SMA_VSE2 SMA_VSE4 SHORTING PB2/RFS1/MMC_D5 ADC_CS
6
4
C156
JUMPER
SWT017 SWT017 10PF DIP4
DEFAULT=2&3
DIP6 DIP6 0805 AGND SWT018
SJ19
J16
SINGLE ENDED INPUTS SHORTING
JUMPER
DEFAULT=2&3
SMA
R205
SW4 disconnects DSP from ADC
0
0402 R207
J7 J26 1 5
U34
10 "SPORT1 ENBL"
SMA SMA 0603 JP27
R212 R238 7 1
0 0
0402 R213 0402 R240 2 6 2
U33 U34 VSE4
1 5 10 1 3 10
AD8022
0603 JP25 0603 JP26 3
MSOP8
7 1 1 1 C178
10PF IDC3X1
2 6 2 2 2 2 R206 0805
VSE2 VSE3 0
AD8022 AD8022
3 3 0402
MSOP8 MSOP8
C159 C176
R211
0
10PF
0805
IDC3X1
R239
0
10PF
0805
IDC3X1 AGND
C155
ANALOG 20 Cotton Road
Nashua, NH 03063
0402 0402 10PF
4
AGND AGND
0805 AGND
DEVICES PH: 1-800-ANALOGD 4
C158 C177
10PF
0805 AGND
10PF
0805 AGND
Title ADSP-BF518F EZ-BOARD
ADC
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:21 Sheet 5 of 16
A B C D
A B C D
J4 J5 "MIC GAIN"
SW4: MIC GAIN
3.3V
HP OUT MIC IN POS. GAIN
R47 SW5
40.2K 1 8
ON
1
0402 1 5 (14dB)
2 7 "MIC/HP LPBK"
2
R41
90.9K 3 6 2 1 (0dB) "AUDIO MODE"
3
0402
4 5 R57
4
3.3V DEFAULT 3 0.5 (-6dB) 3.3V 10K SW6
DIP4 0402 1 8
ON
MICIN LHPOUT_RDIV
1
SWT018
4 NC 2 7
RHPOUT_RDIV
2
1 FER19 1
C79 330 3 6
3
1UF 0805
0603 AVDD 4 5
AUDIO_MODE
4
LINE OUT LINE IN DIP4
SWT018
C88 C87 C86 C71 C72
10UF 0.1UF 0.1UF U1 10UF 0.1UF R56
R46 C74 0805 0402 0402 0805 0402 10K
47.0K 220PF 5 18 0402
0402 0402 DBVDD AVDD
DNP 4 19
DGND AGND
3
DCVDD SW6 allows the MICIN signal to be looped back,
FER4 R247 for test purposes, to the Left and Right headphone.
600 5.6K FER20
0603 0402 MICIN_RDIV 22 AGND 330 DO NOT switch positions 1 & 2 ON at the same time.
MICIN 0805
AGND MICBIAS_Z 21 12 HPVDD Ensure that JP15 is on 2&3 or OFF when using SW6.
MICBIAS HPVDD
JP15 R42 15
1 680 HPGND C75 C76
FER3 0402 10UF 0.1UF AUDIO CODEC INTERFACE MODE:
600 2 0805 0402
"MIC" 0603 SW6.3 ON and SW6.4 OFF = SPI MODE
3
LLINEIN_RDIV 24 SW6.3 OFF and SW6.4 ON = TWI MODE
"LINE IN" IDC3X1 C91 LLINEIN
220PF RLINEIN_RDIV 23
0402 RLINEIN
J5 "MIC SELECT" DNP
2 MICIN
SJ3 AGND
CT4
220UF
R53 FER8 "HEAD PHONE"
SHORTING 0 600
D2E
JUMPER 0603 0603
DEFAULT=2&3
LHPOUT
13 LHPOUT LHPOUT_RDIV "LINE OUT"
3 MICBIAS AGND 14 RHPOUT
RHPOUT CT3
FER5 R45 C80
2 1 600 5.6K 1UF
220UF
J4 2
D2E
0603 0402 0603 9 2
4 LLINEIN CODEC_DACLRC DACLRC
CT1
8
CODEC_DACDAT DACDAT 10UF
7 R52 FER7
LEFT_LPBK CAP002
FER2 R40 C81 10 0 600
8 600 5.6K 1UF CODEC_ADCDAT ADCDAT 16 LOUT 0603 0603
RIGHT_LPBK 0603 0402 0603 11 LOUT RHPOUT_RDIV 3
5 RLINEIN CODEC_ADCLRC ADCLRC 17 ROUT
ROUT CT2
7 1
BCLK BCLK 10UF
6
CAP002
LOUT_RDIV 4
CON050 R50 R51
25 47.0K 47.0K 7
C67 C68 C69 C70 C195 R43 R44 C196 AUDIO_MODE MODE 0402 0402 LEFT_LPBK
100PF 100PF 100PF 100PF 220PF 5.6K 5.6K 220PF 26 6 8
XTI/MCLK
0603 0603 0603 0603 0402 0402 0402 0402 CSB CSB CLKOUT RIGHT_LPBK
27 ROUT_RDIV 5
AGND SDIN SDIN
XTO
28 20 6
3.3V SCLK SCLK VMID VMID
2
SSM2602 CON050
ICS009
AGND
AGND AGND
R49 FER6 AGND
100 600
AGND 0402 0603
"AUDIO CLK"
3.3V R59
10K
MICIN_RDIV 0402 R54 FER9
R60 100 600
LLINEIN_RDIV U20 4 33 0402 0603
VDD 0402
RLINEIN_RDIV 1 3 AUDIO_CLK
OE OUT
GND
C73 12MHZ 2
R248 R249 R250 0.01UF OSC003
3 1.0M 1.0M 1.0M 0402 3
0402 0402 0402 R55 R48
47.0K 47.0K C82 C83 C84 C85
0402 0402 100PF 100PF 100PF 100PF
0603 0603 0603 0603
AGND
AGND
3.3V VMID AGND
FER21
330
0805 C90 C89
10UF 0.1UF
0805 0402
1
SW15
12
"SPI/TWI" 10K
0402
0805
DNP
ON
TFS0/SD_D3 CODEC_DACLRC
1
2 11 AGND
DT0PRI/SD_CMD CODEC_DACDAT
2
SW16
3 10 1 12 C78
ON
1000PF
4 9 2 11 0805
RFS0/SD_D2 CODEC_ADCLRC
4
DNP
5 8 3 10
TSCLK0/SD_CLK BCLK SPI0_MOSI
5
6 7 4 9
RSCLK0/SD_D1 SDA SDIN
ANALOG 20 Cotton Road
6
DIP6 5 8
SPI0_SCK
5
4 PH: 1-800-ANALOGD 4
DIP6 AGND
SWT017
A B C D
A B C D
R68
49.9
0603
VCCO_SW VCCPLL_SW
MDIO SMDIO
R71
49.9
0603 3.3V VCCA_SW
VCC3A_SW
MDC SMDC
R72
49.9
0603
MIICRS/HWAIT SCRS
R73
49.9
0603
1 COL SCOL 1
VDDIO1107
VDDC1123
VDDIO079
22
VDDC091
38
VDDA043
VDDA157
63
51
VDDARX50
R75 U4
VDDIO2
VDDC2
VDDA2
VDDAP
VDDATX
49.9
0603 48
TXP1 TXP1
ERXD0 SMRXD0 3.3V 49
R76 TXM1 TXM1
49.9 45
0603 RXP1 RXP1
46
ERXD1 SMRXD1 95 RXM1 RXM1
R77 SMDIO MDIO
49.9 94
0603 SMDC MDC 56
87 TXP2 TXP2
ERXD2 SMRXD2 R355 SCRS SCRS 55
R74 10K 86 TXM2 TXM2
49.9 0402 SCOL SCOL 53
0603 85 RXP2 RXP2
SMRXD0 SMRXD0 52
ERXD3 SMRXD3 84 RXM2 RXM2
R79 SMRXD1 SMRXD1
49.9 SMDIO 83
0603 SMRXD2 SMRXD2 3
82 P1LED0 P1LED0
ERXDV SMRXDV SMRXD3 SMRXD3 2
R67 81 P1LED1 P1LED1
33 SMRXDV SMRXDV 1
0402 80 P1LED2 P1LED2
SMRXC SMRXC 25
ERXCLK SMRXC 77 P1LED3 P1LED3
R66 SMTXC/REFCLK SMTXC/REFCLK
33 ERXER 76
0402 SMTXER SMTXER 6
75 P2LED0 P2LED0
MIITXCLK SMTXC/REFCLK SMTXD0 SMTXD0 5
R78 R353 74 P2LED1 P2LED1
33 10K SMTXD1 SMTXD1 4
0402 0402 73 P2LED2 P2LED2
SMTXD2 SMTXD2 20 3.3V VCC3A_SW
RMII_PHYINT SMTXER 72 P2LED3 P2LED3
2 R82 SMTXD3 SMTXD3 2
49.9 71 70
0603 SMTXEN SMTXEN LEDSEL0 LEDSEL0 FER13
23 600
ETXD0 SMTXD0 LEDSEL1 LEDSEL1 0603
R81 99
49.9 SPIS SPIS
0603 98 68
SSDA SDA UNUSED1 3.3V
ETXD1 SMTXD1 97 69 C94 C93 C92 C101 C102 C103
R80 SSCL SCL UNUSED2 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF
49.9 96 92 0805 0402 0402 0805 0402 0402
0603 SMTXER SPIQ SPIQ UNUSED3 R62
93 1.0K
ETXD2 SMTXD2 UNUSED4 0402
R83 30 102
49.9 R354 P1ANEN P1ANEN UNUSED5
0603 10K 31 103
0402 P1SPD P1SPD UNUSED6 R70
ETXD3 SMTXD3 32 104 100
R84 P1DPX P1DPX UNUSED7 0402
49.9 33 105 AGND
0603 P1FFC P1FFC UNUSED8
13 108
ETXEN SMTXEN P2ANEN P2ANEN UNUSED9
14 109
P2SPD P2SPD UNUSED10 VCCO_SW VCCA_SW VCCPLL_SW
15 110
P2DPX P2DPX UNUSED11 FER12 FER14
16 111 600 600
P2FFC P2FFC UNUSED12 0603 0603
29 112
P2MDIX P2MDIX UNUSED13
28 113
P2MDIXDIS P2MDIXDIS UNUSED14
12 114 C95 C96 C97 C98 C99 C100 C106 C105 C104
ADVFC ADVFC UNUSED15 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF
26 115 0805 0402 0402 0805 0402 0402 0805 0402 0402
RMIIEN UNUSED16
27 116
HWPOVR HWPOVR UNUSED17
3 89 117 3
SCONFIG0 SCONFIG0 UNUSED18
88 118
3.3V SCONFIG1 SCONFIG1 UNUSED19
101 119
PS0 PS0 UNUSED20
100 120 AGND
PS1 PS1 UNUSED21
121
UNUSED22
36 124
PWRDN PWRDN UNUSED23 R61
125 1.0K
R86 R85 UNUSED24 0402
10K 10K 67 126
0402 0402 RESET RESET UNUSED25
65 40 R69
CLKBUF X1 MUX1 0
66 41 0805
"ETHERNET MODE" X2 MUX2
44
FXSD1
59
TEST1 R63
60 3.01K
SW17 TEST2 0402
1 12 61
ON
39ADGND1
42ADGND2
47ADGND3
54ADGND4
58ADGND5
62ADGND6
64ADGND7
ADGND8
1.0K
21DGND1
78DGND2
90DGND3
106DGND4
122DGND5
DGND6
3 10 128 0402
SPI0_MOSI SCANEN
3
4 9
SDA SSDA
4
37
KS8893M R65
5 8 PQFP128 1.0K
SPI0_SCK
ANALOG 20 Cotton Road
5
0402
6 7
SCL SSCL
6
DIP6
Nashua, NH 03063
4 SWT017
DEVICES PH: 1-800-ANALOGD 4
A B C D
A B C D
3.3V
3.3V
ON
P1FFC
1
1 8
ON
ADVFC
1
2 7
P1DPX
2
2 7
HWPOVR
2
3 6
P1SPD
3
3 6 JP11 JP12
PS1
3
4 5 1 2 1 2
P1ANEN LEDSEL0 LEDSEL1
4
4 5
PS0
4
DIP4
SWT018 DIP4
SWT018 R91 R93
R103 1.0K 1.0K
1.0K R116 0402 0402
SW7: Port 1 Configuration Switch 0402 1.0K
0402
Switch Description Position Function
SW8: Ethernet Configuration Switch
1 Force Flow Control OFF Disable Switch Description Position Function
ON Enable
1 Advertise Flow Control OFF Disable
2 Force Full/Half OFF Half Duplex ON Enable
JPx: LED Configuration Switch
ON Full Duplex
2 Hardware Pin Overwrite OFF Enable
OFF OFF OFF ON ON OFF ON ON
3 Force Speed OFF 10BaseT ON Disable
ON 100BaseTX PxLED3 tri-state,PD tri-state,PD ACT NU
3,4 Serial Bus Mode OFF OFF Not Used
4 Auto-Negotiation OFF Enable OFF ON TWI Slave PxLED2 LINK/ACT 100LINK/ACT LINK NU
ON Disable ON OFF SPI Slave
PxLED1 FULL DPX/COL 10LINK/ACT FULL DPX/COL NU
ON ON Not Used
PxLED0 SPEED FULL DPX SPEED NU
2 2
PS1
R94
1.0K
PS0 0402
3.3V P1LED3
R271 R272
1.0K 1.0K
0402 0402
PORT 2 3.3V
P2FFC
1
LED009 0603
2 11
P2DPX P1LED1
2
3 10
P2SPD
3
LED12 R97
P2ANEN
4 9 PORT 1 YELLOW 270
4
LED009 0603
5 8 R89
P2MDIXDIS P1LED2
5
10K
6 7 0402
P2MDIX "ETHERNET PD"
6
LED4 R98
DIP6 YELLOW 270
SWT017 JP13 LED009 0603
SCONFIG0 1 2
R109 PWRDN P1LED3
3 1.0K SCONFIG1 3
SW18: Port 2 Configuration Switch 0402
ON Disable P2LED2
LED8 R102
5 Auto MDI/MDI-X OFF Enable YELLOW 270
LED009 0603
ON Disable
P2LED3
A B C D
A B C D
VCC3A_SW
PORT 1
U28 J15
1 16 1
TXP1 TD+ TX+
1 2 2
1
TCT
3 14 3
TXM1 TD- TX-
1CT:1CT 15 4
TCM
5
6 11 6
RXP1 RD+ RX+
7 7
RCT
8 9 8
RXM1 RD- RX-
10
TCM_
NC1
NC2
NC3
NC4
R118 R119 R120 R121
49.9 49.9 49.9 49.9
0603 0603 0603 0603
12
13
HX1188 R136 R138 R139 R137 R135
ICS007 75.0 49.9 49.9 49.9 49.9
0603 0603 0603 0603 0603
C114
1000PF
1206
2 2
SHGND
VCC3A_SW
PORT 2
U27 J14
1 16 1
TXP2 TD+ TX+
2 2
TCT
3 14 3
TXM2 TD- TX-
1CT:1CT 15 4
TCM
5
6 11 6
RXP2 RD+ RX+
7 7
RCT
8 9 8
RXM2 RD- RX-
10
TCM_
NC1
NC2
NC3
NC4
12
13
C112
1000PF
1206
SHGND
A B C D
A B C D
3.3V
All USB interface circuitry is considered proprietary and has
been omitted from this schematic.
ON
A SPI0_SSEL3/CUD
1
6 2 5
B CDG/ADC_A1/LED2 "JTAG"
2
5 3 4
SW1 CZM/ADC_A2/LED3
3
4 DIP3 R144 R145 PS_5V 3.3V
SW2 SWT015 10K 10K
0402 0402
2
COMMON
P1
ROTARY_ENC_EDGE 1 2 EMU
SWT025
TP1 3 4
7 8 TCK
GND
11 12 TDI
C116
0.1UF U21 13 14 TDO DA_STANDALONE
0402 C117
R270 1 0.1UF J2 IDC7X2_SMTA
10K C1+ 0402
0402 3
C1- 2 R143
1
V+ 10K
C115 4 6 6 0402
0.1UF C2+ V-
0402 5 2
C2-
7
2 SW10 2
1 8 11 14 3
ON
2 7 10 7 8
MIICRS/HWAIT T2IN T2OUT
2
3 6 12 13 4
UART0_RX R1OUT R1IN
3
TP12
4 5 9 8 9
R2OUT R2IN
4
CON038
C118
"UART0 SETUP" 0.1UF
0402 R203
10K
(UART 0) R149
22
0402 3.3V
0402
MMC_D0
DR0PRI/SD_D0
R146
22
0402
MMC_D1
RSCLK0/SD_D1
4
J13
R147 7
VDD
3.3V 22 DAT0
0402 8
MMC_D2 DAT1
RFS0/SD_D2 9
R148 DAT2 C154
22 1 0.01UF
0402 CD/DAT3 0402
"eMMC ENABL" TFS0/SD_D3
MMC_D3 5
CLK
GND1
GND2
3 R150 2 3
22 CMD
VCCQ3AA3
VCCQ4AA5
VCC2T10
VCCQ1W4
M6
VCC1N5
VCC3U9
VCC4K6
VCCQ2Y4
3
6
VCCQ5
1 4 MMC_CLK
ON
MMC_CLK TSCLK0/SD_CLK
1
2 3 R151
MMC_CMD
2
W6 22
DIP2 CLK 0402
SWT020 W5 MMC_CMD
1
SW20
16 H3
CMD
2GB eMMC DT0PRI/SD_CMD
ON
MMC_D0 D0
1
2 15 H4
MMC_D1 D1
2
3 14 H5
MMC_D2 D2
3
4 13 J2
MMC_D3 D3 "SD CARD"
4
R241 5 12 J3
D4
5
22
0402 6 11 J4
D5
6
PB1/DR1PRI/MMC_D4 7 10 J5
D6
7
8 9 J6
D7
8
R242
Y2VSSQ1
Y5VSSQ2
AA4VSSQ3
AA6VSSQ4
K2VSSQ5
22 DIP8
P5VSS1
R10VSS2
U8VSS3
K4VSS4
VDDI
MTFC2GDKDM
FBGA169
R243
22
0402
C188
RSCLK1/MMC_D6 0.1UF
0402
R244
22
0402
C179
0.01UF
C180
0.01UF
C181
0.01UF
C182
0.01UF
C183
0.01UF
C184
0.01UF
C186
0.01UF
C185
0.01UF
C187
0.01UF
ANALOG 20 Cotton Road
Nashua, NH 03063
0402 0402 0402 0402 0402 0402 0402 0402 0402
4 ADC_A0/LED1/MMC_D7/OTP_EN
DEVICES PH: 1-800-ANALOGD 4
A B C D
A B C D
A[1:19]
1 1
P5 P6 P7
A1 A1 B1 D0 A1 B1 A1 B1
D0 GND9 D[0:15] D0 GND9 MDC D0 GND9
A2 A2 B2 D1 A2 B2 A2 B2
D1 D2 AMS0 D1 D2 ETXD0 MDIO D1 D2 DR0PRI/SD_D0
A3 B3 A3 B3 A3 B3
GND0 D3 AMS1 GND0 D3 ETXD1 GND0 D3 RSCLK0/SD_D1
A3 A4 B4 D2 A4 B4 A4 B4
D4 GND10 D4 GND10 SPI0_SSEL1 D4 GND10
A4 A5 B5 D3 A5 B5 A5 B5
D5 D6 AMS3/SPI0_SEL2 D5 D6 ETXD2 SPI0_SSEL3/CUD D5 D6 RFS0/SD_D2
A6 B6 A6 B6 A6 B6
GND1 D7 ARE GND1 D7 ETXD3 GND1 D7 TFS0/SD_D3
A7 B7 A7 B7 A7 B7
CLKOUT CLK1+ GND11 CLKBUF CLK1+ GND11 SPI0_SCK CLK1+ GND11
A8 B8 A8 B8 A8 B8
CLK1- D8 AMS2 CLK1- D8 ERXD0 CLK1- D8 DT0PRI/SD_CMD
A9 B9 A9 B9 A9 B9
GND2 D9 ABE1#/SDQM1 GND2 D9 ERXD1 GND2 D9 TSCLK0/SD_CLK
A5 A10 B10 D4 A10 B10 A10 B10
D10 GND12 D10 GND12 SPI0_MISO D10 GND12
A6 A11 B11 D5 A11 B11 A11 B11
D11 D12 SCAS D11 D12 ERXD2 SPI0_MOSI D11 D12 UART0_TX
A12 B12 A12 B12 A12 B12
GND3 D13 SCKE GND3 D13 ERXD3 GND3 D13 UART0_RX
A7 A13 B13 D6 A13 B13 A13 B13
D14 GND13 D14 GND13 CDG/ADC_A1/LED2 D14 GND13
A8 A14 B14 D7 A14 B14 A14 B14
D15 D16 ABE0#/SDQM0 D15 D16 ETXEN CZM/ADC_A2/LED3 D15 D16
A15 B15 A15 B15 A15 B15
GND4 D17 SMS GND4 D17 ERXDV GND4 D17
A9 A16 B16 D8 A16 B16 A16 B16
D18 GND14 D18 GND14 SCL D18 GND14
A10 A17 B17 D9 A17 B17 A17 B17
D19 D20 SWE D19 D20 ERXER SDA D19 D20
A18 B18 A18 B18 A18 B18
GND5 D21 SRAS GND5 D21 GND5 D21
A11 A19 B19 D10 A19 B19 A19 B19
2 D22 GND15 D22 GND15 PB1/DR1PRI/MMC_D4 D22 GND15 2
A12 A20 B20 D11 A20 B20 A20 B20
D23 CLK2- D23 CLK2- PB2/RFS1/MMC_D5 D23 CLK2-
A21 B21 A21 B21 A21 B21
GND6 CLK2+ AWE GND6 CLK2+ ERXCLK GND6 CLK2+
A13 A22 B22 D12 A22 B22 A22 B22
D24 GND16 D24 GND16 RSCLK1/MMC_D6 D24 GND16
A14 A23 B23 D13 A23 B23 A23 B23
D25 D26 SA10 D25 D26 MIITXCLK ADC_A0/LED1/MMC_D7/OTP_EN D25 D26
A24 B24 A17 A24 B24 A24 B24
GND7 D27 GND7 D27 MIICRS/HWAIT GND7 D27
A15 A25 B25 D14 A25 B25 A25 B25
D28 GND17 D28 GND17 DR1SEC D28 GND17
A16 A26 B26 A19 D15 A26 B26 A26 B26
D29 D30 D29 D30 RMII_PHYINT RESET D29 D30
A27 B27 A18 A27 B27 A27 B27
GND8 D31 GND8 D31 COL GND8 D31
DMAX_ALT DMAX_ALT DMAX_ALT
DNP DNP DNP
3 3
A B C D
A B C D
3.3V
3.3V
3.3V
ON
U6 PB1/DR1PRI/MMC_D4
1
0805 0603
3 4 2 3
PB2/RFS1/MMC_D5
2
SW13 DIP2
SWT020
74LVC14A
MOMENTARY
SOIC14
SWT024
C124
1UF
0805
2 2
SW2: GPIO enable
1 push button 1 DSP (U12, PH0) ON ON (PB1), OFF eMMC, ADC, Expansion Interface)
2 push button 2 DSP (U12, PH1) ON ON ( PB2), OFF eMMC, ADC, Expansion Interface)
3.3V
LED9
"RESET" RED
3 LED001 3
U22
1 8
MR RESET
4 7
PFI RESET RESET
5
DA_SOFT_RESET PFO
U26
1
4 ADM708SARZ
2 SOIC8
SN74LVC1G08
SW11
SOT23-5
MOMENTARY
SWT024
3.3V
3.3V
3.3V 3.3V
"RESET"
A B C D
A B C D
3.3V 3.3V
PS_5V PS_5V
D[0:15]
A[1:19]
J1
A1 2 1 P3 P2
ADDR1 ADDR0 1 2 1 2
A3 4 3 A2 GND1 PWR_IN1 GND1 PWR_IN1
ADDR3 ADDR2 3 4 3 4
A5 6 5 A4 GND2 PWR_IN2 GND2 PWR_IN2
ADDR5 ADDR4 5 6 5 6
A7 8 7 A6 GND3 VDDIO1 GND3 VDDIO1
ADDR7 ADDR6 7 8 7 8
A9 10 9 A8 GND4 VDDIO2 GND4 VDDIO2
ADDR9 ADDR8 9 10 9 10
A11 12 11 A10 GND5 3.3V1 GND5 3.3V1
ADDR11 ADDR10 11 12 11 12
1 A13 14 13 A12 GND6 3.3V2 GND6 3.3V2 1
ADDR13 ADDR12 13 14 13 14
A15 16 15 A14 TFS0/SD_D3 PPI0FS1 PPI0FS2 DT0PRI/SD_CMD DT0PRI/SD_CMD DTPRI DRPRI DR0PRI/SD_D0
ADDR15 ADDR14 15 16 15 16
A17 18 17 A16 AMS3/SPI0_SEL2 PPI0FS3 PPI0CLK RFS0/SD_D2 UART0_TX DTSEC DRSEC UART0_RX
ADDR17 ADDR16 17 18 17 18
A19 20 19 A18 ERXD2 PPI0D1 PPI0D0 ETXD2 TSCLK0/SD_CLK TSCLK RSCLK RSCLK0/SD_D1
ADDR19 ADDR18 19 20 19 20
22 21 ERXD3 PPI0D3 PPI0D2 ETXD3 TFS0/SD_D3 TFS RFS RFS0/SD_D2
ADDR21 ADDR20 21 22 21 22
24 23 ERXDV PPI0D5 PPI0D4 ERXCLK CZM/ADC_A2/LED3 SPISEL1 SPISEL2 MIICRS/HWAIT
ADDR23 ADDR22 23 24 23 24
26 25 SPI0_SSEL1 PPI0D7 PPI0D6 COL AMS2 SPISEL3 SPICLK RSCLK1/MMC_D6
ADDR25 ADDR24 25 26 25 26
28 27 MDIO PPI0D9 PPI0D8 MDC ADC_A0/LED1/MMC_D7/OTP_EN SPIMOSI SPISS PB1/DR1PRI/MMC_D4
ADDR27 ADDR26 27 28 27 28
30 29 ERXD0 PPI0D11 PPI0D10 ETXD0 PB2/RFS1/MMC_D5 SPIMISO TIMER DR1SEC
ADDR29 ADDR28 29 30 29 30
32 31 ERXD1 PPI0D13 PPI0D12 ETXD1 SCL SCL SDA SDA
ADDR31 ADDR30 31 32 31 32
34 33 RMII_PHYINT PPI0D15 PPI0D14 ETXEN UART0_TX UARTTX UARTRX UART0_RX
AWE AWE AOE 33 34 33 34
36 35 PPI0D17 PPI0D16 UARTRTSUARTCTS
ARDY ARE ARE 35 36 35 36
38 37 TSCLK0/SD_CLK TIMER2/GPIO TIMER1/GPIO RSCLK0/SD_D1 RESET RESET NC
AMS1 AMS1 AMS0 AMS0 37 38 37 38
40 39 RESET RESET TIMER3/GPIO UART0_TX PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5
AMS3/SPI0_SEL2 AMS3 AMS2 AMS2 39 40 39 40
42 41 PPI1FS1 PPI1FS2 ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2
ABE1#/SDQM1 ABE1 ABE0 ABE0#/SDQM0 41 42 41 42
44 43 PPI1FS3 PPI1CLK WAKE WAKE RSVD1
ABE3 ABE2 43 44 43 44
46 45 PPI1D1/PPI0D19 PP1D0/PPI0D18 RSVD2 RSVD3
BR NMI NMI 45 46 45 46
48 47 PPI1D3/PPI0D21 PPI1D2/PPI0D20 RSVD4 RSVD5
BGH BG 47 48 47 48
50 49 PPI1D5/PPI0D23 PPI1D4/PPI0D22 RSVD6 RSVD7
CLKOUT CLKOUT RESET RESET 49 50 49 50
52 51 PPI1D7 PPI1D6 RSVD8 RSVD9
PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5 51 52 IDC25X2_SMTA
54 53 PPI1D9 PPI1D8
2 ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2 53 54 2
D1 56 55 D0 PPI1D11 PPI1D10
DATA1 DATA0 55 56
D3 58 57 D2 PPI1D13 PPI1D12
DATA3 DATA2 57 58
D5 60 59 D4 PPI1D15 PPI1D14 3.3V
DATA5 DATA4 59 60 PS_5V
D7 62 61 D6 PPI1D17 PPI1D16
DATA7 DATA6 61 62
D9 64 63 D8 SDA SDA NC
DATA9 DATA8 63 64
D11 66 65 D10 SCL SCL RSVD1
DATA11 DATA10 65 66
D13 68 67 D12 RSVD2 RSVD3 P4
DATA13 DATA12 67 68 1 2
D15 70 69 D14 RSVD4 RSVD5 GND1 PWR_IN1
DATA15 DATA14 69 70 3 4
72 71 RSVD6 RSVD7 GND2 PWR_IN2
DATA17 DATA16 IDC35X2_SMTA 5 6
74 73 GND3 VDDIO1
DATA19 DATA18 7 8
76 75 GND4 VDDIO2
DATA21 DATA20 9 10
78 77 GND5 3.3V1
DATA23 DATA22 11 12
80 79 GND6 3.3V2
DATA25 DATA24 13 14
82 81 ADC_A0/LED1/MMC_D7/OTP_EN DTPRI DRPRI PB1/DR1PRI/MMC_D4
DATA27 DATA26 15 16
84 83 CZM/ADC_A2/LED3 DTSEC DRSEC DR1SEC
3.3V PS_5V DATA29 DATA28 17 18
86 85 CDG/ADC_A1/LED2 TSCLK RSCLK RSCLK1/MMC_D6
DATA31 DATA30 19 20
88 87 SPI0_SSEL3/CUD TFS RFS PB2/RFS1/MMC_D5
RSVD1 RSVD2 21 22
90 89 SPI0_SSEL1 SPISEL1 SPISEL2 AMS3/SPI0_SEL2
RSVD3 RSVD4 23 24
92 91 SPI0_SSEL3/CUD SPISEL3 SPICLK SPI0_SCK
RSVD5 RSVD6 25 26
94 93 SPI0_MOSI SPIMOSI SPISS AMS2
RSVD7 RSVD8 27 28
3 96 95 SPI0_MISO SPIMISO TIMER DR1SEC 3
PWR_IN1 GND1 29 30
98 97 SCL SCL SDA SDA
PWR_IN2 GND2 31 32
100 99 CZM/ADC_A2/LED3 UARTTX UARTRX DR1SEC
VDDIO1 GND3 33 34
102 101 UARTRTSUARTCTS
VDDIO2 GND4 35 36
104 103 RESET RESET NC
3.3V1 3.3V2 37 38
QMS52X2_SMT PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5
39 40
ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2
41 42
WAKE WAKE RSVD1
43 44
RSVD2 RSVD3
45 46
RSVD4 RSVD5
47 48
RSVD6 RSVD7
49 50
RSVD8 RSVD9
IDC25X2_SMTA
A B C D
A B C D
VDDOTP TP3
3.3V
VPPOTP TP2
R182 C136 L2
2.0K 0.1UF 1UH
0603 0603 IND019
D2 D5
1 PS_5V
MBR130LSFT1G MBR130LSFT1G 1
1A 1A
SJ4
SOD-123FL SOD-123FL
SHORTING
JUMPER R181
DEFAULT=NOT INSTALLED U11 140.0K
0603
2 V- V+ 1
L1 TRIM R352
"OTP FLAG ENBL" 22UH 3 ADR550B R180 VR3 21.5K
IND018 SOT23-3 1.91K 0603
0603 1 5 R179
JP14 IN OUT 21.5K
1 D4 3 0603
ADC_A0/LED1/MMC_D7/OTP_EN C127 MBR130LSFT1G EN DNP
2 VR2 10UF 1A 2 4
1210 SOD-123FL GND ADJ
IDC2X1 6 5 C129
IN SW1 2.2UF ADP1710
0805 TSOT5
7 2 C133 R178
RT FB C126 R183 1UF 10K
D3
10UF 10.0K 0603 0603
MBR130LSFT1G
3 8 1210 0603 DNP DNP
SD SS 1A
SOD-123FL
4 1
GND COMP
R173 C125 C208
10K 10UF 1UF
0402 1210 0603 ADP1610 R176 C131 R351 R184
MSOP8 24.0K 22000PF 0 3.01K
0603 0402 0603 0603 R177 C132
C135
DNP 10K 2.2UF
10UF
C209 0603 0805
1210
1UF DNP
0603
DNP
C130
2200PF
0603
2 2
L6
1UH
IND019
-12V
1 2
C201 C200
L8 10UF 10UF
22UH D9 1210 1210
IND024 MBR130LSFT1G
3 4
SOD-123FL
PS_5V C206
2.2UF
0805
1 2
L9
22UH
IND024
3 4
3 3
R350 D10
100K C204 MBR130LSFT1G L7
C205 R349 0402 2.2UF 1UH
10UF 10 0805 SOD-123FL IND019
1210 0603 +12V
C207
1000PF C203 C202
0603 10UF 10UF
R348 1210 1210
R345 VR6 44.2K
0 0603
0603 6 5
DNP IN SW1
7 2
RT FB
3 8
SD SS
4 1
R346 GND COMP
0 C199 C210
0603 1UF 1UF
0603 0603 ADP1611 R344 C197 R347
DNP MSOP8 20.0K 22000PF 4.99K
0402 0402 0603
C198
3300PF
0603 ANALOG 20 Cotton Road
Nashua, NH 03063
4 DEVICES PH: 1-800-ANALOGD 4
A B C D
A B C D
F1 FER17
3A 190
FUS004 FER002
4 3
PS_5V
1 2
J3
R267
1
C149 0
C148 10UF 0402
D8
1000PF 1210
MBRS540T3G WAKE
3 1206
5A
SMC
2
POWER
CON045
R186
SHGND 1.2K R246 C141 P8
0402 10K 4.7UF 1 2
U7 0402 0603
DNP VR5 IDC2X1
1 10
SHGND W A 1 5
EN GND1 "VDDINT"
2 9
AD0 B R189 2 6
1.0K IN GND2
3 8 0402 C139
AD1 VCC 0.01UF 3 7
0402 OUT GND3
4 7 SJ5
SDA SDA GND 4 8 SHORTING
ADJ GND4 JUMPER
5 6 DEFAULT=INSTALLED
SCL SCL VLOGIC
AD5258 R187 ADP1715
MSOP10 C140 C137 2.67K C138 R245 MSOP8
0.1UF 4.7UF 0402 4.7UF 10K
0402 0603 0603 0402
Remove P8 when measuring VDDINT
2 2
PS_5V
C146
10UF
C142
10UF
Remove P9 when measuring VDDEXT 1.8V @ 500mA
1210 0805
DNP SJ6
SHORTING "VDDFLASH"
JUMPER
3 3.3V @ 2A DEFAULT=INSTALLLED P11 3
1 2 TP11
3.3V TP8
IDC2X1 VDDFLASH
PGND R204
TP5 3.3V "VDDEXT" VR4 0.05
R196 R194 TP6 1206
R192 VR1 0.05 0.05 1 3
24.9K 1206 1206 P9 EN OUT
0603 5 U8 1 2 2
1 IN IN
COMP IDC2X1 VDDEXT 4
4 1 5 SS
CS L3 R191
6GND1
7GND2
8GND3
GND4
C143 C144 2 6 2.5UH 0.05 C151 C152 C150
470PF 68PF 3 6 R195 IND013 1206 2.2UF 0.1UF 2.2UF
FB PGATE
5
0603 0603 0 3 7 0805 0402 0805
GND 0603
R193 2 ADP1864AUJZ 4 8
80.6K SOT23-6 Remove P11 when measuring VDDFLASH
0603
D7
CT6 CT5 C145
MBRS540T3G
SI4411DY 220UF 2.2UF 4.7UF
SMC
SO-8 D2E B 0805
DNP R198
0.05 TP7 SJ8
R197 1206 SHORTING
255.0K JUMPER
0603 VDDMEM DEFAULT=INSTALLLED
PGND
P10
1 2
PGND
IDC2X1
SHORTING
JUMPER
DEFAULT=INSTALLLED
Title ADSP-BF518F EZ-BOARD
PGND
POWER
Remove P10 when measuring VDDMEM
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:26 Sheet 15 of 15
A B C D
A B C D
22 33 33 33 33
RNS005 RNS005 RNS005 RNS005 RNS005
22 33 33 22 33
RNS005 RNS005 RNS005 RNS005 RNS005
2 2
22 33 33 22 33
RNS005 RNS005 RNS005 RNS005 RNS005
3 33 33 33 22 22 3
RNS005 RNS005 RNS005 RNS005 RNS005
RN21
D15_ZZ 1 8 D15
R1A R1B
D14_ZZ 2 7 D14
R2A R2B
D13_ZZ 3 6 D13
R3A R3B
D12_ZZ 4 5 D12
R4A R4B
22
RNS005
A B C D
I INDEX
Numerics audio
2-wire interface (TWI), 2-3 interface, 1-17
codec (U31), 1-13, 1-15, 1-17, 2-10
dual connectors (J4-5), 1-18, 2-26
A SPI/TWI select switch (SW16), 2-13
AD5258 digipot, 2-2 SPORT0 enable (SW15), 1-17, 2-13
ADC7266 (U2), 2-9 test switches (SW22-23), 1-19, 2-15
ADC_A0-2 signal, 1-21
ADC channel select jumpers (JP17-28), 2-19
B
ADC range jumper (JP4), 2-17
ADM3202 line driver/receiver (U21), 1-19 background telemetry channel (BTC), 1-25
ADP1715 low dropout regulator (LDO), 2-2 battery
AMS0-3 select lines, 1-11, 2-9, 2-18 holder connector (J12), 2-26
analog audio interface, See audio supply, 1-20
analog-to-digital converter (ADC), 1-12, 1-17, bill of materials, A-1
1-18, 2-15, 2-17 board schematic (ADSP-BF518F), B-1
architecture, of this EZ-Board, 2-2 boot
ASYNC (asynchronous memory control) modes, 2-8
external memory banks 0-3, 1-10 mode select switch (SW1), 1-12, 1-14
C
CDG signal, 1-21
audio codec, See audio
configuration, of this EZ-Board, 1-4
connectors Ethernet
diagram of locations, 2-24 interface, xiv, 1-13, 1-16
J12 (battery holder), 2-26 configuration switch (SW8), 2-11
J13 (SD), 2-26 connectors (J14-15), 1-17, 2-27
J14-15 (Ethernet), 1-17 LEDs (LED4-8, LED10-12), 2-22
J14 (Ethernet), 2-27 mode switch (SW17), 2-14
J15 (Ethernet), 2-27 PHY IC (U29), 1-13
J16-26 (SMA), 2-26 port 1 config switch (SW7), 1-16, 2-11
J1 (expansion interface II), 1-21, 2-25, 2-26 port 2 config switch (SW18), 1-16, 2-14
J2 (RS-232), 2-25 power down jumper (JP13), 2-17
J3 (power), 1-6, 2-25 reset push button (SW11), 2-12
J4-5 (dual audio), 1-18, 2-26 example programs, 1-25
J7 (SMA), 2-26 expansion interface II
P1 (JTAG), 1-6, 1-22, 2-27 J1 connector, 1-21, 1-23, 2-25, 2-26
P2 (expansion interface II), 1-21, 2-27 P2 connector, 1-19, 1-21, 1-23, 2-27
P3 (expansion interface II), 1-15, 2-28 P3 connector, 1-15, 1-23, 2-28
P4 (expansion interface II), 1-21, 2-27 P4 connector, 1-19, 1-21, 1-23, 2-27
P5-7 (DMAX land grid array), 1-22, 2-28 external memory, 1-9, 1-10
ZP1 (debug agent), 2-29
contents, of this EZ-Board package, 1-3
F
core voltage, 2-2
CUD (up) signal, 1-14, 1-15 features, of this EZ-Board, xiii
customer support, xvii flag pins, See programmable flags by name (PFx,
CZM signal, 1-21 PGs, PHx)
flash memory enable switch (SW6), 2-9
flash WP jumper (JP3), 2-17
D
Das U-Boot, universal boot loader, 1-13
G
debug agent connector (ZP1), 2-29
default configuration, of this EZ-Board, 1-4 general-purpose IO pins (GPIO), 1-21, 2-8,
down signal (CDG), 1-15 2-12, 2-14, 2-22
DR1PRI signal, 1-21 general-purpose push buttons (PB1-2), 1-21
GPIO enable switch, See SW2
E
I
eMMC
enable switches (SW20-21), 1-12 installation, of this EZ-Board, 1-4
enable switch (SW20-21), 2-15 IO voltage, 2-2
interface, 1-12
J M
JTAG MAC address, 1-16
interface, 1-22 media independent interface (MII), 1-16
connector (P1), 1-6, 1-22, 2-27 Media Instruction Set Computing (MISC), xi
jumpers memory map, of this EZ-Board, 1-9
diagram of locations, 2-16 MICBIAS signal, 2-18
JP11-12 (LED select), 2-17 MICIN signal, 2-18
JP13 (Ethernet power down), 2-17 microphone
JP14 (OTP flag enable), 2-18 gain switch (SW5), 2-10
JP15 (mic select), 1-17, 2-18 headphone select (SW6), 1-18, 2-10
JP16 (SPI flash CS enable), 1-15, 2-18 select jumper (JP15), 1-17, 2-18
JP17-28 (ADC channel select), 2-19 SPI/TWI switch (SW8), 1-17
JP3 (flash WP), 2-17 Micro Signal Architecture (MSA), xi
JP4 (ADC range), 1-19, 2-17 MMC_Dx signals, 1-21
JP6 (mic select), 1-17
P10 (VDDMEM power), 1-24, 2-20
N
P11 (VDDFLASH power), 1-24, 2-20
P17-28 (ADC channel select), 1-19 notation conventions, xxi
P8 (VDDINT power), 1-24, 2-19
P9 (VDDEXT power), 1-24, 2-19 O
oscilloscope, 1-24
K OTP_EN signal, 1-21
KSZ8893M PHY device, 2-14 OTP flag enable jumper (JP14), 2-18
OTP memory writes, 2-18
L
P
land grid array connectors (P5-7), 1-22, 2-28
LEDs package contents, 1-3
diagram of locations, 2-21 parallel flash memory, xiii, 1-11
LED10-12 (Ethernet), 2-22 See also NAND, flash memory
LED1-3 (PH3, PH5-6), 1-21, 2-22 parallel peripheral interface (PPI), See PPI
LED4-8 (Ethernet), 2-22 interface
LED4 (USB monitor), 1-6 PF0-7 programmable flags, 2-3
LED9 (reset), 2-22 PF8 programmable flag, 2-3
power (LED13), 2-23 PF9-15 programmable flags, 2-3
LED select jumpers (JP11-12), 2-17 PG0-10 programmable flags, 2-5
license restrictions, xii, 1-8 PG11 programmable flag, 2-5
PG12 programmable flag, 2-5
PG13-15 programmable flags, 2-5
PH0-1 programmable flags, 1-21, 2-6, 2-12
PH2 programmable flag, 2-6 secure digital (SD) interface, 1-12, 1-13
PH3 programmable flag, 1-21, 2-6, 2-18, 2-22 serial peripheral interconnect (SPI) ports, See
PH4 programmable flag, 2-6 SPI interface
PH5-6 programmable flags, 1-21, 2-6, 2-22 session startup procedure, 1-6
PH7 programmable flag, 2-6 SMA connectors (J7, J16-26), 2-26
POST (power-on-self test) program, 1-12, 1-19, SPI0_SSEL2 signal, 2-18
1-24, 2-12 SPI flash CS enable jumper (JP16), 2-18
power SPI interface
5V wall adaptor (P14), 1-3 connections, 1-13
connector (J3), 1-6, 2-25 SPI/TWI switch (SW16), 1-17
LED (LED13), 2-23 SPISEL1 signal, 1-14
measurements, 1-24 SPISEL2 signal, 1-13
PPI interface SPISEL3 signal, 1-14
connections, 1-15 SPORT0 enable switch (SW15), 1-17, 2-13
expansion interface II connector (P3), 1-15, SPORT1 enable switch (SW4), 1-18, 2-9
2-28 SRAM memory, 1-9
programmable flag inputs PH0 -1, 1-21 SSM2602 audio codec (U1), 2-13
standalone debug agent, xii, 1-4, 1-6, 1-8, 1-11,
1-22
R
SW10 (UART0 setup) switch, 2-12
real-time clock (RTC), 1-20, 2-3 SW11 (reset) push button, 2-12
Reduced Instruction Set Computing (RISC), xi SW12-13 (IO) push buttons, 2-12
reference design info, 1-25 SW14 (rotary encoder with momentary) switch,
removable secure interface (RSI), 1-12 2-13
reset SW15 (SPORT0 enable) switch, 1-17, 2-13
LED (LED9), 2-22 SW16 (SPI/TWI config) switch, 1-17, 2-13
push button (SW11), 2-12 SW17 (Ethernet mode) switch, 2-14
restrictions, of evaluation license, 1-8 SW18 (Ethernet port 2 config) switch, 1-16,
RFS1 signal, 1-21 2-14
rotary encoder SW19 (encoder enable) switch, 1-16, 2-14
interface, 1-15 SW1 (boot mode select) switch, 1-12, 1-14, 2-8
enable switch (SW19), 1-15, 2-14 SW20-21 (eMMC enable) switches, 1-12
with momentary switch (SW14), 2-13 SW20 (eMMC enable) switch, 2-15
RS-232 connector (J2), 2-25 SW21 (eMMC enable) switch, 2-15
RTC pin, 1-20 SW22-23 (test) switches, 1-19, 2-15
SW2 (push button enable) switch, 1-21, 2-8,
S 2-13
schematic, of ADSP-BF518F EZ-Board, B-1 SW3 (flash enable) switch, 2-9
SD connector (J13), 2-26 SW4 (SPORT1 enable) switch, 1-18, 2-9
SDRAM interface, 1-10, 1-11 SW5 (mic gain) switch, 1-17, 2-10
SW6 (mic select) switch, 1-18, 2-10 universal asynchronous receiver transmitter, See
SW7 (Ethernet port 1 config) switch, 1-16, 2-11 UART0, UART1
SW8 (Ethernet config) switch, 2-11 USB monitor LED (LED4), 1-6
switches, diagram of locations, 2-7
system architecture, of this EZ-Board, 2-2
V
VDDEXT
T power jumper (P9), 2-19
thumbwheel control, xiv voltage domain, 1-24
TWI config switch (SW8), 1-17 VDDFLASH
power jumper (P11), 2-20
voltage domain, 1-24
U
VDDINT
UART0 interface power jumper (P8), 2-19
expansion interface II connectors (P2), 1-19, voltage domain, 1-24
2-27 VDDMEM
reset push button (SW11), 2-12 power jumper (P10), 2-20
setup switch (SW10), 2-12 voltage domain, 1-24
UART1 interface VisualDSP++ environment, 1-6
enable switch (SW14), 2-12 voltage planes, 1-23
expansion interface II connectors (P4), 1-19,
2-27
UART1_RX signal, 2-12, 2-18, 2-19 W
UART1_TX signal, 2-12, 2-18, 2-19 wall adaptor connector (J3), 1-6, 1-22
U-Boot, universal boot loader, 1-13 watchdog timer, 1-20