You are on page 1of 20

a-Si:H TFT LCD

(Fabrication & Design)

By Jong-Kwon Lee, Ph.D.

11th Nov. 2010


1. c-Si MOS vs a-Si TFT

• The similarity
: cleaning, deposition of thin films, photolitho., and wet & dry etching of the thin films
1. c-Si MOS vs a-Si TFT

• The difference
1) a-Si TFT on glass vs c-Si MOS on Si wafers
2) the process temp : a-Si TFT (250 ~350) vs c-Si MOS (~1,000℃)
• Critical issues in the processing of TFT arrays
:low-resistance gate-line, uniform & fine etching, and lithographic accuracy
to achieve high precision, large aperture ratio, low power,and large screen
 It is required to minimize the number of array processes by reducing the
number of photo masks and simplify thin-film-formation & etching process
2. Fabrication process of a-Si TFT
2. Fabrication process of a-Si TFT
3. Fabrication process of C/F

• Color filters (CFs) can be made with either dyes or pigments, utilizing coloring
method such as dyeing, diffusion, electro-deposition, and printing
3. Fabrication process of C/F
3. Fabrication process of C/F

• There are several fairly common color-element configurations for LCDs.


Stripe is the most popular, followed by mosaic and delta.
4. LC cell process

• The TFT-array and color-filter are made into an LCD panel by assembling the
two substrates together with a sealant, while the cell gap is maintained by spacers.
4. LC cell process

• After forming alignment layers on the lower panel of TFT and the upper panel of C/F,
scatter the spacers and print the seals to put together.
• After putting them together, inject liquid crystal into the inside using the capillary pheno-
menon and seal the inlet to finish the LCD process
5. Assembling LCD Modules

• When the polarizing plates are attached to the finished panel, the driver-IC is mounted
to it, PCB (Printed Circuit Board) is assembled and finally the backlight units and the
enclosure are assembled, the module is completed.
6. a-Si TFT structures

* Coplanar- type TFT : source/data and gate are formed in the same layer.
( most poly silicon)
* Stagged-ty[e TFT : source/drain and gate are formed at different layers
( most armorphous silicon)
: inverted staggered (bottom gate)/ Normal staggered (top gate)
7. a-Si TFT Design

The operational characteristics of a TFT are determined by the sizes of its electrodes,
the W/L ratio, and the overlap between the gate electrode and the source-drain
7. a-Si TFT Design

 Minimizing parasitic capacitance in TFTs


The parasitic capacitances resulting from the overlap of electrodes can not be avoided
in staggered TFT structures, but the parasitic effects must be minimized to maximize
the LCD's performance.
To reduce the overlap between the electrodes, a self-align process is often implemented .
7. a-Si TFT Design

 I-V Characteristics of an a-Si TFT and its operating points

• Vg at ~20 V for switch-on, or at -5 V for switch-off  on/off current ratio ≥ 106


• The performance of the TFT also depends on fabrication process parameters
(eg. electron mobility & Thickness of gate insulators)
• To increase the current gain of the TFT for better pixel-switching performance,
 increase the W/L ratio, then decrease aperture ratio
(display's brightness and contrast are reduced !) : Trade off relationship
7. a-Si TFT Design

 Storage Capacitor Design

The storage capacitor can be formed by using either an independent storage-capacitor


electrode or part of the gate bus-line as a storage-capacitor electrode

independent storage-capacitor Cs on gate capacitor


7. a-Si TFT Design

 Reduction of photo-induced leakage current in a TFT

• Because a-Si has photoelectric characteristics, the a-Si TFT must be shielded from
incident light .
• The a-Si layer must also be as thin as possible to minimize the generation of
photo-induced current, which can cause the TFT to malfunction.
7. a-Si TFT Design

 Light-shielding structures in a TFT-Array

• In the top-gate structure, a light-shield layer must first be formed at the region of
the TFT channel.(The formation of this light shield may cause an extra process step)
• In bottom-gate TFTs, a gate electrode is first formed at the TFT channel region,
where it also serves as a light-shield layer.
7. a-Si TFT Design

 Aperture Ratio

• The aperture ratio is given by the area of the pixel aperture divided by the total
pixel area (aperture area plus the area of the opaque elements).
: In the unit cell, TFT electrodes, storage-capacitor electrodes, signal bus-lines,
and the black-matrix material constitute opaque areas.
• To increase the aperture ratio as much as possible, the size of the opaque elements
must be made as small as possible, while maintaining a design that maximizes the
size of the pixel-electrode area
7. a-Si TFT Design

 Aperture Ratio

Improvement of aperture ratio using a Improvement of aperture ratio using an


black-matrix-on-TFT-array ITO layer as a Cs electrode

You might also like