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Name : .....................................
V Semester B.Tech. Degree Examination, June 2009
Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100
5. Design a synchronous counter using JK FF and external gates for the following
sequence 000, 101, 110, 111, 011, 010, 000.
6. Design a sequence generator for the following sequence 7, 5, 3, 2, 1 and display it.
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Batch 1
*3924A* (Page : 1) 3924 A
Reg. No. : ................................
Name : .....................................
2. Design and set up a 3 bit binary to gray and gray to binary code converter using
mode control switch.
Y = F (a, b, c) = ∑ (0, 1, 3, 5, 7)
4. Design and set up a 3 bit comparator using gates.
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Batch 2
3924A* (Page : 1) 3924 A
Reg. No. : ................................
Name : .....................................
2. A three stage counter must be designed that will count in two different modes
depending on logic level of control line. If control line is high the counter must
count 0, 2, 4, 6, 0. If the control line is low the counter must count up through all
eight states.
4. Set up a binary adder cum substractor using 2’s compliment form using IC 7483.
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Batch 3
3924A* (Page : 1) 3924 A
Reg. No. : ................................
Name : .....................................
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Batch 4
3924A* (Page : 1) 3924 A
Reg. No. : ................................
Name : .....................................
5. Design and setup a 3-bit synchronous down counter using JK Flip flop.
6. Design and setup a mode-6 synchronous self starting counter using JK Flip Flop.
Batch 5