Professional Documents
Culture Documents
Homework – 3
Date:
21/10/10
Ans:
Features of RISC:-
Uniform instruction format, using a single word with the opcode in the
same bit positions in every instruction, demanding less decoding;
Identical general purpose registers, allowing any register to be used in
any context, simplifying compiler design (although normally there are
separate floating point registers);
Simple addressing modes. Complex addressing performed via sequences
of arithmetic and/or load-store operations;
Few data types in hardware, some CISCs have byte string instructions,
or support complex numbers; this is so far unlikely to be found on a
RISC.
RISC chips require fewer transistors and cheaper to produce. Finally, it's
easier to write powerful optimized compilers. In common CISC chips
are relatively slow (compared to RISC chips) per instruction, but use
little (less than RISC) instructions.
RISC puts a greater burden on the software. Software developers need to
write more lines for the same tasks. In CISC, software developers no
need to write more lines for the same tasks.
Mainly used for real time applications Mainly used in normal PC’s,
Workstations and servers
Large number of registers, most of which can be used as general purpose
registers CISC processors cannot have a large number of registers.
RISC processor has a number of hardwired instructions. CISC processor
executes microcode instructions.
Ans:
It has been shown that some code optimization problems are NP-
complete, or even undesirable. In practice, factors such as the
programmer's willingness to wait for the compiler to complete its task
place upper limits on the optimizations that a compiler implementer
might provide. (Optimization is generally a very CPU- and memory-
intensive process.) In the past, computer memory limitations were also a
major factor in limiting which optimizations could be performed.
Because of all these factors, optimization rarely produces "optimal"
output in any sense, and in fact an "optimization" may impede
performance in some cases; rather, they are heuristic methods for
improving resource usage in typical programs
A compiler typically only deals with a part of a program at a time, often
the code contained within a single file or module; the result is that it is
unable to consider contextual information that can only be obtained by
processing the other files.
Ans:
Instructions are organized into lines in the memory and are loaded one
after the other.
The goal of the pipeline is to perform each step in parallel with the
preceding and following steps, meaning reading an instruction (FETCH)
while the previous step is being read (DECODE), while the step before
that is being executed (EXECUTE), while the step before that is being
written to the memory (MEMORY), and while the first step in the series
is being recorded in a register (WRITE BACK).
Part - B
Ans:
CISC Architecture
Instructions are of variable length and may sometimes require more than
one clock cycle. Because CISC-based processors can only process one
instruction at a time, the processing time is a function of the size of the
instruction.
RISC Architecture
Ans:
A superscalar CPU architecture implements a form of parallelism
called instruction level parallelism within a single processor. It therefore
allows faster CPU throughput than would otherwise be possible at a
given clock rate. A superscalar processor executes more than one
instruction during a clock cycle by simultaneously dispatching multiple
instructions to redundant functional units on the processor. Each
functional unit is not a separate CPU core but an execution resource
within a single CPU such as an arithmetic logic unit, a bit shifter, or a
multiplier. Super scaling consists of placing multiple processing units in
parallel in order to process multiple instructions per cycle.
Ans:
The processor (CPU, for Central Processing Unit) is the computer's
brain. It allows the processing of numeric data, meaning information
entered in binary form, and the execution of instructions stored in
memory.