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Objective:
General Instructions:
You are given 9 digital subsystems that are mostly used in processor design. You can
choose any one of them and follow the design methodology given below.
Only 6 groups (at the maximum) can register for any particular project out of 9 projects
listed. Projects would be allotted based on first come first register basis.
You need to work on SOC encounter, modelsim, RTL compiler, Leonardo spectrum etc.
Extra reading is required for understanding of these circuits. Also, self tool exploration is required for implementation
Design instructions:
Optimize your design for speed and power. Subsystem is a part of bigger synchronous design.
Refer to recent papers . Choose your own specs. As the assignment will be based on relative grading, the more
challenging you make from others the more marks you will be awarded. Challenging refers that how close are
your specs to the desired one.
Characterize your design by tabulating obtained values of all (maximum) parameters (specs) which you
studied in the class.
If you are not able to meet your specs, you can go ahead with system design, but you need to explain why it
has happened at the time of demonstration.
If required, you can change specifications. However you need to give a clear justification
Validate your design for all process corners and temperature Variation. Keep the power dissipation as small as
possible.
You should submit a soft copy of DETAILED report of your assignment to IC.
Your design should meet specification at all process corners with temperature varying from -40o to 125o C.
Common Specifications:
Circuits:
There are 10 digital circuits given below. Some of the required information with respect to particular circuit is
given to you. Typical values of performance parameters is also listed in a table
.For most of the circuits given switches are required. Implement Switch by simple NMOS or PMOS or both (to
decrease the ON resistance of it).
To remedy this problem, an additional circuit is typically used to synchronise the local clock to the reference clock.
Two common circuits which are used for this purpose are the PLL and the DLL.
USEFUL REFERENCE:
Uploaded on site
TOPIC 3: Design a HIGH SPEED TEN OPERANDS 128-BITS CARRY SAVE ADDER
The most important application of a carry-save adder is to calculate the partial products in integer multiplication. This
allows for architectures, where a tree of carry-save adders (a so called Wallace tree) is used to calculate the partial
products very fast. One 'normal' adder is then used to add the last set of carry bits to the last partial products to give
the final multiplication result. Usually, a very fast carry-look ahead or carry-select adder is used for this last stage, in
order to obtain the optimal performance.
Useful References:
USEFUL REFERENCE:
[l] N. Takagi, et al, “High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,” IEEE
Trans. on Computers, Vol.C-34, No.9, pp.789-796, September 1985.
[2] H.Makino, et al, “A 8.8-ns 54x54-bit Multiplier Using New Redundant Binary Architecture,” Proceedings of 1993
International Conference on Computer Design, Cambridge, MA, USA, pp.202-205, October 3-6, 1993.\
1.) CMOS VLSI Implementation of a Low-Power Logarithmic Converter Khalid H. Abed, Senior Member,
IEEE, and Raymond E. Siferd, Member, IEEE
2.) Useful reference ---------IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 11,
NOVEMBER 2003
Topic 6: Design a 32 bit x 32 Radix -4 SRT divider
Useful reference---Computer Arithmetic –algorithms and hardware design. By : Behrooz Parhami
Topic 7: Design of a fully pipelined CORDIC PROCESSOR for OFDM based WLAN
Useful reference --------European Journal of Scientific Research, ISSN 1450-216X Vol.27 No.4 (2009),
pp.588-596
Topic 8: Design of real time Autocorrelator to perform the autocorrelation of 128 samples each of 16
bits wide.
Topic 10: Design of programmable Ring Oscillator using 101or more inverter chain/s. There can be multiple
parallel chains of inverters which can be activated/ deactivated through a digital input to change the frequency of
the oscillator by a factor 2. You have to design standard cell for single inverter and explore tool to use this
standard cell to generate an automatic schematic driven layout. implement your design using your standard cell
in 180nm technology. (This is schematic driven layout)
Topic 12: Design and Implementation of High Speed DDR SDRAM( Dual Data Rate Synchronously
Dynamic RAM) Controller using (Verilog)
Useful reference: IEEE Explore