kBhilai School of Engineering, Durg.

CT-2 Examination-2011

Branch: ET&T SEM: 4th Duration: 2hr

Max.Marks: 50 Analog Electronic Circuits Min. Pass: 25

i) Question (1a) is compulsory which carries 2 Marks

ii) Question (a) is compulsory from each unit which carries 2 Marks.
iii) Questions from b , c, d write any two question from each UNIT which carries 7
Marks.

1(a) Draw the circuit diagram of an emitter follower and list three characteristics.

UNIT 1

a) State millers theorem.

Io
b) (i) For the circuit shown below in fig.1 Calculate AI = , R , & Av the h-parameter
Ii i
of transistor are hie = 2kΩ , hfe = 100, hre =2.5x10-4 , hoe=25µA/V.

Fig.(1)
(Or)
(ii) Calculate Ai , Ri, Av, Avs & Ais for the given Circuit fig 2.

Fig.(2)

1
c) (i) Draw the low frequency hybrid model for CE configuration and derive expression
of voltage gain, current gain and output admittance for CE configuration.

(or)

(ii) Find the voltage gain Avs , of the amplifier shown fig 3. Assume hie = 1000Ω,
hre =10-4 , hfe=50, hoe=10-4A/V

Fig.(3)

d) (i) Find hre in terms of common base h- parameters.

(Or)

(ii) Show the circuit diagram of common drain (CD) FET amplifier and show that its
voltage gain is less than unity.

UNIT 3
a) Mention the sources noise in transistor circuit.

b) (i) Define lower cut off frequency and upper cut off frequency. Derive the
expression for these frequency interms of circuit component. Draw frequency
response curve of an RC coupled amplifier.

(or)
(ii) A three stage RC coupled amplifier used FET with following parameters
gm= 25mA/V, rd=7.7KΩ, Rd=10kΩ and Rg=1MΩ, Ce =0.005µF per stage
calculate Av mid overall , fL and fH per stage and overall.
c) (i) (a) For the transistor CE stage shown in fig. 4 with 1/hoe =∞, calculate the
percentage tilt in the output if the input current I is a 100 Hz. Square wave.

(b) What is the lowest frequency square wave which will suffer less than 1 percent
tilt ?

2
 Fig.(4)

(or)

(ii) It is desired that the voltage gain of a RC coupled amplifier at 60Hz. should
not decrease more than 10% from its midband value. Show that the coupling
capacitor C must be equal to 5.5/R’ where R’=Ro’+Ri’ is expressed in kilo ohms
and C in microfarad.

d) (i) Explain various types of distortions in amplifier.

(or)

(ii) Define Noise . explain noise figure .derive the necessary Equation for noise
figure.

UNIT 2

a) Draw the hybrid π model for a transistor in common emitter configuration.

b) (i) Given the following transistor measurements made at Ic= 5mA, VCE=10 V, and
at room temp. hfe= 100, hie=600Ω, [Aie] = 10 at 10 MHz. Cc= 3 pF .
Find fβ, fT, Ce, rb’e, and rbb’ .

(Or)

(ii) Draw the circuit and derive the expression for CE short circuit current gain Ai
in terms of any frequency f and fβ of the BJT.

c) (i) The h-P parameter of the transistor used in the circuit shown in fig.5 Using
millers theorem and the approximate analysis, compute
(a) The upper 3dB frequency of the current gain Ai= IL/Ii .
(b) The magnitude of the voltage gain Avs= Vo/Vs at frequency of part(a).

3
 Fig.(5)

(ii) Consider a CE stage transistor amplifier with load resistance RL shunted by

capacitance CL.
V ce −g m R
(a) K= = L

V b e 1+ jw (C c +C L ) R L
(b) Prove that 3 dB frequency is given by:
1
fH≈
2 π (C c +C L ) R L
Provided that the following condition is satisfied:
gb e R L ( C c +C L ) ≫C e +C c (1+ gm RL )
'

d) i) Derive expression for the following parameters of small signal high frequency
hybrid π model of transistor amplifier:
(a) Transistor Transconductance gm
(b) Input conductance gb’e
(c) Output conductance gce

(or)

(ii) Derive equation for current gain of high frequency transistor with resistive
load RL.