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CHAPTER 8:

Counter & Register


8.0 – Introduction to counter
8.1 – Asynchronous counter
8.2 – Synchronous counter
8.3 – Up & Down Synchronous counter

8.4 – Integrated circuit register


8.5 – Serial-In/Serial-Out
8.6 – Serial-In/Parallel-Out
8.7 – Parallel-In/Serial-Out
8.8 – Parallel-In/Parallel-Out
8.9 – Ring counter

8.0 Introduction to Counters


• Counting is a fundamental function of digital circuits
• Counters are devices which have a CLOCK input and produce n outputs.
• Counters consists of flip-flop connected together in specific ways such that on
each clock edge the output change.
• n flip-flops are required for an n-bit output counter.
• Normally, the effect of this change is to generate an output that is in some way
related to the previous output numerically (Pattern).
• For example, every time a clock edge is detected the output could increase by 1.
• Therefore, for n=3 (3 flip-flop); can write a table that illustrates this.

After the 8th clock edge, the counter


start again 0.
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• depends on previous output • have same control input for each
flip flop which is the clock
• have propagation delay
• have less propagation delay

COUNTERS
• The flip-flops can be connected in one or two ways, to produce either asynchronous
counters or synchronous counters:

- Asynchronous counters (Ripple counter)


All the inputs are the same (tied HIGH) and the
output of each flip-flop is connected to the CLK
of the next flip-flop.

- Synchronous counters
All the CLKs of each flip-flop are connected
to a common CLOCK, and the inputs are a
combinations of the previous outputs.

• The least-significant bit (LSB) is shown on the left and the most-significant bit (MSB)
is shown on the right.
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JK Flip flop as basic function for counters:
•A JK flip flop toggles when both inputs are 1. In this case it
effectively counts every second clock pulse:

J
Q
1

clock

~Q
K

clock
You can also say
it counts from 0 to
1 and back again.
Q

Sometimes called a “scale of 2 counter”

8.1 ASYNCHRONOUS COUNTER OPERATION


2-Bit Asynchronous Binary Counter: Connect two such flip flops together:

Q1 1 Q2
1

clock

• The clock (CLK) is applied to the clock input of only the first flip-flop FF0, which
always the LSB.
• The two flip-flops are never simultaneously triggered, so the counter operation is
asynchronous.
Complete the
clock timing diagram for
Q2
Q1
Outputs Q1 and Q2
Q2 cycle.

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ASYNCHRONOUS COUNTER OPERATION
Propagation Delay
Asynchronous counters are commonly referred to as ripple counters for the
following reason.
– The effect of the input clock pulse is first “felt” by FF0.
– This effect cannot get to FF1 immediately because of the propagation
delay through FF0.
– Then, there is the propagation delay through FF1 before FF2 can be
triggered.
– Thus, the effect of an input clock pulse ‘ripples’ through the counter, taking
some time, due to propagation delays, to reach the last flip-flop.

A 3-Bit Asynchronous Binary Counter

Qa Qb Qc
-A 3-bit asynchronous
binary counter is shown 1 J Q 1 J Q 1 J Q
in figure beside.
-It has eight sates, due clk
to its three flip-flops. 2n 1 1 1
K Q K Q K Q

– These propagation delays cause a number of


sequence changes when going from one number to
the next, which can be undesirable in a lot of
situations.
– The counter can get the wrong value at a particular
instant in time
– Operating speed is therefore limited. 8

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A 4-Bit Asynchronous Binary Counters

ASYNCHRONOUS DECADE COUNTER

• Also known as truncated asynchronous counters.


• Modulus of a counter is the number of unique states that the counter will
sequence through.
• The key to implement truncated asynchronous counters is to detect the first
undesired state then RESET the flip-flops to zero that are not already zero.

Example:
An asynchronous counter is required that counts from 0 to 9 before staring again at 0 again.

Solution
Step 1
We must determine how many flip-flops are required to implement a counter that counts to 9.
4 bits are required and hence 4 flip-flops will be used to implement the counter.

Step 2
We must detect when state 10 is output by the counter, i.e, when Q3Q2Q1Q0 = 1010.
When we detect this state, we need to output a zero to those flip-flops not already zero.
In order to output a zero, we can used a NAND gate circuit.

10

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Hence our circuit for detecting the presence of a 10 can
be simplified to:

This is possible because states 11, 12, 13, 14 and 15


cannot occur as the counter is RESET when 10 is
detected. However the previous circuit is perfectly
acceptable.

Step 3
We must decide on which flip-flops need to be RESET. When state 10 is detected Q0 and
Q2 are already zero, therefore they do not need to be RESET. However Q1 and Q3 are
both 1 so they must be RESET to 0. Hence the output of the detection circuit must be
connected to their CLR inputs.
The circuit required therefore is :

Replace T with J-K.


T FF equal to JK FF
with both inputs are
connected together

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8.2 SYNCHRONOUS COUNTER OPERATION


With respect to counter operation, synchronous means that all the flip-flops in the
counter are clocked at the same time by a common clock pulse.

A 2-Bit Synchronous Binary Counter


Qa Qb Operation used: will be either 00-NC,
or 11-Tgl
1 J Q J Q

1 K Q K Q

clk
1
C
0

Qa 0
1

Qb 0

00 01 10 11 00 01 12

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SYNCHRONOUS COUNTER OPERATION
A 3-Bit Synchronous Binary Counter

Qa Qb Qc

1
Qc should not toggle
J Q J Q J Q
until both Qa and Qb
are 1
1 K Q K Q K Q

clk

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SYNCHRONOUS COUNTER OPERATION


A 4-Bit Synchronous Binary Counter
The particular counter is implemented with negative-triggered flip-flops.

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Example: Design a 3 bit Gray code with sequence below by using
JK Flip Flop

?? So how??...in other
words…it should be a
design process to
implement counters with
all sort of sequences…

A summary of steps used in the design of this counter follows. In general, these
steps can be applied to any sequential circuit.

1. Specify the counter sequence and draw the a state diagram.

2. Derive a next-state table from the state diagram.

3. Develop a transition table showing the flip-flop inputs required for each
transition. The transition table is always the same for a given type of flip-flop.

4. Transfer the J and K states from the transition table to Karnaugh maps. There is
a K map for each input of each flip-flop.

5. Group the K map cells to generate and derive the logic expression for each flip-
flop input.

6. Implement the expressions with combinational logic, and combine with the flip-
flops to create the counter.
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Example: Design a 3 bit Gray code by using JK Flip Flop

Step 1: State Diagram

Step 2: Next State Table

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Step 3: Flip flop Transition Table

Step 4: Karnaugh Maps

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Step 5: Logic Expressions for Flip Flop Inputs

J 0  Q2Q1  Q2 Q1  Q2  Q1
K 0  Q2 Q1  Q2Q1  Q2  Q1
J1  Q2Q0
K1  Q2 Q0
J 2  Q1 Q0
K 2  Q1 Q0

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Step 6: Implementation

Example: Design a counter for the sequence of: 000, 010, 011, 101, 110
using J-K FF
Step 1: Derive the State Transition Diagram

000 110

010 101

011
Present Next
State State
CBA C+ B+ A+
Step 2: Next State Table 000 0 1 0
001 X X X
010 0 1 1
011 1 0 1
100 X X X
101 1 1 0
110 0 0 0
111 X X X

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Step 3: State Transition Table

Present Next
Remapped Next State
State State
Q Q+ J K C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 X 0 0 0 0 1 0 0 X 1 X 0 X
0 1 1 X 0 0 1 X X X X X X X X X
1 0 X 1 0 1 0 0 1 1 0 X X 0 1 X
X 0 0 1 1 1 0 1 1 X X 1 X 0
1 1
1 0 0 X X X X X X X X X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 X X X X X X X X X

Step 4: Karnaugh Maps Step 5: Logic Expressions


for Flip Flop Inputs
CB CB
A A X X 1 X
0 0 X X JC KC
X 1 X X X X X 0
JC = A
CB CB KC = A
A A
1 X X X X 0 1 X
JB KB JB = 1
X X X 1 X 1 X X
KB = A + C
CB
A 0 1 0 X ACB JA = B C
JA
X X X X KA
X X X X X 0 X 1 KA = C

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Step 6: Implementation

+
JC = A
C B A KC = A
A J Q J Q JA J Q
CLK CLK CLK
\A K Q KB K Q C K Q
\C \B \A JB = 1
Count

KB = A + C

A B JA
JA = B C
C KB \C
KA = C

8.3 UP/DOWN Synchronous Counters


 Capable of progressing in either direction through a certain sequence.
 Sometimes called a bidirectional counter, can have any specified sequence of
states.
 Can be reversed at any point in their sequence.
 For instance, the 3-bit counter can be made to go through the following sequence:
UP
0, 1, 2, 3, 4, 5, 6, 7, 0……

DOWN

 An up/down counter also can be in following sequence:


UP
3, 2, 6, 4, 7, 3,……

DOWN

 To implement up/down counter, the previous process design can be use but with
additional control input to control the sequence whether it is in up manner(control
input should be in high state=1) or down manner(control input should be in low
state=0).
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8.4 Integrated Circuit Registers

• Shift Registers, for data storage and data movement


• Concept of storing a 1 or 0 in a D Flip Flop is shown

Types of Registers

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8.5 Serial In/Serial Out Registers

An 8 bit Shift Register

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8.6 Serial In/Parallel Out Registers

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The 74HC164 8-bit serial in/parallel out shift register.

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8.7 Parallel In/Serial Out Register

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The 74HC165 8-bit parallel load shift register.

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8.8 A parallel in/parallel out register

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8.9 Ring Counters

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Clock Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Pulse
0 1 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0

2 0 0 1 0 0 0 0 0 0 0

3 0 0 0 1 0 0 0 0 0 0

4 0 0 0 0 1 0 0 0 0 0

5 0 0 0 0 0 1 0 0 0 0

6 0 0 0 0 0 0 1 0 0 0

7 0 0 0 0 0 0 0 1 0 0

8 0 0 0 0 0 0 0 0 1 0

9 0 0 0 0 0 0 0 0 0 1

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