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• depends on previous output • have same control input for each
flip flop which is the clock
• have propagation delay
• have less propagation delay
COUNTERS
• The flip-flops can be connected in one or two ways, to produce either asynchronous
counters or synchronous counters:
- Synchronous counters
All the CLKs of each flip-flop are connected
to a common CLOCK, and the inputs are a
combinations of the previous outputs.
• The least-significant bit (LSB) is shown on the left and the most-significant bit (MSB)
is shown on the right.
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JK Flip flop as basic function for counters:
•A JK flip flop toggles when both inputs are 1. In this case it
effectively counts every second clock pulse:
J
Q
1
clock
~Q
K
clock
You can also say
it counts from 0 to
1 and back again.
Q
Q1 1 Q2
1
clock
• The clock (CLK) is applied to the clock input of only the first flip-flop FF0, which
always the LSB.
• The two flip-flops are never simultaneously triggered, so the counter operation is
asynchronous.
Complete the
clock timing diagram for
Q2
Q1
Outputs Q1 and Q2
Q2 cycle.
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ASYNCHRONOUS COUNTER OPERATION
Propagation Delay
Asynchronous counters are commonly referred to as ripple counters for the
following reason.
– The effect of the input clock pulse is first “felt” by FF0.
– This effect cannot get to FF1 immediately because of the propagation
delay through FF0.
– Then, there is the propagation delay through FF1 before FF2 can be
triggered.
– Thus, the effect of an input clock pulse ‘ripples’ through the counter, taking
some time, due to propagation delays, to reach the last flip-flop.
Qa Qb Qc
-A 3-bit asynchronous
binary counter is shown 1 J Q 1 J Q 1 J Q
in figure beside.
-It has eight sates, due clk
to its three flip-flops. 2n 1 1 1
K Q K Q K Q
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A 4-Bit Asynchronous Binary Counters
Example:
An asynchronous counter is required that counts from 0 to 9 before staring again at 0 again.
Solution
Step 1
We must determine how many flip-flops are required to implement a counter that counts to 9.
4 bits are required and hence 4 flip-flops will be used to implement the counter.
Step 2
We must detect when state 10 is output by the counter, i.e, when Q3Q2Q1Q0 = 1010.
When we detect this state, we need to output a zero to those flip-flops not already zero.
In order to output a zero, we can used a NAND gate circuit.
10
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Hence our circuit for detecting the presence of a 10 can
be simplified to:
Step 3
We must decide on which flip-flops need to be RESET. When state 10 is detected Q0 and
Q2 are already zero, therefore they do not need to be RESET. However Q1 and Q3 are
both 1 so they must be RESET to 0. Hence the output of the detection circuit must be
connected to their CLR inputs.
The circuit required therefore is :
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1 K Q K Q
clk
1
C
0
Qa 0
1
Qb 0
00 01 10 11 00 01 12
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SYNCHRONOUS COUNTER OPERATION
A 3-Bit Synchronous Binary Counter
Qa Qb Qc
1
Qc should not toggle
J Q J Q J Q
until both Qa and Qb
are 1
1 K Q K Q K Q
clk
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Example: Design a 3 bit Gray code with sequence below by using
JK Flip Flop
?? So how??...in other
words…it should be a
design process to
implement counters with
all sort of sequences…
A summary of steps used in the design of this counter follows. In general, these
steps can be applied to any sequential circuit.
3. Develop a transition table showing the flip-flop inputs required for each
transition. The transition table is always the same for a given type of flip-flop.
4. Transfer the J and K states from the transition table to Karnaugh maps. There is
a K map for each input of each flip-flop.
5. Group the K map cells to generate and derive the logic expression for each flip-
flop input.
6. Implement the expressions with combinational logic, and combine with the flip-
flops to create the counter.
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Example: Design a 3 bit Gray code by using JK Flip Flop
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Step 3: Flip flop Transition Table
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Step 5: Logic Expressions for Flip Flop Inputs
J 0 Q2Q1 Q2 Q1 Q2 Q1
K 0 Q2 Q1 Q2Q1 Q2 Q1
J1 Q2Q0
K1 Q2 Q0
J 2 Q1 Q0
K 2 Q1 Q0
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Step 6: Implementation
Example: Design a counter for the sequence of: 000, 010, 011, 101, 110
using J-K FF
Step 1: Derive the State Transition Diagram
000 110
010 101
011
Present Next
State State
CBA C+ B+ A+
Step 2: Next State Table 000 0 1 0
001 X X X
010 0 1 1
011 1 0 1
100 X X X
101 1 1 0
110 0 0 0
111 X X X
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Step 3: State Transition Table
Present Next
Remapped Next State
State State
Q Q+ J K C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 X 0 0 0 0 1 0 0 X 1 X 0 X
0 1 1 X 0 0 1 X X X X X X X X X
1 0 X 1 0 1 0 0 1 1 0 X X 0 1 X
X 0 0 1 1 1 0 1 1 X X 1 X 0
1 1
1 0 0 X X X X X X X X X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 X X X X X X X X X
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Step 6: Implementation
+
JC = A
C B A KC = A
A J Q J Q JA J Q
CLK CLK CLK
\A K Q KB K Q C K Q
\C \B \A JB = 1
Count
KB = A + C
A B JA
JA = B C
C KB \C
KA = C
DOWN
DOWN
To implement up/down counter, the previous process design can be use but with
additional control input to control the sequence whether it is in up manner(control
input should be in high state=1) or down manner(control input should be in low
state=0).
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8.4 Integrated Circuit Registers
Types of Registers
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8.5 Serial In/Serial Out Registers
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8.6 Serial In/Parallel Out Registers
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The 74HC164 8-bit serial in/parallel out shift register.
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8.7 Parallel In/Serial Out Register
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The 74HC165 8-bit parallel load shift register.
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8.8 A parallel in/parallel out register
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8.9 Ring Counters
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Clock Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Pulse
0 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0 0
5 0 0 0 0 0 1 0 0 0 0
6 0 0 0 0 0 0 1 0 0 0
7 0 0 0 0 0 0 0 1 0 0
8 0 0 0 0 0 0 0 0 1 0
9 0 0 0 0 0 0 0 0 0 1
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