CHAPTER 7

LATCH AND FLIP-FLOP

SEQUENTIAL CIRCUIT
 Called a circuit with memory.
 The output signals depend not only on the current
inputs, but also the past sequence of input variables.
 Two types of sequential circuits:
• Synchronous sequential circuits
• Asynchronous sequential circuits

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I) SYNCHRONOUS SEQUENTIAL CIRCUIT

• the output changes state only at a specified point on a triggering

input called the clock (CLK), which is designated as a control input,
C

• That is, the changes in the output occur in synchronization with the
clock.

II) ASYNCHRONOUS SEQUENTIAL CIRCUIT

• depends on the inputs at only instance of time, which

the input change.

• Refer to the events that do not have fixed time

relationship with each other, and generally do not occur
at the same time
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TERMINOLOGY

Multivibrator A class of digital circuits in which the output is connected

back to the input to produce either two stable states, one
stable states, or no stable states, depending on the
configuration.

Bistable Having two stable states. Flip-flop and latches are bistable
multivibrators.

Latch An asynchronous bistable multivibrator, used for

storing 1 bit.

Flip-Flop A synchronous bistable multivibrator, used for

storing 1 bit.

Asynchronous There is not fixed timing relationship.

Synchronous There is a fixed timing relationship, usually

through the use of a clock pulse
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 Multivibrators

Bistable Monostable Astable

Asynchronous synchronous
S-R
Latch Flip-Flop
D

Gated Gated
S-R J-K
S-R D 5

LATCHES (SELAK)
 The latch is a type of temporary storage device that has two
stable states (bistable).

 Basically is similar to FF because they are bistable devices that

can reside in either of two states using a feedback arrangement.

 The main difference between latches and FF is in the method

used for changing their state.

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 Asynchronous

Latch

Gated Gated
S-R
S-R D

The S-R (SET-RESET) Latch (74LS279)

 An active-HIGH input S-R (SET-RESET) latch is formed with two cross-
coupled NOR gates.

 An active-LOW input S  R latch is formed with two cross-coupled NAND

gates.

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 The S-R Latch

 To explain the operation of the latch, we will use the OR gates with
negative/low inputs.
 The latch is redrawn with the negative-OR equivalent symbols used for
NAND gates.

Negative-OR equivalent of
the NAND gate S  R latch.

When Q is HIGH, Q is LOW, and when Q is LOW, Q is HIGH.

The S-R Latch

We can replace the S and R with the less confusing A and B respectively.

1) Let start by assuming that both inputs are 1 and Q = 1, therefore

i) Let input A change to 0: ii) Let input A change back to 1:

For case i and ii , there is no change in Q, hence Q’ remains the same.

Summary:
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 The S-R Latch

2) Let input B change to 0:

Q changes to 0, hence Q’ change to 1

The circuit is now in a stable state.

Summary:
If Q=1, Q’=0, A=1  changing B from 1 to 0  RESETs Q to 0, Q’
to 1
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The S-R Latch

3) Let input A changes to 0:

Q will change to 1 and Q’ will change to 0

The circuit now in stable state.

Summary:
IF Q=0, Q’=1, B=1; A change from 1 to 0  SET Q to 1 and Q’ to 0.

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6
 The S-R Latch

4) Previously we had A=0, B=1, Q=1 and Q’=0, let change B to 0.

Clearly, it is and INVALID Condition. Because Q=Q’

Summary:
The case of A=B=0 is to be avoided.

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The S-R Latch

All this can summarized in the following truth-table:

A latch can reside in either of its two

states, SET or RESET
SET means that the Q output is HIGH.
RESET means that the Q output is
LOW.

Logic symbols for both the active-HIGH input and the active-LOW input latches
are shown in figure below:

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The S-R Latch -- EXAMPLE

If the S and R waveforms in figure (a) below are applied to

the inputs of the active-LOW input S  R latch, determine the
waveform that will be observed on the Q output. Assume Q is
initially LOW.

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S-R Latch Application

If the switch bounce, If the switch bounce,

means it is between
position 1 & 2,
output will high. As
long as switch DC
from point 2, output
will be high
means it is between
position 1 & 2,
output will maintain
because S-R will
both high, means NC
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 The Gated S-R Latch
• A gated latch requires an enable input, EN.
• When EN input = HIGH ==> the S and R inputs control the state to
which the latch will go.
• The latch will not change until EN is HIGH.
• As long as EN remains HIGH, the output is controlled by the state of
the S and R inputs.
• The invalid state occurs when both S and R are simultaneously HIGH.

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S R Q Q’ Status

0 0 NC NC Remain

0 1 0 1 Reset

1 0 1 0 Set

1 1 1 1 Invalid

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Example (Gated S-R Latch)

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The Gated D Latch

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 21

Example (Gated D Latch)

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 synchronous
S-R
Flip-Flop
D

J-K

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Clock Pulse, Edge-Triggering

• The transition from state 0 to state 1 is called leading / positive / rising
edge of the pulse.
• The transition from state 1 to state 0 is called trailing / negative / falling
edge of the pulse.
• The triggering of flip-flops can occur either at positive edge or negative edge.
• The time during which the clock is at logic 1 is called enable and the time
during which the clock is at logic 0 is called disable.
• Unlike enable in latch, CLK just activate on the trigger time only not all on the
enable time.
Enable Trailing (negative)
edge

Leading (positive)
edge Diable
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Clock Pulse

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 Edge-Triggered Flip-flops
• The most important memory element is the flip-flop., which is made up
of an assembly of logic gates.

Normal output
Q
1. Q =1, Q’=0 called HIGH state
. or SET state.
Inputs .
.
.
Inverted output
2. Q =0, Q’=1  called LOW state
or RESET state.

• An edge-triggered flip-flop changes state either at the positive edge

(rising edge) or at the negative edge (falling edge) of the clock pulse.
• It is sensitive to its inputs only at this transition of the clock.
• Flip-flop cannot change state except on the triggering edge of its clock
pulse.

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The Edge-triggered S-R Flip-flop

Truth-table for a positive edge-triggered

S-R Flip-flop.

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What happen to the output
of gated SR at this point if CLK is the input
to the enable port? Get the difference
Enable & CLK

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The Edge-Triggered D Flip-Flop

• One problem with S-R Flip-Flop is that there can be a 1 on the Q and a
1 on the Q when the SET and RESET inputs are both 1.  invalid
condition.
• This problem can be alleviated by placing an inverter between the SET
and RESET inputs, as shown in figure below.
• This makes a new input which we call the D input.
• Notice that: the SET and RESET inputs can never be the same value
because of the inverter  The unused state never exist.
•
•The D flip-flop is used to store bits of
binary numbers.
•It can be used as the output port of a
microcomputer.

1 – Set
0 - Reset

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 Example:
Given the waveforms in figure (a) below for the D input and the
clock, determine the Q output waveform if the flip-flop starts out
RESET.

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The Edge-Triggered J-K Flip-Flop

• The J-K flip-flop is versatile and is widely used type of flip-flop.

• The S-R edge-triggered flip-flop can be modified to become J-K edge-
triggered flip-flop. The circuit is shown below.

• As can be seen the only changes in the JK flip-flop from the SR flip-flop
are the additional feedback lines from the outputs to the opposite
steering gates.

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 The Edge-Triggered J-K Flip-Flop

• The difference between the SR flip-flop and JK flip-flop is:

 JK flip-flop has no invalid state as does the SR flip flop.

Summarized Truth-table Logic Symbols

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Example

The waveforms in figure (a) below are applied to the J, K and

clock inputs as indicated. Determine the Q output, assuming
that the flip-flop is initially RESET.

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 Asynchronous Inputs
• Operate independently of the synchronous inputs and clock input
• Can be used to set the flip-flop to the 1 state or clear the flip-flop to 0
state at any time, regardless of the conditions at the other inputs.

PRESET CLEAR Flip-flop response

1 1 Clocked operation.
0 1 Q =1 (regardless of clock)
1 0 Q = 0 (regardless of clock)
0 0 Not used. (will give ambiguous response)

Designations for Asynchronous Inputs

• There are PRE, CLR, SD and RD.
• But, the most common used designations are PRE and CLR.
• For the active-LOW status, we will use overbar to indicate them.

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Asynchronous Preset and Clear Inputs

• Most integrated circuit flip-flop also have asynchronous inputs.

• These are inputs that affect the state of the flip-flop independent of the
clock.
• An active level on the preset input will set the flip-flop.
• An active level on the clear input will reset the flip-flop.
• These preset and clear inputs must both be kept HIGH for
synchronous operation
.

Logic symbol for a JK flip-flop with Logic diagram for a basic JK flip-flop
active LOW preset and clear inputs with active LOW preset and clear
inputs. 34

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 Example:

For a positive edge-triggered JK flip-flop with preset and clear

inputs in figure below, determine the Q output for the inputs
shown in the timing diagram in part (a) if Q is initially LOW.

Flip-flop 7476

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Flip-flop 7474

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 Flip-flop Timing Considerations (Pg. 390-393)

Manufactures of IC flip-flop will specify several important timing

parameters and characteristics that must be considered before a FF
is used in any circuit application.

1. Set-up Time (ts)

- is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, S and R or D)
prior to the triggering edge of the clock pulse.

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2. Hold Time (th)

- is the minimum interval required for the logic levels to remain on
the inputs after the triggering edge of the clock pulse.

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3. Propagation Delays
- is the interval of time required after an input signal has been
applied for the resulting output change to occur.
- 4 categories of propagation delay are important in the operation of
a FF.

Measured from the triggering edge of Measured from the triggering

the clock pulse to the LOW-to-HIGH edge of the clock pulse to the
transition of output. HIGH-to-LOW transition of
output.
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Measured from the leading Measured from the leading

edge of the preset input to the edge of the clear input to the
LOW-to-HIGH transition of the HIGH-to-LOW transition of
output. the output.

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4. Maximum Clocking Frequency, fMax
- is the highest frequency that may be applied to the CLK input of
a FF.
- or is the highest rate at which FF can be reliably triggered.
- at clock frequencies above the maximum, the FF would be
unable to respond quickly enough, and the operation would be
impaired.
- eg: For 7470 J-K flip-flop IC, its f MAX fall in the range 20 to 35
MHz. So, he will specify the minimum f MAX as 20 MHz. This
means that; he cannot guarantee that the 7470 FF that you put in
your circuit will work above 20MHz. But, if you operate them
below 20MHz, however; he guarantees that they will all work.

5. Pulse Widths (tw) / Clock Pulse HIGH and LOW times

- the minimum time duration that the CLK signal must remain
LOW before it goes HIGH, sometimes called tw (L), and the
minimum time that CLK must kept HIGH before it returns LOW.
Sometimes called tw (H).

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6. Power Dissipation
- is the total power consumption of the device.
- Example:
If the FF operates on a +5V dc source and draws 5mA of current,
the power dissipation is:
P  VCC  5mA  25mW

- Power dissipation is very important in most applications, in

which the capacity of dc supply is concern.
- Example:
PT  10  25mW  250 mW  0.25W
- It also tells you the output capacity required of the dc supply.
- Example:
If the FF operates on +5V dc, then the amount of current that the
supply must provide is:

250mW
I  50mA
5V

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Actual ICs

As practical examples of these timing parameters, let’s take a look at several

actual integrated-circuit FFs.
In particular, we will look at the following ICs:

 7474 Dual edge-triggered D flip-flop (standard TTL)

 74LS112 Dual edge-triggered J-K flip-flop (low power Schottky TTL)
 74C74 Dual edge-triggered D flip-flop (metal-gate CMOS)
 74HC112 Dual edge-triggered J-K flip-flop (high-speed CMOS)

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Flip-Flop Applications
1. Contact Bounce Elimination

- When a mechanical switch is closed, the poles of the switch vibrate

or bounce a number of times before finally making a solid contact.
- this bounces may produce voltage spikes, as shown in figure (a).
- Such voltage spikes are not desirable in a digital system.

- An SR latch can be used to eliminate the contact bounce as shown in

figure (b).
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 - The normal position of switch is 1.
- This R input is LOW and latch is in RESET position.
- When switch is thrown to position 2, R goes HIGH due to
presence of pull up resistor to VCC and S goes to LOW on the
first contact.
- This SETs the latch.
- Any further voltage spikes on the S input do not affect the latch
and it remains SET.
- The Q output makes a clean transition from LOW to HIGH and
voltage spikes due to contact bounce are eliminated.
- A similar clean transition occurs when the switch is brought back
to position 1.

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2. Parallel Data Storage in Registers

- Data storage is an important aspect of digital systems.

- Many data bits are taken on parallel lines and stored
simultaneously in a group of flip-flops.
- Figure (a) shows this parallel data input.
- The data inputs are connected to D0, D1 and D2.
- The clock inputs of all the three flip-flops are tied together
and connected to common clock input.
- This ensures that all the three flip-flops are triggered together.
- As shown in Figure (a), positive edge triggering is used in
this case.
- Therefore, the data is stored in flip-flops on the positive
edge of the clock.
- All the CLR terminals are also connected together, so that all
the three flip-flops are reset together.
- Groups of FF used to store data are known as registers in
computer terminology.

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 FF used in a basic
register for parallel
data storage

In digital systems, data

are normally stored in
groups of bits, that
represent numbers,
codes or other
information.

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3. Frequency Division
- Divide (reduce) the frequency of a periodic waveform.
- When a pulse of waveform is applied to the clock input of a J-K
flip-flop that is connected to toggle (J=K=1), the output is a
square wave with one-half the frequency of the clock input.
- Thus, a single flip-flop can be applied as a divide-by-2 device, as
illustrated in figure below.
- This results in an output that changes at half the frequency of the
clock waveform.

Q is one-half the frequency

of CLK.

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 • Further division of a clock
frequency can be achieved by
using the output of one FF as the
clock input to a second FF, as
shown in figure beside.

• The frequency of the QA output is

divided by 2 by FF B.

• The QB output is, therefore, one-

fourth the frequency of the original
clock input.

• By connecting the FF in this way, a

frequency division is achieved.
(n = num of FF)

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4. Counting

• Concept for digital counters.

• As illustrated in figure beside, there
are negative edge-triggered JKs.
• Both FF are initially RESET.
• FF A toggles on the –ve-going
transition of each clock pulse.
• The Q output from FF A clocks FF
B.
• The waveforms are shown.
• If we take QA as LSB, a 2-bit
sequence produce as the FF are
clocked.
• The binary sequence repeats every
four clock pulse.
• This the FF are counting in
sequence from 0 to 3 (00, 01, 10,
11) and then recycling back to 0 to
begin the sequence.
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THE END

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