R

ALLIANCE
Series Software

Synopsys FPGA Express

Implementation Flow
Module Generators

LogiBLOX CORE Generator

.V .VEI .VEO Verilog & VHDL

.VHD .NGC= Xilinx Binary NGC Instantiation
.VHI .VHO
Netlist

State Diagram
State Diagram SchematicDesign
Schematic Design
HDL Editor
HDL Editor
Editor
Editor Editor
Editor

Xilinx
VHDL VHDL XNF
EDIF VHDL EDN
Verilog Verilog Verilog Macros
Library

Functional
Simulation Flow Timing
Requirements

Timing
CORE Simulation
Generator Flow
VSS
VSS Xilinx XNF
VHDL
VCS
VCS Verilog
I
LogiBLOX or
or M
SDF
P
3rd
3rd L FPGAExpress
UNIFIED E
Party
Party M
Gates EDIF E
N Behavioral
SS T VHDL
NCF
UniSim
II A XNF
Verilog

VITAL, Verilog, M
M T
BIT
Gates JEDEC I
U
U O EDIF
LL N
SimPrim
A
A EDIF for Virtex, VirtexE,
Spartan II
VITAL, Verilog,
Gates TT
Reports Tools User
HDL II Constraints
Test Bench File
O
O
N
N
Command
File
or g
EDDIE 1999 Functional Simulation Flow
Test Vectors EG

PN 0010416 01
 R

ALLIANCE
Series Software

Synopsys FPGA Express

Information
Guide Overview

Device Architecture Support

FPGA Product Family
1
Create a project
Go to menu File New and define a new project.
All HDL files processed by FPGA Express must be
Spartan done through a project.
Virtex
XC4000X

CPLD Product Family

XC9500
2
Add HDL files to project and
analyze HDL files
After creating project, HDL design files can be
added to the project. After adding the HDL
design files, FPGA Express will automatically
analyze the HDL files.
Xilinx
Contacts and Technical Support

World Wide Web:

3
Implement the design
Select the top-level module/entity in the
Design Sources window and the implement
http://www.xilinx.com
button will be highlighted.
Click on the implement button and specify the
North America France
target die, speed grade and package.
1-800-255-7778 33 1-3463-0100
Strategies for synthesis can be specified during
hotline@xilinx.com frhelp@xilinx.com
implementation.
United Kingdom Japan
44 1932-820821
ukhelp@xilinx.com
81 3-3297-9163
jhotline@xilinx.com
4
Enter constraints
In the Chips window, select the implementation.
Right-click on the selected implementation and
Synopsys select Edit Constraints. A window will appear
Contacts and Technical Support where various constraints can be edited.
After entering constraints, save constraints by
World Wide Web: closing the constraints window.

5
http://www.synopsys.com
United States Optimize the design
1-800-245-8005
Click on the optimize button located next to the
support_center@synopsys.com
implement button to synthesize the design OR
select the menu Synthesis Optimize Chip

6
Place & Route XNF or EDIF file
with A2.1i
After optimization, write out the XNF or EDIF file
by clicking on the Export Netlist button next to
the implement button. Place and Route the XNF
or EDIF file using A2.1i implementation tools
with the Design Manager GUI or DOS shell
PN 0010416 01 based commands.