601

t B. E. (Computer Engg.) VIIth Semester Examination,

.
. December-2002

ADVANCE COMPUTER ARCHITECTURE Paper-

CSE-40 l-C
Time allowed: 3 hours Maximum Marks: 100

Note: Attempt any five questions . .•.

1. (a) What do you mean by micro-programming? Explain

vertical and horizontal micro-instructions. 10

(b) The logical address space in a computer consists of 128

segments. Each segment can have up to 32. pages of 4 k
words in each. Physical memory consists of 4 k blocks of
4 k words in each. Formulate the physical and logical
address formats. 10

2. (a) Compute the area in rbe with and without aspect mismatch
adjustment of a 32 KB direct mapped cache
. with 256 bit lines and 20-bit tag. 10
(b) Explain in brief the various phases in a processor
design project. 10

3. What do you mean by process management? Explain in brief

the following :
\:--,~';"'!"~'JI"'"!-(":",,,;,:.;,:"o;., .• :~.
 ( 2 ) (3)

4. (a) What do you mean by dynamic pipeline? Explain vari,)US (b) Assume a CBWA Cache with write (dirty line) buffer;
levels of dynamic pipei ine sophistication. find T . and T . , Tb .
m. miss c.mlSS usy
1 (c) Repeat the problem assuming both a dirty line buffer'
0
(b) WhLt is the effect of using buffers on the instructions and wrap-around load. 20
execution ? Discuss the design .)f a buffer. 10
7. (a) Describe different vector instructions a..nd operations
5. (a) Whnt is the basic design principie for Cache? Discuss with example. 1
various types of localities ... 10 0
(b) Develop the Gamma (y}-binomial-model of bypassed
(b) What do you mean by Cache-niapping ? Explain the set
vector memory behaviour. Deri ve the Yopt (no
a~sociative mapping scheme for cache with the help of a
contention). 10
. iiagram. 10
8. (a) Describe the Cache coherence problem. Discuss the
6. Assume ,: CBWA cache has a miss rate of 0.03 misses per
writing mechanism for Cache to make available the latest
reference with a dirty line ratio of 0.5 . This Cache is used copy of data in Cache. 10 (b) Discuss various mechanisms for
with a pro ::essor that makes a referenc ,:; every 40 ns. (mean), sharing memory
assume the Cache is configured with: among multiple processes. 10
Cache line size = 16B
Phys· cal word size = 4 B
the meme ry is configured as
T = 120 llS,T =l00ns,Tbu =40ns,m=2.
a c s
'
(a) Assu:ne the cache writes a dirty line before reading lines !

(unbuffered) and that an entire line must be

transferred to the processor before it resumes ...............................................' ...• ", .. "'.,,~'""" , ..••• """~;_.j~;.;4~$".;,;,
..
.• .• •. " _.', ..••.• '~ ~- ••••• ",'- "'> ~ .. ~ -~~ ~.,:.r:~' .,".'"-,...,, ~';"""";$."ii. ••.. ~ ••.• Jtilj-~ ••.•. '1>' ""'v'-"'- ~
lit . "'Ln-. ._.!.._~.~
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