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Under the guidance of: Dr. Syamal Kumar Dana Scientist F & Head Instrumentation Division Indian Institute of Chemical Biology Jadavpur, Kolkata.
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Phase Locked Loop is a circuit that synchronizes an output signal (generated by an oscillator) with a reference or input signal in frequency.

In the synchronized or locked state the phase error between the

oscillator output signal and the reference signal is either zero or constant.

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1.Linear PLL
A linear PLL has all analog components.

2.Digital PLL
Digital PLL has digital as well as analog components such as the charge pump.

3.All Digital PLL

All Digital PLL (ADPLL) has all digital components.

4.Software PLL
Algorithm based PLL where functions of a PLL are performed by a computer based program written using high level languages like C/C++ which finally are programmed into microcontrollers.

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x(t) Phase Detector Loop Filter Frequency Divider
Voltage Controlled Oscillator

y(t)

* There are 4 components of a PLL: 1.Phase Detector 2.Loop Filter 3.Voltage Controlled Oscillator 4.Frequency Divider
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Compulsory Components

Optional Component
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ANALOG PLL

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* Inputs of the Phase Detector:
1. Reference input 2. Feedback from VCO

* The PD output controls the VCO such that

the phase difference between the two inputs is held constant, making it a negative feedback system.

* The Phase Detector produces the output

signal ud(t) proportional to the phase error. Ud(t) = Kd.e Where, Kd = gain of the PD.
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Counter u1 u2 J K Q Enable N Clock High Frequency Clock Reset

u1 u2 Q N

t t t t

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*It is usually a low pass filter. *Functions of Loop Filter:

1.Its primary function is to find the loop dynamics. 2.The second function is limiting the amount of reference frequency energy (ripple) appearing at the PD output that is then applied to the VCO control input i.e. it helps discard the ac component.

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Modulus Control (K) K Clock UP/ DN UP Counter Down Counter Carry Borrow

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*All PLLs employ an oscillator
element with variable capability.

*The VCO operates at a frequency

determined by output signal of the loop filter.

2(t) = 0 + K0uf(t) of 0 = center angular frequency the VCO K0 = VCO Gain (rad.s-1V-1)
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ID CLK Carry Borrow CP INC DEC OUT ID OUT = (ID CLK) . (TOGGLE FF)

* ID Counter is sensitive to the positive edges of the clock. * ID Clock frequency is 2Nf0 where N is the modulus control for
the Modulo N counter.

* A Toggle FF signal is generated according to the four different

conditions encountered.
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1.No BORROW or CARRY pulses
ID CLK TOGGLE ID OUT

ID CLK

2.CARRY input applied when the toggle - FF is in the low state

TOGGLE CARRY ID OUT

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3. CARRY input applied when the toggle-FF is in the high state

ID CLK TOGGLE CARRY ID OUT

ID CLK

4. Application of a BORROW pulse

TOGGLE BORROW ID OUT

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* Parameters of the ADPLL:
o K Modulus control of the K counter loop filter o M The frequency of the clock signal of K counter is M times the center frequency of
the ADPLL. o N Modulus control of the modulo N counter and the IDCLK frequency 2Nf0. o For minimum phase jitter M=2K

o N > N(practical) = * Values of K, N and M considered for an ADPLL with center frequency of 10MHz are
f0 = 10MHz K=8 N=8 M = 16

* Hold Range of the ADPLL

fH = f0 = 1.25MHz

* Lock-in Time of the ADPLL

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= 0.4 usec
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* Roland E. Best, Phase-Locked Loops Design,

Simulation and Applications 5th ed., McGraw Hill, 2003.

* H R Pota, Phase-Locked Loop, June 6, 2005

(Technical Brief Lecture Notes).

* Martin Kumm, Harald Klingbeil, and Peter Zipf,

Member, An FPGA-Based Linear All-Digital PhaseLocked Loop, IEEE Trans. on Circuits Syst-I, Regular paper, vol. 57, no. 9, Sept. 2010. pp.2487-2497.

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