First Encounter: Design Flow

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Design Flow
The qualiIied libraries are tested in the normal Cadence First Encounter Ilow. For details oI the
Cadence Place&Route Ilow with Encounter please reIer to the Cadence documentation. Here
some special Iunctions are explained that can or have to used in the design Ilow using
austriamicrosystems Hit-Kit libraries:
Step
Helpful TCL
Functions
Database Setup
amsDbSetup
amsGlobalConnect
Floorplan

amsUserGrid

Placement
amsHVringBlk

Clock Tree Synthesis



Routing
amsRoute
amsFillcore
amsFillperi
Parasitic Extraction



Export SDF, GDSII
amsWrite
amsWriteSDF4View
Final Layout in
Virtuoso

To be able to run the TCL Iunctions the amsSetup.tcl script, that was created by amsencounter,
has to sourced within encounter:
encounter~ source amsSetup.tcl
Typing amsHelp or amsTAB~ show the available ams-Iunctions. In the Iollowing
documentation it is assumed that the environment was set up with the amsencounter script and
that the amsSetup.tcl script is loaded.
The Iollowing examples apply to the 0.18m process H18A4. You have to replace the library
names and process names iI you use another process. Special settings necessary Ior some
processes are given as well.

Database Setup
II the conIiguration Iile includes all necessary data the database can be loaded by executing
encounter~ amsDbSetup
This command will load the conIiguration Iile and read in all the libraries and verilog netlist. II
you have to add some inIormation into the conIiguration you can also load the conIiguration Iile
using
Design -> Design Import ...
and modiIy the entries.
O LEFs: See table
O Timing Libs (.lib): See table
O Power/Ground Net names: See table below
O Parasitic Extraction technology Iiles
Power & Ground Net Names
O Names written in italic style are peripheral ring nets and are not used iI you are just
routing a digital standard cell block without periphery cells.
Libraries Power Nets Ground Nets
Core Periphery Core Periphery Core Periphery
CORELIBHV IOLIBHJ4/5/6AM vdd!
vdd5vl' vdd5vr'
vdd5vo' trig1v8'
trig5v' por5vr'
gnd!
gnd5vl'
gnd5vr'
gnd5vo'
subc5v'
CORELIB IOLIB4/5/6AM vdd! vdd5vl' vdd5vr' gnd! gnd5vl'
vdd5vo' trig1v8'
trig5v' por5vr'
gnd5vr'
gnd5vo'
subc5v'
CORELIBHVT IOLIB4/5/6AM vdd!
vdd5vl' vdd5vr'
vdd5vo' trig1v8'
trig5v' por5vr'
gnd!
gnd5vl'
gnd5vr'
gnd5vo'
subc5v'
The por5vr! bus is a wiring Ior a power-on-reset net that resets all the logic in the IOPADs.
There is a special cell called PORGEN5VHV that creates that power-on-reset signal. This cell
PORGEN5V_HV cell has to be placed in the periphery ring, otherwise the IOPADs would
not work.
Corner cells have to be added iI periphery cells are also in the design. They can be added with
an io-Placement Iile called 'corners.io' that is created by the amsencounter script:
Design -> Load -> I/O File...
The Global Power Connections can be set with the command
encounter~ amsGlobalConnect core[both
Option core is setting only the power supplies Ior the core region, whereas option both is setting
the connection Ior the peripheral supply rings also.

Floorplan
The settings Ior the diIIerent processes can be seen in the Iollowing table.
Core cell row settings
Library SiteName Row Height X-Offset Y-Offset Abut Flip
CORELIB_HV ams018hvSite 5.04m HalIGrid OnGrid Yes Yes
CORELIB ams018Site 5.04m HalIGrid OnGrid Yes Yes
CORELIB_HVT ams018Site 5.04m HalIGrid OnGrid Yes Yes
Periphery cell settings
AIter having placed the periphery cells it is important to snap them to a 0.1m grid. Executing
the Iunction
encounter~ amsUserGrid
sets a user grid to 0.01m and snaps the periphery cells to that grid. Otherwise you will get gaps
when placing the peripery-spacer cells and this will give design rule errors.

Placement
When the H18 CORELIBHV cells are used the core region has to be surrounded by a HV-Ring
(PWELL isolation Ior DN in Substrate NW Ring inside DN). This will be done in Virtuoso
aIter the Place&Route is Iinished. Special Hit-Kit Iunctions are available in Virtuoso to create
these rings. As these rings include Metal1 wires it is necessary to create blockages Ior metal1
during the place&route. These blockages can be created using the TCL command:
encounter~amsHVringBlk row[corebox width] offset]
o row.......creates blockages around core rows (Ior non rectangular core regions)
o corebox...creates blockages around the core bounding box
o width.....width oI the blockage (deIault 10m)
o oIIset....oIIset Irom row or core bounding box (deIault 0)
The Iollowing pictures show the blockage ring in encounter and the already created HV-ring in
Virtuoso.

II the row option is used in the amsHVringBlk command a perl script is invoked to create a DEF
Iile with the blockages. ThereIore perl has to be installed.
II the blockages Ior the HV-Ring are created the Iollowpin routing cannot be extended to the leIt
and right supply rings. ThereIore stripes need to be routed to connect the standard cells to the
supply rings.
Clock Tree Synthesis
When you generate a Clock SpeciIication Iile you will get a list oI inverters, buIIers and delay
cells. You can choose all or just a set oI these cells to be used Ior building the clock tree. There
are also special clock buIIers and inverters (CLKBUx and CLKINx). These cells have a better
symmetry between rising and Ialling delays.
Library Cell-Type Cell-Names
CORELIBHV
Inverters:
INVXLHV INVX1HV INVX2HV INVX3HV INVX4HV
INVX6HV INVX8HV INVX12HV INVX16HV
INVX24HV INVX32HV
Clock-
Inverters:
CLKINXLHV CLKINVX1HV CLKINVX2HV
CLKINVX3HV CLKINVX4HV CLKINVX6HV
CLKINVX8HV CLKINVX12HV CLKINVX16HV
CLKINVX24HV INVX32HV
BuIIers:
BUFX2HV BUFX3HV BUFX4HV BUFX6HV BUFX8HV
BUFX12HV BUFX16HV BUFX24HV BUFX32HV
Clock-
BuIIers:
CLKBUFX2HV CLKBUFX3HV CLKBUFX4HV
CLKBUFX6HV CLKBUFX8HV CLKBUFX12HV
CLKBUFX16HV CLKBUFX24HV CLKBUFX32HV
Delay
Cells:
DLY1X1HV DLY2X1HV DLY3X1HV DLY4X1HV
CORELIB
Inverters:
INVXL INVX1 INVX2 INVX3 INVX4 INVX6 INVX8 INVX12
INVX16 INVX24 INVX32
Clock-
Inverters:
CLKINXL CLKINVX1 CLKINVX2 CLKINVX3 CLKINVX4
CLKINVX6 CLKINVX8 CLKINVX12 CLKINVX16
CLKINVX24 INVX32
BuIIers:
BUFX2 BUFX3 BUFX4 BUFX6 BUFX8 BUFX12 BUFX16
BUFX24 BUFX32
Clock-
BuIIers:
CLKBUFX2 CLKBUFX3 CLKBUFX4 CLKBUFX6
CLKBUFX8 CLKBUFX12 CLKBUFX16 CLKBUFX24
CLKBUFX32
Delay
Cells:
DLY1X1 DLY2X1 DLY3X1 DLY4X1
CORELIBHVT Inverters:
INVXLHVT INVX1HVT INVX2HVT INVX3HVT
INVX4HVT INVX6HVT INVX8HVT INVX12HVT
INVX16HVT INVX24HVT INVX32HVT
Clock-
Inverters:
CLKINXLHVT CLKINVX1HVT CLKINVX2HVT
CLKINVX3HVT CLKINVX4HVT CLKINVX6HVT
CLKINVX8HVT CLKINVX12HVT CLKINVX16HVT
CLKINVX24HVT INVX32HVT
BuIIers:
BUFX2HVT BUFX3HVT BUFX4HVT BUFX6HVT
BUFX8HVT BUFX12HVT BUFX16HVT BUFX24HVT
BUFX32HVT
Clock-
BuIIers:
CLKBUFX2HVT CLKBUFX3HVT CLKBUFX4HVT
CLKBUFX6HVT CLKBUFX8HVT CLKBUFX12HVT
CLKBUFX16HVT CLKBUFX24HVT CLKBUFX32HVT
Delay
Cells:
DLY1X1HVT DLY2X1HVT DLY3X1HVT DLY4X1HVT
The number in the cell name characterises the drive strenght oI the cell. For example
INVX16HV has 16 times the drive strength oI INVX1HV.

Routing
BeIore the routing is started the gaps between periphery cells and core cells should be Iilled with
special cells.
Placement of Periphery Filler Cells
The space between the periphery cells has to be Iilled with special cells that will also connect the
power supply lines. A number oI Iiller cells are available with diIIerent widths. You have to start
the procedure using the largest one going down to the smallest.
There is no menu command that can be used to Iill the gaps between the periphery cells. It can
just be done Irom the command line either by using the ams-Iunction:
encounter~ amsFillperi
or by executing the encounter command:
addIoFiller -cell PERI_SPACER_100_HV -prefix pfill
When using the addIoFiller command repeat this step with the diIIerent spacer cells. The number
in the cell names represents the width oI the cell. Start with the largest one going down to the
smallest. The amsFillperi Iunction is doing that automatically.
To completely Iill the gaps the IO-Cells need to be placed on a 0.01m grid. This can be done by
speciIying a User Grid and snapping the IOs to that grid (amsUserGrid):
setPreference ConstraintUserXGrid 0.01
setPreference ConstraintUserXJffset 0.01
setPreference ConstraintUserYGrid 0.01
setPreference ConstraintUserYJffset 0.01

snapFPlanIJ -usergrid

Library Cell Name Width x (m)
IOLIBHV4/5/6AM PERISPACERxHV
100, 50, 20, 10, 5, 2, 1, 0p5, 0p1,
0p05, 0p01
IOLIB4/5/6AM PERISPACERxP
100, 50, 20, 10, 5, 2, 1, 0p5, 0p1,
0p05, 0p01
Do not use just the smallest Iiller cell, because this will result in errors in your design and
increase your database.
Placement of Core Filler Cells
The gaps between standard cells should be Iilled with Iiller cells to avoid design rule violations.
They can be placed beIore or aIter the routing.
Place -~ Filler -~ Add Filler...
o Cell Name(s): FILLCAPX32HV FILLCAPX16HV FILLCAPX8HV
FILLCAPX4HV FILLCELLX32HV ... (see table below)
o PreIix: irgendwos
o No Area is needed but can be speciIied
To reduce the number oI Iiller cells several Iiller cells with diIIerent widths can be used in the
0.18m processes. The number x in the cell name deIines the width oI the cell in multiples oI the
minimal pitch.
Two types oI Iiller cells exist:
O with coupling capacitances (need to be in the Iinal netlist Ior LVS)
O without coupling capacitances
Library
Cell with coupling caps Cell without coupling caps
Cellname Width y Cellname Width y
CORELIBHV FILLCAPXyHV 32,16,8,4 FILLCELLXyHV 32,16,8,4,2,1
CORELIB FILLCAPXy 32,16,8,4 FILLCELLXy 32,16,8,4,2,1
CORELIBHVT FILLCAPXyHVT 32,16,8,4 FILLCELLXyHVT 32,16,8,4,2,1
A TCL Iile 'Iillcore.tcl' is prepared by 'amsencounter', that includes the commands to place the
Iiller cells. The Iunction
encounter~ amsFillcore
loads that TCL Iile and executes it. The Iunctions uses Iill cells with coupling capacitances Iirst
then places Iiller cells without coupling caps. Filler cells with coupling caps reduce the routing
space a little bit and thereIore they have to be placed beIore routing is started. Then only cells
with coupling caps will be inserted.
II you run the amsFillcore command aIter the routing Iiller cells with coupling caps will only be
placed where they produce no violations, and the rest will be Iilled with Iillers without coupling
caps.
The FILLCAPX cells include transistors that are recognized by the LVS tools. ThereIore it is
necessary to insert the correct number oI FILLCAP cells into the schematic. A Skill procedure
can be Iound in the Cadence CIW under:
Hit-Kit Utilities --~ Layout Utilities -~ Create FILLCAP schematic
Routing
Routing oI signal nets can be done with WROUTE or NanoRoute. In the processes H18A4/5/6
the top metal is a thick metal. It can be used Ior Power Routing but should not be used Ior signal
routing. ThereIore the top metal layer has to be set to Metal 3, 4 or 5, not using the top metal.
The command
setMaxRouteLayer 3[4[5
sets the Top Routing Layer Ior Trial Route, NanoRoute, the placement program, and clock tree
synthesis (CTS). It does not set it Ior WROUTE. To restrict wroute the top layer has to be
speciIied in the Advanced - Routing Layer Limits Option.
Top Metal: M3[M4[M5
or by using the ams Iunction
encounter~ amsRoute wroute

Parasitic Extraction
Parasitic extraction is either done by Encounter using the capTables or by QRC. The techIiles
and captables can be Iound under:
Proce
ss
Encounter Cap-Table QRC Techfile
H18A
4
$AMSDIR/artist/HKH18/LEF/h18a4/h18a
4.capTable
$AMSDIR/assura/h18a4/h18a4/QRC/qr
cTechFile
H18A
5
$AMSDIR/artist/HKH18/LEF/h18a5/h18a
5.capTable
$AMSDIR/assura/h18a5/h18a5/QRC/qr
cTechFile
H18A
6
$AMSDIR/artist/HKH18/LEF/h18a6/h18a
6.capTable
$AMSDIR/assura/h18a6/h18a6/QRC/qr
cTechFile

Write GDSII and SDF
SDF is written Ior the active analysis views in multi mode timing. To write SDF the ams
Iunction can be used:
encounter~ amsWriteSDF4View <viewList>
It writes SDF Iiles Ior all the analysis views speciIied in the list and stores them in a directory
called SDF. Be aware that SDF can only be generated Ior views that are active.
The mapping Iile gds2.map has to be used Ior writing out GDSII. By using the ams Iunction
encounter~ amsWrite <postfix>
the encounter database is saved, a SPEF Iile and a GDSII Iile is written. The Iiles are named with
O SDF/topcell-name~postIix~.speI: Encounter Parasitic Extraction File
O SDF/topcell-name~postIix~qrc.speI: Fire&Ice Parasitic Extraction File
O topcell-name~postIix~.gds: GDSII File
O DB/topcell-name~postIix~.enc: Encounter Database

Final Layout in Virtuoso
From First Encounter To DFII
When you have Iinished routing in First Encounter you have to write a GDSII Iile.
This Iile you have to import into CADENCE:
File -> Import -> Stream...
o SpeciIy GDSII File Name
o Library Name you want to write your layout to (library must already exist)
o Under Options set additionally to the deIault settings:
Retain ReIerence Library (No Merge): yes
Do Not Overwrite Existing Cell: yes
o Units: Thousands
For all the cells you are using in your design, layout views should exist in one oI the Cadence
libraries that are deIined in your cds.lib Iile. You will get a layout view oI your top cell that will
use layout views oI all standard cells or macro blocks.
Create HV-Ring
II Iloating logic (Irom CORELIBHV) is used in the design a HV-Ring has to be drawn around
the core region. This is done in the Layout Editor Virtuoso. In Encounter you should have
prevented Metal1 routing around the core region by placing blockages (amsHVringBlk). The
HV-Ring can now be placed in this space.
To create the rings a skill Iunction Irom the Virtuoso menu can be used:
Hit-Kit Utilities -> Guard Ring Generator
This generator needs a DN shape. Its outline is used as guidance Ior the ring. II you look at the
complete layout oI the design you see the DN shapes oI all the standard cells Irom
CORELIBHV. To create the HV-Rings do the Iollowing:
1. Create a single DN shape that includes all the DN shapes oI the standard cells.
2. Select that DN shape and open the Guard Ring Generator Dialog Box
3. Select Guard Ring Type: NW Ring inside DN - Click on 'Generate Guard Ring'
4. Select Guard Ring Type: PWELL Isolation Ior DN in Substrate - Click on 'Generate
Guard Ring'
This will create the 2 HV-Rings around the core area. These 2 rings also need to be connected.
O Connect the inner ring (NW Ring) to the core power (vdd!)
O Connect the outer ring (PWELL isolation) to the substrate (subc! net)
Core Supply ESD Trigger Net
For ESD protection oI the core logic a separate trigger signal is used. Whereas the trigger signal
Ior the periphery (trig5v!) is routed internally in the periphery cells the trig1v8! net is a
connection between cells VDDPAD5VL_HV and RAILCLAMP5VL_HV that has to be
routed in the core region. II it was not done in Encounter this connection has to be done beIore
running DRC and LVS.
See example layout in the EXAMPLES library in the H18 Hit-Kit.
Adding Labels to the Layout
Some global supplies need to be labeled in the layout to get a clean DRC and LVS.
O Add labels to your power supplies: Ior example vdd!, vdd5!, gnd!
O Add a 'sub!' label on layout SXCUT-label somewhere on the layout
O Add 'subc!' label on the substrate metal routing
Additionally iI periphery cells are used:
O Add trig1v8! label on the correct metal-label layer on the trig1v8! net
O Add trig5v! label (on layer MT-label) on the trig5v! bus (most inner ring) in the
periphery (best place is a corner cell iI available)
O Add a por5vr! label (on layer MT-label) on the por5vr! bus in the periphery (best place is
a corner cell iI available)
Modifications on the top schematic for a clean LVS
To get a clean LVS some modiIications have to be done on the top schematic. As the transistors
in the FILLCAP cells are not ignored any more the exact number oI FILLCAP cells need to
placed in the schematic. A Skill Iunction reading a DEF File (exported Irom Encounter) can help
to create a schematic Ior these FILLCAP cells. Invoke Irom the CIW:
Hit-Kit Utilities -> Layout Utilities -> Create FILLCAP Schematic

You can create a schematic or calculate the total decoupling capacitance only. II you want to
create a schematic you have to speciIy the library, the cell and the view name. As File Name you
can either speciIy a DEF Iile (coming Irom Encounter) or a simple ascii Iile with a list oI
FILLCAP cells and their amount used in the design, Ior example:
FILLCAPX8_HV 23
FILLCAPX16_HV 7
FILLCAPX4_HV 267
FILLCAPX8_HV 117
A schematic will be created with the correct number oI FILLCAP cells and also a symbol iI you
selected that option. Open the created schematic view and check and save it. Then place the
symbol oI this cell on the top level oI your schematic.
(Move the cursor on the picture to see Iull Irame)
sub! - subc! Nets
For a clean LVS you also have to add a subcx device on the top level oI the schematic when you
are using Iloating logic (see picture above). Place this instance Irom:
Library: cmhv7sI
Cell: subcx
View: symbol
Connect the top pin to the metal substrate wiring (subc!) and the bottom pin to the substrate
(sub!).
EXAMPLE Layout
In the Hit-Kit you can Iind an EXAMPLE library that includes a cell called digiexample that
shows a digital layout:
$AMSDIR/artist/HKH18/EXAMPLES
On the layout and schematic views oI this cell you can see all the modiIications that were
described above.

See Also
O Known Problems & Solutions