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FEATURES
Analog I/O Multichannel, 12-bit, 1 MSPS ADC Up to 16 ADC channels1 Fully differential and single-ended modes 0 to VREF analog input range 12-bit voltage output DACs Up to 4 DAC outputs available1 On-chip voltage reference On-chip temperature sensor (3C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (3%) External watch crystal External clock source up to 44 MHz 41.78 MHz PLL with programmable divider Memory 62 kB flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability
APPLICATIONS
Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking
DAC1
ADuC7026
DAC2
DAC3
XCLKI XCLKO
ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 2k 32 SRAM 31k 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved.
04955-001
POR
JTAG
Transfer Function....................................................................... 37 Typical Operation....................................................................... 38 MMRs Interface.......................................................................... 38 Converter Operation.................................................................. 40 Driving the Analog Inputs ........................................................ 42 Calibration................................................................................... 42 Temperature Sensor ................................................................... 42 Band gap Reference.................................................................... 42 Nonvolatile Flash/EE Memory ..................................................... 43 Programming.............................................................................. 43 Security ........................................................................................ 44 Flash/EE Control Interface ....................................................... 44 Execution Time from SRAM and Flash/EE............................ 46 Reset and Remap ........................................................................ 46 Other Analog Peripherals.............................................................. 48 DAC.............................................................................................. 48 Power Supply Monitor ............................................................... 49 Comparator ................................................................................. 50 Oscillator and PLLPower Control........................................ 52 Digital Peripherals.......................................................................... 54 Three-Phase PWM..................................................................... 54 General-Purpose Input/Output................................................ 61 Serial Port Mux........................................................................... 63 UART Serial Interface................................................................ 63 Serial Peripheral Interface ......................................................... 66 I2C Compatible Interfaces ......................................................... 68 Programmable Logic Array (PLA)........................................... 72 Processor Reference Peripherals................................................... 75 Interrupt System ......................................................................... 75 Timers .......................................................................................... 76 External Memory Interfacing ................................................... 80
Rev. A | Page 2 of 93
ADuC7019/20/21/22/24/25/26/27
PC-Based Tools ...........................................................................87 In-Circuit Serial Downloader....................................................87 Outline Dimensions........................................................................88 Ordering Guide ...........................................................................90
REVISION HISTORY
1/06Rev. 0 to Rev. A Changes to Table 1 ............................................................................6 Added the Flash/EE Memory Reliability Section .......................43 Changes to Table 30 ........................................................................52 Changes to Serial Peripheral Interface .........................................66 10/05Revision 0: Initial Version
Rev. A | Page 3 of 93
The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Eight kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART or I2C serial interface ports, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting this MicroConverter family. The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of 40C to +125C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are available in a variety of memory models and packages.
Rev. A | Page 4 of 93
ADuC7019/20/21/22/24/25/26/27
DETAILED BLOCK DIAGRAM
DACGND
70
DACV DD
75
72
71
67
73
74
53
26
25
54
28
27
37
ADC0 77 ADC1 78 ADC2/CMP0 79 ADC3/CMP1 80 ADC4 1 ADC5 2 ADC6 3 ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADC11 76 ADCNEG 9 TEMP SENSOR MUX 12-BIT SAR ADC 1MSPS
ADuC7026*
ADC CONTROL DAC CONTROL
12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC
BUF
DACREF
69
AGND
AGND
DGND
IOVDD
IOVDD
AVDD
AVDD
LVDD
RST
10 DAC0*/ADC12
BUF
11 DAC1*/ADC13
BUF
12 DAC2*/ADC14
BUF
13 DAC3*/ADC15
29 P3.0/AD0/PWM0H/PLAI[8]
62KBYTES FLASH/EE (31k 16 BITS) ARM7TDMI MCU CORE WAKEUP/ RTC TIMER POWER SUPPLY MONITOR OSC THREEPHASE PWM
DAC BM/P0.0/CMPOUT/PLAI[7]/MS2 20
MUX
JTAG EMULATOR
PLL
44 XCLKO 45 XCLKI
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
P4.6/AD14/PLAO[14] 18 P4.7/AD15/PLAO[15] 19
POR
21 49 50 17 33
INTERRUPT CONTROLLER
35 36 48 24 16
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P0.6/T1/MRST/PLAO[3]/AE
P1.0/T1/SPM0/PLAI[0]
P2.1/WS/PWM0H/PLAO[6]
P2.2/RS/PWM0L/PLAO[7]
TMS
P2.4/PWM0H/MS0
P2.6/PWM1H/MS2
P1.7/SPM7/PLAO[0]
P1.1/SPM1/PLAI[1]
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.6/SPM6/PLAI[6]
P4.0/AD8/PLAO[8]
P4.1/AD9/PLAO[9]
P2.0/SPM9/PLAO[5]/CONVSTART
P0.3/TRST/A16/ADC BUSY
P4.2/AD10/PLAO[10]
P4.3/AD11/PLAO[11]
P4.4/AD12/PLAO[12]
P4.5/AD13/PLAO[13]
Figure 2.
Rev. A | Page 5 of 93
04955-002
P0.2/PWM2L/BHE
P0.1/PWM2H/BLE
P2.5/PWM0L/MS1
P2.7/PWM1L/MS3
TDI
TDO
TCK
P2.3/AE
ADuC7019/20/21/22/24/25/26/27 SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = 40C to 125C, unless otherwise noted. Table 1.
Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy1, 2 Resolution Integral Nonlinearity Differential Nonlinearity3, 4 DC Code Distribution ENDPOINT ERRORS5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT7 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS DC ACCURACY8 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error9 Gain Error Mismatch Min Typ 5 12 0.6 1.0 0.5 +0.7/0.6 1 1 1 2 1 69 78 75 80 1.5 +1/0.9 Max Unit s Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB dB dB dB dB FIN = 10 kHz sine wave, fSAMPLE = 1 MSPS Includes distortion and noise components Test Conditions/Comments Eight acquisition clocks and fADC/2
2.5 V internal reference 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input is a dc voltage
2 5
1 20 2.5
V V A pF V mV ppm/C dB ms V k RL = 5 k, CL = 100 pF
5 40 75 70 1 0.625 65 AVDD
TA = 25C
12 2 1 15 1 0.1
Rev. A | Page 6 of 93
ADuC7019/20/21/22/24/25/26/27
Test Conditions/Comments DACREF range: DACGND to DACVDD
s nV-sec mV A V pF mV s
Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register 100 mV overdrive and configured for 0.5 s response time (CMPRES = 11)
780 1.3 3 2.79 3.07 2.5 2.36 50 0 10,000 20 0.2 40 80 10 1 60 120 512
mV mV/C C V V % V s sec cycles years A A A pF V V V V All digital outputs excluding XCLKI and XCLKO ISOURCE = 1.6 mA ISINK = 1.6 mA Two selectable trip points Of the selected nominal trip point voltage
TJ = 85C All digital inputs excluding XCLKI and XCLKO VIH = VDD or VIH = 5 V VIL = 0 V; except TDI on ADuC7019/20/21/22/24/25 VIL = 0 V; TDI, on ADuC7019/20/21/22/24/25 All logic inputs excluding XCLKI and XCLKO
Input Capacitance LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage12 CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance
1.1 1.7 20 20
V V pF pF
Rev. A | Page 7 of 93
ADuC7019/20/21/22/24/25/26/27
Parameter INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS 13, 14 Power Supply Voltage Range AVDD AGND and IOVDD IOGND Analog Power Supply Currents AVDD Current DACVDD Current15 Digital Power Supply Current IOVDD Current in Normal Mode Min Typ 32.768 Max 3 326 41.78 0.05 0.05 130 24 3.06 1.58 1.7 12 2.5 44 41.78 Unit kHz % kHz MHz MHz MHz ms ns s ms ms ns ns
3.6
V A A A ADC in idle mode; all parts except ADuC7019 ADC in idle mode; ADuC7019 only
25
IOVDD Current in Pause Mode IOVDD Current in Sleep Mode Additional Power Supply Currents ADC DAC
1 2 3
10 15 45 30 400 1000
mA mA mA mA A A mA mA A
Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 85C TA = 125C @ 1 MSPS @ 62.5 kSPS per DAC
All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. Measured using the factory set default values in ADCOF and ADCGN. 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory set default values in ADCOF and ADCGN using an external AD845 op amp as an input buffer stage as shown in Figure 47. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 8 DAC linearity is calculated using a reduced code range of 100 to 3995. 9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 10 Endurance is qualified as per JEDEC Standard 22 method A117 and measured at 40C, +25C, +85C, and +125C. 11 Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22 method A117. Retention lifetime derates with junction temperature. 12 Test carried out with a maximum of eight I/O set to a low output level. 13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V supply, Sleep Mode: 3.6 V supply. 14 IOVDD power supply current decreases typically by 2 mA during a flash/EE erase cycle. 15 On the ADuC7019/20/21/22, this current must be added to AVDD current.
Rev. A | Page 8 of 93
ADuC7019/20/21/22/24/25/26/27
Max 4 8
Unit ns ns
CLK (XMxPAR[14:12] + 1) x CLK CLK + (!XMxPAR[10]) x CLK (!XMxPAR[8]) x CLK CLK + (!XMxPAR[10] + !XMxPAR[8]) x CLK 8 (XMxPAR[7:4] + 1) x CLK 0 (!XMxPAR[8]) x CLK CLK (!XMxPAR[8] + 1) x CLK 4 ns ns 12 ns
CLK CLK TMS_AFTER_CLKH MS TAE_H_AFTER_MS AE TWR TAE WR THOLD_DATA_AFTER_WR_H RD THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TADDR_AFTER_CLKH A/D[15:0] FFFF 9ABC TDATA_AFTER_WR_L 5678 TBEN_AFTER_AE_L BEN0 BEN1 A16
04955-052
TWR_L_AFTER_AE_L
TRELEASE_MS_AFTER_WR_H TWR_H_AFTER_CLKH
9ABE
1234
Rev. A | Page 9 of 93
ADuC7019/20/21/22/24/25/26/27
Table 3. External Memory Read Cycle
Parameter CLK TMS_AFTER_CLKH TADDR_AFTER_ CLKH TAE_H_AFTER_MS TAE THOLD_ADDR_AFTER_AE_L TRD_L_AFTER_AE_L TDATA_AFTER_RD_L TRD TRD_H_AFTER_CLKH THOLD_DATA_AFTER_RD_H TRELEASE_MS_AFTER_RD_H Min 4 4 CLK (XMxPAR[14:12] + 1) x CLK CLK + (!XMxPAR[10]) x CLK CLK + (!XMxPAR[10] + !XMxPAR[9]) x CLK 8 (XMxPAR[3:0] + 1) x CLK 0 (!XMxPAR[9]) x CLK CLK Typ UCLK
12 4
ns ns ns
CLK ECLK TMS_AFTER_CLKH GP0 TAE_H_AFTER_MS TAE AE WR TRD RD THOLD_DATA_AFTER_RD_H TDATA_AFTER_RD_L TADDR_AFTER_CLKH A/D[15:0] BEN1 BEN0 A16
04955-053
FFFF
234B
Rev. A | Page 10 of 93
ADuC7019/20/21/22/24/25/26/27
Slave Max
Description SCLOCK low pulse width1 SCLOCK high pulse width1 Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both CLOCK and SDATA Fall time for both CLOCK and SDATA Pulse width of spike suppressed
Master Typ 1360 1140 251350 740 400 12.51350 400 200 20
Unit ns ns ns ns ns ns
300 100 50
ns ns ns
tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD.
tBUF
SDATA (I/O)
tSUP tR
MSB LSB ACK MSB
tDHD tH
27 8
tDSU tRSU
9
tF tDHD tR
1 S(R) REPEATED START
Rev. A | Page 11 of 93
04955-054
tL
tSUP
tF
ADuC7019/20/21/22/24/25/26/27
Table 5. SPI Master Mode Timing (PHASE Mode = 1)
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
1 2
Description SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
tSH
tSL
tSR
tSF
tDAV
MOSI MSB
tDF
tDR
BITS 61 LSB
MISO
MSB IN
BITS 61
LSB IN
04955-055
tDSU tDHD
Rev. A | Page 12 of 93
ADuC7019/20/21/22/24/25/26/27
Min Typ (SPIDIV + 1) tHCLK (SPIDIV + 1) tHCLK Max Unit ns ns ns ns ns ns ns ns ns ns
Description SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK (POLARITY = 1)
tDOSU
MOSI MSB
MISO
MSB IN
BITS 61
LSB IN
tDHD
Rev. A | Page 13 of 93
04955-056
tDSU
ADuC7019/20/21/22/24/25/26/27
Table 7. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
1 2
Description CS to SCLOCK edge1 SCLOCK low pulse width2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge
(SPIDIV + 1) tHCLK (SPIDIV + 1) tHCLK 25 1 tUCLK 2 tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
tSL
tSR
tSF
SCLOCK (POLARITY = 1)
tDAV
MISO MSB
tDF
tDR
BITS 61 LSB
MOSI
MSB IN
BITS 61
LSB IN
04955-057
tDSU tDHD
Rev. A | Page 14 of 93
ADuC7019/20/21/22/24/25/26/27
Min 2 tHCLK + 2 tUCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
Description CS to SCLOCK edge1 SCLOCK low pulse width2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge
(SPIDIV + 1) tHCLK (SPIDIV + 1) tHCLK 25 1 tUCLK 2 tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 25
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
SCLOCK (POLARITY = 1)
tDOCS tDF
MISO MSB
tDAV tDR
BITS 61 LSB
MOSI
MSB IN
BITS 61
LSB IN
04955-058
tDSU
tDHD
Rev. A | Page 15 of 93
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 16 of 93
ADuC7019/20/21/22/24/25/26/27
40 39 38 37 36 35 34 33 32 31
ADC3/CMP1 1 ADC4 2 GNDREF 3 4 DAC0/ADC12 5 DAC1/ADC13 6 DAC2/ADC14 7 DAC3/ADC15 TMS 8 9 TDI BM/P0.0/CMPOUT/PLAI[7] 10
PIN 1 INDICATOR
ADuC7019/ ADuC7020
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2]
ADC4 1 ADC5 2 ADC6 3 ADC7 4 GNDREF 5 6 DAC0/ADC12 7 DAC1/ADC13 TMS 8 9 TDI BM/P0.0/CMPOUT/PLAI[7] 10
40 39 38 37 36 35 34 33 32 31
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2]
PIN 1 INDICATOR
ADuC7021
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2]
11 12 13 14 15 16 17 18 19 20
P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1]
04955-064
P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1]
11 12 13 14 15 16 17 18 19 20
ADC5 1 ADC6 2 ADC7 3 ADC8 4 ADC9 5 GNDREF 6 TMS 7 8 TDI BM/P0.0/CMPOUT/PLAI[7] 9 P0.6/T1/MRST/PLAO[3] 10
40 39 38 37 36 35 34 33 32 31
ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
PIN 1 INDICATOR
ADuC7022
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
11 12 13 14 15 16 17 18 19 20
Rev. A | Page 17 of 93
04955-066
04955-065
ADuC7019/20/21/22/24/25/26/27
Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No. 7019/7020 7021 38 37 39 38 40 39 1 40 7022 36 37 38 39 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
2 3 4 5 6 7
1 2 3 4 5 6 7
40 1 2 3 4 5 6
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15
Description Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/ Comparator Negative Input. Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor needs to be connected between this pin and AGND/Single-Ended or Differential Analog Input 15. Test Mode Select, JTAG Test Port Input. Debug and download access. Test Data In, JTAG Test Port Input. Debug and download access. Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter serial download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 k resistor. General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. Test Clock, JTAG Test Port Input. Debug and download access. Test Data Out, JTAG Test Port Output. Debug and download access. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 f capacitor to DGND. Ground for Core Logic. General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/ ADCBUSY Signal Output. Reset Input, Active Low. Multifunction I/O Pin. External Interrupt Request 0, Active High/GeneralPurpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/GeneralPurpose Input andOutput Port 0.5/ADCBUSY Signa l Output/Programmable Logic Array Output Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/ Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/ Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter.
8 9 10
8 9 10
7 8 9
11
11
10
P0.6/T1/MRST/PLAO[3]
12 13 14 15 16 17 18 19 20
12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19
21
21
20
IRQ1/P0.5/ADCBUSY/PLAO[2]
22
22
21
P2.0/SPM9/PLAO[5]/CONVSTART
23
23
22
P0.7/ECLK/XCLK/SPM8/PLAO[4]
24
24
23
XCLKO
Rev. A | Page 18 of 93
ADuC7019/20/21/22/24/25/26/27
Description Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 f capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power.
29
29
28
P1.4/SPM4/PLAI[4]/IRQ2
30 31 32 33 34 35 36 37
30 31 32 33 34 35 36
29 30 31 32 33 34 35
Rev. A | Page 19 of 93
ADuC7019/20/21/22/24/25/26/27
ADuC7024/ADuC7025
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND DAC REF VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
ADuC7024/ ADuC7025
TOP VIEW (Not to Scale)
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND DAC REF VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
ADuC7024/ ADuC7025
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
04955-067
04955-068
Rev. A | Page 20 of 93
ADuC7019/20/21/22/24/25/26/27
Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP)
Description Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present on the ADuC7025. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present on the ADuC7025. JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 k resistor/General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 F capacitor to DGND. Ground for Core Logic. General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic Array Input Element 8. General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic Array Input Element 9. General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic Array Input Element 10. General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic Array Input Element 11. General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. Reset Input, Active Low. General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic Array Input 12. General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic Array Input Element 13. Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADCBUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] P2.0/SPM9/PLAO[5]/CONVSTART P0.7/ECLK/XCLK/SPM8/PLAO[4]
35
XCLKO
Rev. A | Page 21 of 93
ADuC7019/20/21/22/24/25/26/27
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic XCLKI P3.6/PWMTRIP/PLAI[14] P3.7/PWMSYNC/PLAI[15] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/PLAO[8] P4.1/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3 P1.4/SPM4/PLAI[4]/IRQ2 P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0] P4.2/PLAO[10] P4.3/PLAO[11] P4.4/PLAO[12] P4.5/PLAO[13] VREF DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Description Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. General-Purpose Input and Output Port 3.6/PWM Safety Cut Off/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable Logic Array Input Element 15. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8. General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD. Ground for the DAC. Typically connected to AGND. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. 3.3 V Power Supply for the DACs. Typically connected to AVDD. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Rev. A | Page 22 of 93
ADuC7019/20/21/22/24/25/26/27
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 ADC11 DACV DD AVDD AVDD AGND AGND DACGND DACREF VREF REFGND P4.5/AD13/PLAO[13] P4.4/AD12/PLAO[12] P4.3/AD11/PLAO[11] P4.2/AD10/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PIN 1 INDICATOR
ADuC7026/ ADuC7027
TOP VIEW (Not to Scale)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/AD9/PLAO[9] P4.0/AD8/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P2.2/RS/PWM0L/PLAO[7] P2.1/WS/PWM0H/PLAO[6] P2.7/PWM1L/MS3 P3.7/AD7/PWMSYNC /PLAI[15] P3.6/AD6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY /PLAO[2]/MS0
P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADC BUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
04955-069
ADuC7019/20/21/22/24/25/26/27
Pin No. 14 15 16 17 18 19 20 Mnemonic TMS TDI P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/ PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADCBUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1
41
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0
42
P2.0/SPM9/PLAO[5]/CONVSTART
Description JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access. General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory Byte Low Enable. General-Purpose Input and Output Port 2.3/External Memory Access Enable. General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic Array Output Element 14. General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic Array Output Element 15. Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 k resistor/General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7/External Memory Select 2. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access. General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory Byte High Enable. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 F capacitor to DGND. Ground for Core Logic. General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 HighSide Output/Programmable Logic Array Input Element 8. General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 LowSide Output/Programmable Logic Array Input Element 9. General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 HighSide Output/Programmable Logic Array Input Element 10. General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 LowSide Output/Programmable Logic Array Input Element 11. General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory Select 0. General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory Select 1. General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory Select 2. Reset Input, Active Low. General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 HighSide Output/Programmable Logic Array Input 12. General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 LowSide Output/Programmable Logic Array Input Element 13. Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/External Memory Select 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External Memory Select 0. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC.
Rev. A | Page 24 of 93
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Description Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cut Off/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/Programmable Logic Array Input Element 15. General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory Select 3. General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-Side Output/Programmable Logic Array Output Element 6. General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 LowSide Output/Programmable Logic Array Output Element 7. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic Array Output Element 8. General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic Array Output Element 9. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic Array Output Element 10. General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic Array Output Element 11. General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic Array Output Element 12. General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic Array Output Element 13. Ground for the Reference. Typically connected to AGND. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD. Ground for the DAC. Typically connected to AGND. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power.
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71, 72 73, 74
XCLKO XCLKI P3.6/AD6/PWMTRIP/PLAI[14] P3.7/AD7/PWMSYNC/PLAI[15] P2.7/PWM1L/MS3 P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3 P1.4/SPM4/PLAI[4]/IRQ2 P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0] P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] REFGND VREF DACREF DACGND AGND AVDD
Rev. A | Page 25 of 93
ADuC7019/20/21/22/24/25/26/27
Pin No. 75 76 77 78 79 80 Mnemonic DACVDD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Description 3.3 V Power Supply for the DACs. Typically connected to AVDD. Single-Ended or Differential Analog Input 11. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Rev. A | Page 26 of 93
ADuC7019/20/21/22/24/25/26/27
fS = 774kSPS
fS = 774kSPS
0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 ADC CODES 3000 4000
04955-075
(LSB)
0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 ADC CODES 3000 4000
04955-074
fS = 1MSPS
fS = 1MSPS
(LSB)
0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 ADC CODES 3000 4000
04955-076
(LSB)
(LSB)
(LSB)
0.5 0.4 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 WCN 0.6 0.7 0.8
04955-072
0.9 1.0
0.9 1.0
Figure 18. Typical Worst Case INL Error vs. VREF, fS = 774 kSPS
Figure 21. Typical Worst Case DNL Error vs. VREF, fS = 774 kSPS
Rev. A | Page 27 of 93
(LSB)
0.5
ADuC7019/20/21/22/24/25/26/27
9000 8000 7000
SNR
78
6000
80
FREQUENCY
SNR (dB)
THD 55
82
84 50
2000
04955-073 04955-070
45 40
86
1.0
1.5
3.0
88
60
1300
CODE
(dB)
80 100 120
04955-078
160
200
(dB)
60 80 100 120
04955-079
200
Rev. A | Page 28 of 93
04955-060
140
THD (dB)
60
ADuC7019/20/21/22/24/25/26/27
1.4 1.2 1.0 0.8
(mA)
40
25 85 TEMPERATURE (C)
125
37.0
36.8
36.6
36.4
04955-082 04955-084
36.2
62.25
1000.00
Rev. A | Page 29 of 93
04955-083
ADuC7019/20/21/22/24/25/26/27 TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point LSB below the first code transition and full scale, a point LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, + LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change.
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When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, the SRAM, and the memory mapped registers.
EXCEPTIONS
ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are: Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and for exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 32. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process.
See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets.
EMBEDDEDICE (I)
EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port.
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R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY
04955-007
CPSR
USER MODE
ABORT MODE
IRQ MODE
UNDEFINED MODE
More information relative to the programmers model and the ARM7TDMI core architecture can be found in the following documents from ARM: DDI0029G, ARM7TDMI Technical Reference Manual DDI0100E, ARM Architecture Reference Manual
At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 s in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode, where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.
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FLASH/EE MEMORY
The total 64 kB of Flash/EE memory is organized as 32 k 16 bits (31 k 16 bits is user space and 1 k 16 bits is reserved for the on-chip kernel). The page size of this Flash/EE memory is 512 bytes. Sixty-two kilobytes of Flash/EE memory are available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in thumb mode and 20.89 MHz in full ARM mode. More details about Flash/EE access time are outlined later in the Execution Time from SRAM and Flash/EE section of this datasheet.
SRAM
Eight kilobytes of SRAM are available to the user, organized as 2 k 32 bits, that is, two words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array. More details about SRAM access time are outlined later in the Execution Time from SRAM and Flash/EE section of this datasheet.
0x00011FFF SRAM 0x00010000 0x0000FFFF REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000
Note that by default, after a reset, the Flash/EE memory is mirrored at address 000000000. It is possible to remap the SRAM at address 000000000 by clearing bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of 2 byte location where the different blocks of memory are mapped as outlined in Figure 33. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 memory organizations are configured in little endian format, which means that the least significant byte is located in the lowest byte address, and the most significant byte is in the highest byte address.
BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004 0x00000000
04955-009
32
0xFFFFFFFF
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0xFFFFFFFF 0xFFFFFC3C
PWM
0xFFFFFC00 0xFFFFF820 0xFFFFF800 0xFFFFF46C
Default Value 0x00000000 0x00XXX000 0x00000000 0x00000000 0x00000000 0x00000000 0x00XXX000 0x00000000 0x00000000
Page 75 75 75 75 76 75 76 76 76
GPIO
0xFFFFF400 0xFFFF0B54
PLA
0xFFFF0B00 0xFFFF0A14
SPI
0xFFFF0A00 0xFFFF0948
I2C1
0xFFFF0900 0xFFFF0848
Depends on the level on the external interrupt pins (P0.4, P0.5, P1.4, and P1.5).
I2C0
0xFFFF0800 0xFFFF0730
UART
0xFFFF0700 0xFFFF0620
System control address base = 0xFFFF0200 0x0220 REMAP1 1 R/W 0x00 0x0230 RSTSTA 1 R/W 0x01 0x0234 RSTCLR 1 W 0x00
1
47 47 47
Depends on model.
DAC
0xFFFF0600 0xFFFF0538
ADC
0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0310 0xFFFF0300 0xFFFF0238 0xFFFF0220 0xFFFF0110 0xFFFF0000
WATCHDOG TIMER
WAKE UP TIMER
Timer address base = 0xFFFF0300 0x0300 T0LD 2 R/W 0x0304 T0VAL 2 R 0x0308 T0CON 2 R/W 0x030C T0CLRI 1 W 0x0320 T1LD 4 R/W 0x0324 T1VAL 4 R 0x0328 T1CON 2 R/W 0x032C T1CLRI 1 W 0x0330 T1CAP 4 R/W 0x0340 T2LD 4 R/W 0x0344 T2VAL 4 R 0x0348 T2CON 2 R/W 0x034C T2CLRI 1 W 0x0360 T3LD 2 R/W 0x0364 T3VAL 2 R 0x0368 T3CON 2 R/W 0x036C T3CLRI 1 W PLL base address = 0xFFFF0400 0x0404 POWKEY1 2 0x0408 POWCON 2 0x040C POWKEY2 2 0x0410 PLLKEY1 2 0x0414 PLLCON 1 0x0418 PLLKEY2 2
0x0000 0xFFFF 0x0000 0xFF 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x00000000 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x0000 0xFFFF 0x0000 0x00
77 77 77 77 77 77 77 78 78 78 78 79 79 79 79 79 80
TIMER 0
INTERRUPT CONTROLLER
W R/W W W R/W W
53 53 53 53 53 53
PSM address base = 0xFFFF0440 0x0440 PSMCON 2 R/W 0x0444 CMPCON 2 R/W Reference address base = 0xFFFF0480 0x048C REFCON 1 R/W
Rev. A | Page 34 of 93
0x0008 0x0000
49 50
0x00
42
ADuC7019/20/21/22/24/25/26/27
Access Address Name Byte Type I2C0 base address = 0xFFFF0800 0x0800 I2C0MSTA 1 R 0x0804 I2C0SSTA 1 R 0x0808 I2C0SRX 1 R 0x080C I2C0STX 1 W 0x0810 I2C0MRX 1 R 0x0814 I2C0MTX 1 W 0x0818 I2C0CNT 1 R/W 0x081C I2C0ADR 1 R/W 0x0824 I2C0BYTE 1 R/W 0x0828 I2C0ALT 1 R/W 0x082C I2C0CFG 1 R/W 0x0830 I2C0DIV 2 R/W 0x0838 I2C0ID0 1 R/W 0x083C I2C0ID1 1 R/W 0x0840 I2C0ID2 1 R/W 0x0844 I2C0ID3 1 R/W 0x0848 I2C0CCNT 1 R/W 0x084C I2C0FSTA 2 R I2C1 base address = 0xFFFF0900 0x0900 I2C1MSTA 1 R 0x0904 I2C1SSTA 1 R 0x0908 I2C1SRX 1 R 0x090C I2C1STX 1 W 0x0910 I2C1MRX 1 R 0x0914 I2C1MTX 1 W 0x0918 I2C1CNT 1 R/W 0x091C I2C1ADR 1 R/W 0x0924 I2C1BYTE 1 R/W 0x0928 I2C1ALT 1 R/W 0x092C I2C1CFG 1 R/W 0x0930 I2C1DIV 2 R/W 0x0938 I2C1ID0 1 R/W 0x093C I2C1ID1 1 R/W 0x0940 I2C1ID2 1 R/W 0x0944 I2C1ID3 1 R/W 0x0948 I2C1CCNT 1 R/W 0x094C I2C1FSTA 2 R SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 0x0A04 SPIRX 1 0x0A08 SPITX 1 0x0A0C SPIDIV 1 0x0A10 SPICON 2 Default Value 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000 Page 69 69 70 70 70 70 70 70 70 70 71 71 71 71 71 71 71 72
48 48 48 48 48 48 48 48
0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x60 0x00 0x00 0x04 0x01 0xAA 0x0000
64 64 64 64 64 64 64 65 65 65 65 66 66 66 65
0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000
69 69 70 70 70 70 70 70 70 70 70 71 71 71 71 71 71 71
R R W R/W R/W
67 67 67 67 67
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Address Name Byte PLA base address = 0xFFFF0B00 0x0B00 PLAELM0 2 0x0B04 PLAELM1 2 0x0B08 PLAELM2 2 0x0B0C PLAELM3 2 0x0B10 PLAELM4 2 0x0B14 PLAELM5 2 0x0B18 PLAELM6 2 0x0B1C PLAELM7 2 0x0B20 PLAELM8 2 0x0B24 PLAELM9 2 0x0B28 PLAELM10 2 0x0B2C PLAELM11 2 0x0B30 PLAELM12 2 0x0B34 PLAELM13 2 0x0B38 PLAELM14 2 0x0B3C PLAELM15 2 0x0B40 PLACLK 1 0x0B44 PLAIRQ 4 0x0B48 PLAADC 4 0x0B4C PLADIN 4 0x0B50 PLADOUT 4 0x0B54 PLALCK 1 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x00000000 0x00000000 0x00000000 0x00000000 0x00 Page 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 73 74 74 74 74 74 Address Name
External memory base address = 0xFFFFF000 0xF000 XMCFG 1 R/W 0x00 0xF010 XM0CON 1 R/W 0x00 0xF014 XM1CON 1 R/W 0x00 0xF018 XM2CON 1 R/W 0x00 0xF01C XM3CON 1 R/W 0x00 0xF020 XM0PAR 2 R/W 0x70FF 0xF024 XM1PAR 2 R/W 0x70FF 0xF028 XM2PAR 2 R/W 0x70FF 0xF02C XM3PAR 2 R/W 0x70FF
GPIO base address = 0xFFFFF400 0xF400 GP0CON 4 R/W 0xF404 GP1CON 4 R/W 0xF408 GP2CON 4 R/W 0xF40C GP3CON 4 R/W 0xF410 GP4CON 4 R/W 0xF420 GP0DAT 4 R/W 0xF424 GP0SET 4 W 0xF428 GP0CLR 4 W 0xF42C GP0PAR 4 W 0xF430 GP1DAT 4 R/W 0xF434 GP1SET 4 W 0xF438 GP1CLR 4 W 0xF43C GP1PAR 4 W 0xF440 GP2DAT 4 R/W 0xF444 GP2SET 4 W 0xF448 GP2CLR 4 W 0xF450 GP3DAT 4 R/W 0xF454 GP3SET 4 W 0xF458 GP3CLR 4 W 0xF45C GP3PAR 4 W 0xF460 GP4DAT 4 R/W 0xF464 GP4SET 4 W 0xF468 GP4CLR 4 W Flash/EE base address = 0xFFFFF800 0xF800 FEESTA 1 R 0xF804 FEEMOD 2 R/W 0xF808 FEECON 1 R/W 0xF80C FEEDAT 2 R/W 0xF810 FEEADR 2 R/W 0xF818 FEESIGN 3 R 0xF81C FEEPRO 4 R/W 0xF820 FEEHIDE 4 R/W PWM base address = 0xFFFFFC00 0xFC00 PWMCON 2 R/W 0xFC04 PWMSTA 2 R/W 0xFC08 PWMDAT0 2 R/W 0xFC0C PWMDAT1 2 R/W 0xFC10 PWMCFG 2 R/W 0xFC14 PWMCH0 2 R/W 0xFC18 PWMCH1 2 R/W 0xFC1C PWMCH2 2 R/W 0xFC20 PWMEN 2 R/W 0xFC24 PWMDAT2 2 R/W
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x20000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x00222222 0x000000XX 0x000000XX 0x000000XX
61 61 61 61 61 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62
81 81 81 81 81 81 81 81 81
45 45 45 45 45 45 45 45
0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
60 60 61 61 60 61 61 61 60 61
Rev. A | Page 36 of 93
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differentialmode or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 V when VREF = 2.5 V The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, , FS 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 37.
1111 1111 1111 1111 1111 1110 1111 1111 1101
OUTPUT CODE
The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage VCM, in the range 0 V to AVDD, and with a maximum amplitude of 2 VREF (see Figure 36).
AVDD VCM VCM 2VREF 2VREF
0000 0000 0011 0000 0000 0010 0000 0000 0001 0V 1LSB VOLTAGE INPUT +FS 1LSB
04955-012
Figure 37. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode
04955-011
VCM 0
2VREF
A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later in the Band gap Reference section. Single or continuous conversion modes can be initiated in the software. An external CONVSTART pin, an output generated from the on-chip PLA, or a Timer0 or Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, which measures die temperature to an accuracy of 3C.
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SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 1LSB = 2 VREF 4096
ADC CLOCK
OUTPUT CODE
CONVSTART
ADCBUSY
ADCDAT
DATA
ADC INTERRUPT
TYPICAL OPERATION
Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top 4 bits are the sign bits. The 12-bit result is placed from Bit 16 to Bit 27 as shown in Figure 39. Again, it should be noted that in fully differential mode, the result is represented in twos complement format, and in pseudo differential and singleended modes, the result is represented in straight binary format.
31 27 16 15 0
04955-014
ADuC7019
The ADuC7019 is identical to the ADuC7020 except for one buffered ADC channel, ADC3, and it has only three DACs. The output buffer of the fourth DAC is internally connected to the ADC3 channel as shown in Figure 41.
ADuC7019
MUX ADC3 1MSPS 12-BIT ADC 12-BIT DAC DAC3 ADC15
04955-016
SIGN BITS
Current Consumption
The ADC in standby mode, that is, powered up but not converting, typically consumes 640 A. The internal reference adds 140 A. During conversion, the extra current is 0.3 A multiplied by the sampling frequency (in kHz). Figure 31 shows the current consumption versus the sampling frequency of the ADC.
Note that the DAC3 output pin must be connected to a 10 nF capacitor to AGND. This channel should be used to measure dc voltages only. ADC calibration might be necessary on this channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs described in this section.
Timing
Figure 40 gives details of the ADC timing. Users have control on the ADC clock speed and on the number of acquisition clocks in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 774 kSPS. For conversion on temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32.
ADCCON Register
Name ADCCON Address 0xFFFF0500 Default Value 0x0600 Access R/W
ADCCON is an ADC control register that allows the programmer to enable the ADC peripheral, select the mode of operation of the ADC (either in single-ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. This MMR is described in Table 14.
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04955-015
1 0000 0000 0000 VREF + 1LSB 0LSB +VREF 1LSB VOLTAGE INPUT (VIN+ VIN)
ADCSTA = 0
ADCSTA = 1
ADuC7019/20/21/22/24/25/26/27
ADCCP Register
Address 0xFFFF0504 Default Value 0x00 Access R/W
ADCCP is an ADC positive channel selection register. This MMR is described in Table 15. Table 15. ADCCP1 MMR Bit Designation
Bit 7 to 5 4 to 0 Value Description Reserved Positive channel selection bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Temperature sensor AGND (self-diagnostic feature) Internal reference (self-diagnostic feature) AVDD/2 Reserved
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others
1
ADC and DAC channel availability depends on part model. See the Ordering Guide for details.
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ADCCN Register
Name ADCCN Address 0xFFFF0508 Default Value 0x01 Access R/W
ADCCN is an ADC negative channel selection register. This MMR is described in Table 16. Table 16. ADCCN MMR Bit Designation
Bit 7 to 5 4 to 0 Value Description Reserved Negative channel selection bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Internal reference (self-diagnostic feature) Reserved
ADCGN Register
Name ADCGN Address 0xFFFF0530 Default Value 0x0200 Access R/W
ADCOF Register
Name ADCOF Address 0xFFFF0534 Default Value 0x0200 Access R/W
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture can operate in three different modes: differential, pseudo differential, and single-ended.
Differential Mode
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 each contain a successive approximation ADC based on two capacitive DACs. Figure 42 and Figure 43 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 42 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A. The comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL+ B A SW1 CHANNEL A SW2 B CAPACITIVE DAC
04955-017
ADCSTA Register
Name ADCSTA Address 0xFFFF050C Default Value 0x00 Access R
ADCSTA is an ADC status register that indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCReady (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion, generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBUSY pin. This pin is high during a conversion. When the conversion is finished, ADCBUSY goes back low. This information can be available on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register.
CS
COMPARATOR
CS
SW3
CONTROL LOGIC
VREF
ADCDAT Register
Name ADCDAT Address 0xFFFF0510 Default Value 0x00000000 Access R
ADCDAT is an ADC data result register. Hold the 12-bit ADC result as shown in Figure 39.
ADCRST Register
Name ADCRST Address 0xFFFF0514 Default Value 0x00 Access R/W
When the ADC starts a conversion, as shown in Figure 43, SW3 opens, and then SW1 and SW2 move to Position B. This causes the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADCs output code. The output impedances of the sources driving the VIN+ and VIN pins must be matched; otherwise, the two inputs have different settling times, resulting in errors.
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The capacitors, C1, in Figure 46 are typically 4 pF and can be primarily attributed to pin capacitance. The resistors are lumped components made up of the ON resistance of the switches. The value of these resistors is typically about 100 . The capacitors, C2, are the ADCs sampling capacitors and typically have a capacitance of 16 pF.
AVDD D
CS
COMPARATOR
CS
SW3
CONTROL LOGIC
VREF
R1 C2
C1
AVDD D
R1 C2
C1
D
04955-021
CS
COMPARATOR
Figure 46. Equivalent Analog Input Circuit Conversion Phase: Switches Open; Track Phase: Switches Closed
SW2
CS
SW3
CONTROL LOGIC
VIN
VREF CHANNEL
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to ground. The VIN pin can be floating. The input signal range on VIN+ is 0 V to VREF.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL+ B A SW1 CS CHANNEL CS COMPARATOR
For AC applications, removing high frequency components from the analog input signal is recommended by using an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the AC performance of the ADC. This can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 47 and Figure 48 give an example of ADC front end.
ADuC702x
10 0.01F ADC0
04955-061
SW3
CONTROL LOGIC
ADuC702x
CAPACITIVE DAC
04955-020
ADC0 VREF
04955-062
ADC1
When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades.
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DRIVING THE ANALOG INPUTS
Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on common-mode input signal (VCM), which is dependent on the reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 17 gives some calculated VCM min and VCM max for some conditions. Table 17. VCM Ranges
AVDD 3.3 V VREF 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V VCM Min 1.25 V 1.024 V 0.75 V 1.25 V 1.024 V 0.75 V VCM Max 2.05 V 2.276 V 2.55 V 1.75 V 1.976 V 2.25 V Signal Peak-to-Peak 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V
3.0 V
CALIBRATION
By default, the factory set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part. (See the Specifications section.) If system calibration is required, it is possible to modify the default offset and gain coefficients to improve end-point errors, but note that any modification to the factory set ADCOF and ADCGN values can degrade ADC linearity performance. For system offset error correction, the ADC channel input stage must be tied to AGND. A continuous software ADC conversion loop must be implemented by modifying the value in ADCOF until the ADC result (ADCDAT) reads code 0 to 1. Offset error correction is done digitally and has a resolution of 0.25 LSB and a range of 3.125% of VREF. For system gain error correction, the ADC channel input stage must be tied to VREF. A continuous software ADC conversion loop must be implemented to modify the value in ADCOF until the ADC result (ADCDAT) reads code 4094 to 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 LSB with a range of 3% of VREF.
REFCON Register
Name REFCON Address 0xFFFF048C Default Value 0x00 Access R/W
The band gap reference interface consists of an 8-bit MMR REFCON described in Table 18. Table 18. REFCON MMR Bit Designations
Bit 7 to 2 1 Description Reserved. Internal Reference Power-Down Enable. Set by user to place the internal reference in power-down mode and use as an external reference. Cleared by user to place the internal reference in normal mode and use it for ADC conversions. Internal Reference Output Enable. Set by user to connect the internal 2.5 V reference to the VREF pin. The reference can be used for external component but needs to be buffered. Cleared by user to disconnect the reference from the VREF pin.
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600
RETENTION (Years)
450
300
150
04955-085
30
40
135
150
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. An application note is available at www.analog.com/microconverter describing the protocol via JTAG.
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It is possible to write to a single Flash/EE location address twice. If a single address is written to more than twice, then the data within the Flash/EE memory can be corrupted. That is, it is possible to walk zeros only byte wise.
SECURITY
The 62 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 22) protects the 62 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the flash memory. Each bit protects four pages, that is, 2 kB. Write protection is activated for all types of access.
FEESTA Register
Name FEESTA Address 0xFFFFF800 Default Value 0x20 Access R
FEESTA is a read-only register that reflects the status of the flash control interface as described in Table 19. Table 19. FEESTA MMR Bit Designations
Bit 15 to 6 5 Description Reserved. Burst Command Enable. Set when the command is a burst command: 0x07, 0x08, or 0x09. Cleared when another command. Reserved. Flash Interrupt Status Bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEEMOD register is set. Cleared when reading FEESTA register. Flash/EE Controller Busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command Fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading FEESTA register. Command Pass. Set by MicroConverter when a command completes successfully. Cleared automatically when reading FEESTA register.
FEEMOD Register
Address 0xFFFFF804 Default Value 0x0000 Access R/W
FEEMOD sets the operating mode of the flash control interface. Table 20 shows FEEMOD MMR bit designations. Table 20. FEEMOD MMR Bit Designations
Bit 15 to 9 8 7 to 5 Description Reserved. Reserved. This bit should always be set to 0. Reserved. These bits should always be set to 0 except when writing keys. See the Sequence to Write the Key section. Flash/EE Interrupt Enable. Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. Erase/Write Command Protection. Set by user to enable the erase and write commands. Cleared to protect the Flash against erase/write command. Reserved. These bits should always be set to 0. Address 0xFFFFF808 Default Value 0x07 Access R/W
To remove or modify the protection, the same sequence is used with a modified value of FEEPRO. If the key chosen is the value 0DEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The sequence to write the key is illustrated in the following example (this protects writing pages 4 to 7 of the Flash):
FEEPRO=0xFFFFFFFD; FEEMOD=0x48; FEEADR=0x1234; FEEDAT=0x5678; FEECON= 0x0C; //Protect pages 4 to 7 //Write key enable //16 bit key value //16 bit key value // Write key command
2 to 0 Name FEECON
The same sequence should be followed to protect the part permanently with FEEADR = 0DEAD and FEEDAT = 0DEAD.
FEECON Register
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FEEDAT Register
Name FEEDAT Address 0xFFFFF80C Default Value 0xXXXX Access R/W
0x031
0x041
Single Verify
0x051 0x061
0x0A 0x0B
Reserved Signature
0x0C
Protect
Description Idle State. Load FEEDAT with the 16-bit data. Indexed by FEEADR. Write FEEDAT at the address pointed by FEEADR. This operation takes 20 s. Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation takes 20 ms. Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the comparison is returned in FEESTA Bit 1. Erase the page indexed by FEEADR. Erase 62 kB of user space. The 2 kB of kernel are protected. This operation takes 2.48 seconds. To prevent accidental execution, a command sequence is required to execute this instruction. See the Command Sequence for Executing a Mass Erase section. Default Command. No write is allowed. This operation takes two cycles. Write can handle a maximum of 8 data of 16 bits and takes a maximum of 8 x 20 s. Automatically erases the page indexed by the write; writes pages without running an erase command. This command takes 20 ms to erase the page + 20 s per data to write. Reserved. Give a signature of the 64 kB of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles. This command can run only once. The value of FEEPRO is saved and removed only with a mass erase (0x06) or the key. Reserved. Reserved. No operation; interrupt generated.
FEEADR Register
Name FEEADR Address 0xFFFFF810 Default Value 0x0000 Access R/W
FEESIGN Register
Name FEESIGN Address 0xFFFFF818 Default Value 0xFFFFFF Access R
FEEPRO Register
Name FEEPRO Address 0xFFFFF81C Default Value 0x00000000 Access R/W
FEEPRO MMR provides immediate protection. It does not require any software keys, see Table 22.
FEEHIDE Register
Name FEEHIDE Address 0xFFFFF820 Default Value 0xFFFFFFFF Access R/W
FEEHIDE provides protection following subsequent reset of the MMR. It requires a software key. See description in Table 22. Table 22. FEEPRO and FEEHIDE MMR Bit Designations
Bit 31 30 to 0 Description Read Protection. Cleared by user to protect all code. Set by user to allow reading the code. Write Protection for Pages 123 to 120, pages 119 to 116, and pages 0 to 3. Cleared by user to protect the pages in writing. Set by user to allow writing the pages.
The FEECON register always reads 0x07 immediately after execution of any of these commands.
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EXECUTION TIME FROM SRAM AND FLASH/EE
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2 ns and a clock cycle is 22 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE). One cycle to execute the instruction, and two cycles to get the 32-bit data from Flash/EE. A control flow instruction (a branch instruction, for example) takes one cycle to fetch but also takes two cycles to fill the pipeline with the new instructions.
SRAM
By default, and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, which facilitates execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, being executed in 32-bit ARM mode, and the SRAM being 32-bit wide instead of 16-bit wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7019/7020/7021/7022/7024/7025/7026/7027, execution starts automatically in factory programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027 are in normal mode (BM pin is high), then they execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. The remap is done from Flash/EE by setting Bit 0 of the REMAP register. Precaution must be taken to execute this command from Flash/EE, above address 0x00080020, and not from the bottom of the array as this is replaced by the SRAM. This operation is reversible. The Flash/EE can be remapped at address 0x00000000 by clearing Bit 0 of the REMAP MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any type of reset remaps the Flash/EE memory at the bottom of the array.
Dead Time 1 1 N2 1 1 N1
Data Access 2 1 2 x N2 2 x 20 s 20 s 2 x N x 20 s1
Dead Time 1 1 N1 1 1 N1
The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles plus 40 s. 2 N is the number of data to load or store in the multiple load/store instruction (1 <N 16).
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RSTSTA Register
Address 0xFFFF0230 Default Value 0x01 Access R/W
REMAP Register
Name REMAP
1
Address 0xFFFF0220
Access R/W
Depends on model.
RSTCLR Register
Name RSTCLR Address 0xFFFF0234 Default Value 0x00 Access R/W
2, 1 0
Remap
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MMRs Interface
Each DAC is configurable independently through a control register and a data register. These two registers are identical for the four DACs. Only DAC0CON (see Table 26) and DAC0DAT (see Table 27) are described in detail in this section.
DACxCON Registers
Name DAC0CON DAC1CON DAC2CON DAC3CON Address 0xFFFF0600 0xFFFF0608 0xFFFF0610 0xFFFF0618 Default Value 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W
R R
04955-023
DACCLR
3 2 1, 0 00 01 10 11
As illustrated in Figure 51, the reference source for each DAC is user selectable in software. It can be either AVDD, VREF, or DACREF. In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-DACREF mode, the DAC output transfer function spans from 0 V to the voltage at the DACREF pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal 2.5 V reference, VREF. The DAC output buffer amplifier features a true rail-to-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 5 mV of both AVDD and ground. Moreover, the DACs linearity specification (when driving a 5 k resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in 0-to-AVDD mode only, codes 3995 to 4095.
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POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the ADuC7019/7020/7021/7022/7024/7025/7026/7027. It indicates when the IOVDD supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, then the monitor interrupts the core using the PSMI bit in the PSMCON MMR. This bit is immediately cleared once CMP goes high. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brown-out conditions. It also ensures that normal code execution does not resume until a safe supply level has been established.
PSMCON Register
Name PSMCON Address 0xFFFF0440 Default Value 0x0008 Access R/W
The endpoint nonlinearities conceptually illustrated in Figure 52 get worse as a function of output loading. Most of the ADuC7019/7020/7021/7022/7024/7025/7026/7027s data sheet specifications assume a 5 k resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 52 become larger. With larger current demands, this can significantly limit output voltage swing.
2 1
TP PSMEN
PSMI
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COMPARATOR
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrate voltage comparators. The positive input is multiplexed with ADC2 and the negative input has two options: ADC3 or DAC0. The output of the comparator can be configured to generate a system interrupt, can be routed directly to the programmable logic array, can start an ADC conversion, or can be on an external pin, CMPOUT, as shown in Figure 53.
IRQ MUX MUX DAC0
04955-025
CMPCON Register
Name CMPCON Address 0xFFFF0444 Default Value 0x0000 Access R/W
ADC2/CMP0 ADC3/CMP1
P0.0/CMPOUT
Hysteresis
Figure 54 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (VOS) is the difference between the center of the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (VH) is the width of the hysteresis range.
COMPOUT VH VH
VOS
COMP0
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON, which is described in
04955-063
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CMPEN
9, 8 00 01 10 11 7, 6 00 01 10 11 5
CMPIN
CMPOC
CMPOL
4, 3 00 01 10 11 2
CMPRES
CMPHYST
CMPORI
CMPOFI
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OSCILLATOR AND PLLPOWER CONTROL
Clocking System
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrates a 32.768 kHz 3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a stable 41.78 MHz clock for the system referred to as UCLK. To allow power saving, the core can operate at this frequency, or at binary submultiples of it. The actual core operating frequency, UCLK/2CD, is refered to as HCLK. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency can also come from an external clock on the ECLK pin as described in Figure 55. The core clock can be outputted on the ECLK pin when using an internal oscillator or external crystal.
XCLKO XCLKI
WATCHDOG TIMER
CRYSTAL OSCILLATOR
WAKEUP TIMER AT POWER UP OCLK 32.768kHz 41.78MHz MDCLK I2C UCLK ANALOG PERIPHERALS P0.7/XCLK
PLL
CD CORE
/2CD HCLK
04955-026
*32.768kHz 3%
P0.7/ECLK
The selection of the clock source is in the PLLCON register. By default, the part uses the internal oscillator feeding the PLL.
ADuC7019/20/21/22/24/25/26/27
Table 33. POWCON MMR Bit Designations
Value Name PC 000 001 010 011 Description Reserved. Operating Modes. Active Mode. Pause Mode. Nap. Sleep Mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7019/7020/7021/7022/7024/ 7025/7026/7027. Stop Mode. IRQ0 to IRQ3 can wake up the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027. Reserved. Reserved. CPU Clock Divider Bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. 2.61 MHz. 1.31 MHz. 653 kHz. 326 kHz.
PLLKEYx Registers
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W
100
PLLCON Register
Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access R/W
POWKEYx Registers
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access W W
POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access R/W
4, 3, 2 1, 0 00 01 10 11
MDCLK
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In double update mode, it is also possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. This technique permits closed-loop controllers to change the average voltage applied to the machine windings at a faster rate. As a result, faster closed-loop bandwidths are achieved. The operating mode of the PWM block is selected by a control bit in the PWMCON register. In single update mode, a PWMSYNC pulse is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The PWM block can also provide an internal synchronization pulse on the PWMSYNC pin that is synchronized to the PWM switching frequency. In single update mode, a pulse is produced at the start of each PWM period. In double update mode, an additional pulse is produced at the mid-point of each PWM period. The width of the pulse is programmable through the PWMDAT2 register. The PWM block can also accept an external synchronization pulse on the PWMSYNC pin. The selection of external synchronization or internal synchronization is in the PWMCON register. The SYNC input timing can be synchronized to the internal peripheral clock, which is selected in the PWMCON register. If the external synchronization pulse from the chip pin is asynchronous to the internal peripheral clock (typical case), the external PWMSYNC is considered asynchronous and should be synchronized. The synchronization logic adds latency and jitter from the external pulse to the actual PWM outputs. The size of the pulse on the PWMSYNC pin must be greater than two core clock periods. The PWM signals produced by the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027 can be shut off via a dedicated asynchronous PWM shutdown pin, PWMTRIP. When brought low, PWMTRIP instantaneously places all six PWM outputs in the off state (high). This hardware shutdown mechanism is asynchronous so that the associated PWM disable circuitry does not go through any clocked logic. This ensures correct PWM shutdown even in the event of a core clock loss. Status information about the PWM system is available to the user in the PWMSTA register. In particular, the state of the PWMTRIP pin is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period.
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The Output Control Unit. This block can redirect the outputs of the three-phase timing unit for each channel to either the high-side or low-side output. In addition, the output control unit allows individual enabling/disabling of each of the six PWM output signals. The Gate Drive Unit. This block can generate the high frequency chopping frequency and its subsequent mixing with the PWM signals. The PWM Shutdown Controller. This block takes care of the PWM shutdown via the PWMTRIP pin and generates the correct reset signal for the timing unit.
// Configure Port Pins GP4CON = 0x300; // P4.2 as PLA output GP3CON = 0x1; // P3.0 configured as // output of PWM0 //(internally) // PWM0 onto P4.2 PLAELM8 = 0x0035; PLAELM10 = 0x0059; // P3.0 (PWM output) // input of element 8 // PWM from element 8
The PWMSYNC pulse control unit generates the internal synchronization pulse and also controls whether the external PWMSYNC pin is used or not. The PWM controller is driven by the ADuC7019/20/21/22/24/ 25/26/27 core clock frequency and is capable of generating two interrupts to the ARM core. One interrupt is generated on the occurrence of a PWMSYNC pulse, and the other is generated on the occurrence of any PWM shutdown action.
CONFIGURATION REGISTERS DUTY CYCLE REGISTERS PWMCON PWMDAT0 PWMCH0 PWMDAT1 PWMCH1 PWMDAT2 PWMCH2
PWMEN
PWMCFG
SYNC
04955-027
PWMSYNC PWMTRIP
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Three-Phase Timing Unit PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM period register, PWMDAT0. The fundamental timing unit of the PWM controller is tCORE = 1/fCORE where fCORE is the core frequency of the MicroConverter.
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Both switching edges are moved by an equal amount (PWMDAT1 tCORE) to preserve the symmetrical output patterns. Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA register, which indicates whether operation is in the first or second half cycle of the PWM period. The resulting on-times of the PWM signals over the full PWM period (two half periods) produced by the timing unit can be written as follows: On the high side T0HH = PWMDAT0 + 2(PWMCH0 PWMDAT1) tCORE T0HL = PWMDAT0 2(PWMCH0 PWMDAT1) tCORE
PWMSYNC
PWMDAT2+1
PWMSYNC
PWMSTA (0)
PWMDAT21+1
PWMDAT22+1
Figure 57. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode
PWMDAT01
PWMDAT02
Figure 58. Typical PWM Outputs of the Three-Phase Timing Unit in Double Update Mode
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04955-029
PWMDAT0
PWMDAT0
04955-028
PWMSTA (0)
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In general, the on-times of the PWM signals in double update mode can be defined as follows: On the high side
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The chopping frequency is therefore an integral subdivision of the MicroConverter core frequency fCHOP = fCORE/(4 (GDCLK + 1)) The GDCLK value can range from 0 to 255, corresponding to a programmable chopping frequency rate from 40.8 kHz to 10.44 MHz for a 41.78 MHz core frequency. The gate drive features must be programmed before operation of the PWM controller and are typically not changed during normal operation of the PWM controller. Following a reset, all bits of the PWMCFG register are cleared so that high frequency chopping is disabled, by default.
PWMCH0 PWMCH0
0H
2 PWMDAT1 2 PWMDAT1
0L
1H
1L
2H
0L
04955-030
2L PWMDAT0 PWMDAT0
2 PWMDAT1
2 PWMDAT1
PWMDAT0
PWMDAT0
In addition, the other four signals (0L, 1H, 2H, and 2L) have been disabled by setting the appropriate enable/disable bits of the PWMEN register. In Figure 59, the appropriate value for the PWMEN register is 000A7. In normal ECM operation, each inverter leg is disabled for certain periods of time so that the PWMEN register is changed based on the position of the rotor shaft (motor commutation).
Figure 60. Typical PWM Signals with High Frequency Gate Chopping Enabled on Both High-Side and Low-Side Switches
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04955-031
Figure 59. Active LO PWM Signals Suitable for ECM Control, PWMCH0 = PWMCH1, Crossover 1H/1L Pair and Disable 0L, 1H, 2H, and 2L Outputs in Single Update Mode.
0H 4 (GDCLK + 1) tCORE
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PWM MMRs Interface
The PWM block is controlled via the MMRs described in this section.
Name PWMCFG
PWMCFG is a gate chopping register. Table 37. PWMCFG MMR Bit Descriptions
Bit 15 to 10 9 8 7 to 0 Name CHOPLO CHOPHI GDCLK Description Reserved. Low-side gate chopping enable bit. High-side gate chopping enable bit. PWM gate chopping period (unsigned).
PWMCON Register
Name PWMCON Address 0xFFFFFC00 Default Value 0x0000 Access R/W
PWMCON is a control register that enables the PWM and chooses the update rate. Table 35. PWMCON MMR Bit Descriptions
Bit 7 to 5 4 3 Name Description Reserved. External Sync Select. Set to use external sync. Cleared to use internal sync. External Sync Select. Set to select external synchronous sync signal. Cleared for asynchronous sync signal. Double Update Mode. Set to 1 by user to enable double update mode. Cleared to 0 by the user to enable single update mode. PWM Synchronization Enable. Set by user to enable synchronization. Cleared by user to disable synchronization. PWM Enable Bit. Set to 1 by the user to enable the PWM. Cleared to 0 by the user to disable the PWM. Also cleared automatically with PWMTRIP.
PWMEN Register
Name PWMEN Address 0xFFFFFC20 Default Value 0x0000 Access R/W
PWM_SYNCSEL PWM_EXTSYNC
PWMEN allows enabling channel outputs and crossover. See its bit definitions in Table 38. Table 38. PWMEN MMR Bit Descriptions
Bit 8 Name 0H0L_XOVR Description Channel 0 Output Crossover Enable Bit. Set to 1 by user to enable Channel 0 output crossover. Cleared to 0 by user to disable Channel 0 output crossover. Channel 1 Output Crossover Enable Bit. Set to 1 by user to enable Channel 1 output crossover. Cleared to 0 by user to disable Channel 1 output crossover. Channel 2 Output Crossover Enable Bit. Set to 1 by user to enable Channel 2 output crossover. Cleared to 0 by user to disable Channel 2 output crossover. 0L Output Enable Bit. Set to 1 by user to disable the 0L output of the PWM. Cleared to 0 by user to enable the 0L output of the PWM. 0H Output Enable Bit. Set to 1 by user to disable the 0H output of the PWM. Cleared to 0 by user to enable the 0H output of the PWM. 1L Output Enable Bit. Set to 1 by user to disable the 1L output of the PWM. Cleared to 0 by user to enable the 1L output of the PWM. 1H Output Enable Bit. Set to 1 by user to disable the 1H output of the PWM. Cleared to 0 by user to enable the 1H output of the PWM. 2L Output Enable Bit. Set to 1 by user to disable the 2L output of the PWM. Cleared to 0 by user to enable the 2L output of the PWM. 2H Output Enable Bit. Set to 1 by user to disable the 2H output of the PWM. Cleared to 0 by user to enable the 2H output of the PWM.
PWMDBL
PWM_SYNC_EN
1H1L_XOVR
PWMEN
2H2L_XOVR
PWMSTA Register
Name PWMSTA Address 0xFFFFFC04 Default Value 0x0000 Access R/W 5 0L_EN
PWMSTA reflects the status of the PWM. Table 36. PWMSTA MMR Bit Descriptions
Bit 15 to 10 9 8 3 2, 1 0 Name Description Reserved. 3 PWMSYNCINT PWMTRIPINT PWMTRIP PWMPHASE PWM Sync Interrupt Bit. PWM Trip Interrupt Bit. Raw Signal from the PWMTRIP Pin. Reserved. PWM Phase Bit. Set to 1 by the MicroConverter when the timer is counting down (1st half). Cleared to 0 by the MicroConverter when the timer is counting up (2nd half). 1L_EN 4 0H_EN
1H_EN
2L_EN
2H_EN
PWMCFG Register
PWMDAT0 Register
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Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 00 GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 01 CMP PWM2H PWM2L TRST PWMTRIP ADCBUSY MRST ECLK/XCLK1 SIN SOUT RTS CTS RI DCD DSR DTR CONVSTART2 PWM0H PWM0L PWM0H PWM0L PWM1H PWM1L PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L PWMTRIP PWMSYNC 10 MS2 BLE BHE A16 MS1 MS0 AE SIN SCL0 SDA0 SCL1 SDA1 CLK MISO MOSI CSL SOUT WS RS AE MS0 MS1 MS2 MS3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 11 PLAI[7]
PWMDAT1 Register
Name PWMDAT1 Address 0xFFFFFC0C Default Value 0x0000 Access R/W
PWMCHx Registers
Name PWMCH0 PWMCH1 PWMCH2 Address 0xFFFFFC14 0xFFFFFC18 0xFFFFFC1C Default Value 0x0000 0x0000 0x0000 Access R/W R/W R/W
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles for the three phases.
PWMDAT2 Register
Name PWMDAT2 Address 0xFFFFFC24 Default Value 0x0000 Access R/W
ADCBUSY PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[5] PLAO[6] PLAO[7]
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 provide 40 general-purpose, bi-directional I/O (GPIO) pins. All I/O pins are 5 V tolerant, which means that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see Table 39 for the pin function definitions). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor (of about 100 k) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIO can drive 1.6 mA at the same time. The following GPIO have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7, and the 8 GPIOs of P1. The 40 GPIO are grouped in five ports, Port 0 to Port 4. Each port is controlled by four or five MMRs, x representing the port number. Note that the kernel changes P0.6 from its default configuration at reset (MRST) to GPIO mode. If MRST is used for external circuitry, an external pull-up resistor should be used to ensure that the level on P0.6 does not drop when the kernel switches mode. For example, if MRST is required for power down, it can be reconfigured in GP0CON MMR.
3
PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11] PLAO[12] PLAO[13] PLAO[14] PLAO[15]
When configured in Mode 1, PO.7 is ECLK by default, or core clock output. To configure it as a clock input, MDCLK bits in PLLCON must be set to 11. 2 The CONVSTART signal is active in all modes of P2.0.
GPxCON Registers
Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFFF400 0xFFFFF404 0xFFFFF408 0xFFFFF40C 0xFFFFF410 Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W
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GPxCON are the port x control registers, which select the function of each pin of port x. as described in Table 40. Table 40. GPxCON MMR Bit Descriptions
Bit 31, 30 29, 28 27, 26 25, 24 23, 22 21, 20 19, 18 17, 16 15, 14 13, 12 11, 10 9, 8 7, 6 5, 4 3, 2 1, 0 Description Reserved Select Function of Px.7 Pin Reserved Select Function of Px.6 Pin Reserved Select Function of Px.5 Pin Reserved Select Function of Px.4 Pin Reserved Select Function of Px.3 Pin Reserved Select Function of Px.2 Pin Reserved Select Function of Px.1 Pin Reserved Select Function of Px.0 Pin Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT
GPxDAT are port x configuration and data registers. They configure the direction of the GPIO pins of port x, set the output value for the pins configured as output, and store the input value of the pins configured as input. Table 42. GPxDAT MMR Bit Descriptions
Bit 31 to 24 Description Direction of the Data. Set to 1 by user to configure the GPIO pin as an output. Cleared to 0 by user to configure the GPIO pin as an input. Port x Data Output. Reflect the State of Port x Pins at Reset (read only). Port x Data Input (read only).
23 to 16 15 to 8 7 to 0
GPxPAR program the parameters for Port 0, Port 1, and Port 3. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Table 41. GPxPAR MMR Bit Descriptions
Bit 31 to 29 28 27 to 25 24 23 to 21 20 19 to 17 16 15 to 13 12 11 to 9 8 7 to 5 4 3 to 1 0 Description Reserved Pull-Up Disable Px.7 Reserved Pull-Up Disable Px.6 Reserved Pull-Up Disable Px.5 Reserved Pull-Up Disable Px.4 Reserved Pull-Up Disable Px.3 Reserved Pull-Up Disable Px.2 Reserved Pull-Up Disable Px.1 Reserved Pull-Up Disable Px.0
GPxSET are data set port x registers. Table 43. GPxSET MMR Bit Descriptions
Bit 31 to 24 23 to 16 Description Reserved. Data Port x Set Bit. Set to 1 by user to set bit on port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved.
15 to 0
GPxCLR Registers
Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR Address 0xFFFFF428 0xFFFFF438 0xFFFFF448 0xFFFFF458 0xFFFFF468 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W
GPxCLR are data clear port x registers. Table 44. GPxCLR MMR Bit Descriptions
Bit 31 to 24 23 to 16 Description Reserved. Data Port x Clear Bit. Set to 1 by user to clear bit on port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved.
15 to 0
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Baud Rate Generation
There are two ways of generating the UART baud rate.
1.
The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Baud rate = 41.78 MHz 2 16 2 DL
CD
Table 47 gives some common baud rate values. Table 47. Baud Rate Using the Normal Baud Rate Generator
Baud Rate 9600 19200 115200 9600 19200 115200 CD 0 0 0 3 3 3 DL 88 h 44 h 0B h 11 h 8h 1h Actual Baud Rate 9600 19200 118691 9600 20400 163200 % Error 0% 0% 3% 0% 6.25% 41.67%
Table 45 also details the mode for each of the SPMUX GPIO pins. This configuration has to be done via the GP0CON, GP1CON, and GP2CON MMRs. By default these ten pins are configured as GPIOs.
2.
The fractional divider combined with the normal baud rate generator produces a wider range of more accurate baud rates.
CORE CLOCK /2 FBEN
/(M+N/2048)
N ) 2048
For example, generation of 19,200 baud with CD bits = 3 (Table 47 gives DL = 8 h),
M+ 41.78 MHz N = 2048 19200 2 3 16 8 2
M+
N = 1.06 2048
The serial communication adopts an asynchronous protocol, which supports various word lengths, stop bits, and parity generation options selectable in the configuration register.
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04955-032
/16DL
UART
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where: Baud Rate = 19,200 bps Error = 0% compared to 6.25% with the normal baud rate generator.
Name COMDIV1
COMIID0 Register
Name COMIID0 Address 0xFFFF0708 Default Value 0x01 Access R
COMIID0 is the interrupt identification register. Table 49. COMIID0 MMR Bit Descriptions
Bit 2:1 Status Bits 00 11 10 01
COMTX Register
Name COMTX Address 0xFFFF0700 Default Value 0x00 Access R/W
Bit 0 NINT 1 0 0 0
Priority 1 2 3
COMRX Register
Name COMRX Address 0xFFFF0700 Default Value 0x00 Access R
Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt
Clearing Operation Read COMSTA0 Read COMRX Write data to COMTX or read COMIID0 Read COMSTA1 register
COMDIV0 Register
Name COMDIV0 Address 0xFFFF0700 Default Value 0x00 Access R/W
00
COMDIV0 is a low-byte divisor latch. COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in COMCON0 register is cleared. COMDIV0 can be accessed when Bit 7 of COMCON0 is set.
COMCON0 Register
Name COMCON0 Address 0xFFFF070C Default Value 0x00 Access R/W
COMCON0 is the line control register. Table 50. COMCON0 MMR Bit Descriptions
Bit 7 Name DLAB Description Divisor Latch Access. Set by user to enable access to COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX and COMTX. Set Break. Set by user to force SOUT to 0. Cleared to operate in normal mode. Stick Parity. Set by user to force parity to defined values: 1 if EPS = 1 and PEN = 1, 0 if EPS = 0 and PEN = 1. Even Parity Select Bit. Set for even parity. Cleared for odd parity. Parity Enable Bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Stop Bit. Set by user to transmit 1.5 stop bits if the word length is 5 bits or 2 stop bits if the word length is 6 bits, 7 bits, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by user to generate 1 stop bit in the transmitted data. Word Length Select: 00 = 5 bits, 01 = 6 bits 10 = 7 bits, 11 = 8 bits
COMIEN0 Register
Name COMIEN0 Address 0xFFFF0704 Default Value 0x00 Access R/W
COMIEN0 is the interrupt enable register. Table 48. COMIEN0 MMR Bit Descriptions
Bit 7 to 4 3 Name EDSSI Description Reserved. Modem Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMSTA1[3:0] are set. Cleared by user. RX Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMSTA0[3:0] are set. Cleared by user. Enable Transmit Buffer Empty Interrupt. Set by user to enable interrupt when buffer is empty during a transmission. Cleared by user. Enable Receive Buffer Full Interrupt. Set by user to enable interrupt when buffer is full during a reception. Cleared by user. 6 5 BRK SP
ELSI
4 3
EPS PEN
ETBEI
STOP
ERBFI
1, 0
WLS
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COMSTA1 Register
Address 0xFFFF0718 Default Value 0x00 Access R
COMCON1 is the modem control register. Table 51. COMCON1 MMR Bit Descriptions
Bit 7 to 5 4 Name Description Reserved. Loop Back. Set by user to enable loop back mode. In loop back mode, the SOUT is forced high. The modem signals are also directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD). Cleared by user to be in normal mode. Parity Enable Bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Stop Bit. Set by user to transmit 1.5 stop bits if the word length is 5 bits or 2 stop bits if the word length is 6 bits, 7 bits, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by user to generate 1 stop bit in the transmitted data. Request To Send. Set by user to force the RTS output to 0. Cleared by user to force the RTS output to 1. Data Terminal Ready. Set by user to force the DTR output to 0. Cleared by user to force the DTR output to 1.
COMSTA1 is a modem status register. Table 53. COMSTA1 MMR Bit Descriptions
Bit 7 6 5 4 3 Name DCD RI DSR CTS DDCD Description Data Carrier Eetect. Ring Indicator. Data Set Ready. Clear To Send. Delta DCD. Set automatically if DCD changed state since COMSTA1 last read. Cleared automatically by reading COMSTA1. Trailing Edge RI. Set if NRI changed from 0 to 1 since COMSTA1 last read. Cleared automatically by reading COMSTA1. Delta DSR. Set automatically if DSR changed state since COMSTA1 last read. Cleared automatically by reading COMSTA1. Delta CTS. Set automatically if CTS changed state since COMSTA1 last read. Cleared automatically by reading COMSTA1.
LOOPBACK
TERI
PEN
DDSR
STOP
DCTS
COMSCR Register
Name COMSCR Address 0xFFFF071C Default Value 0x00 Access R/W
RTS
DTR
COMSCR is an 8-bit scratch register used for temporary storage. It is also used in network addressable UART mode.
COMDIV2 Register
Name COMDIV2 Address 0xFFFF072C Default Value 0x0000 Access R/W
COMSTA0 Register
Name COMSTA0 Address 0xFFFF0714 Default Value 0x60 Access R
COMDIV2 is a 16-bit fractional baud divide register. Table 54. COMDIV2 MMR Bit Descriptions
Bit 15 Name FBEN Description Fractional Baud Rate Generator Enable Bit. Set by user to enable the fractional baud rate generator. Cleared by user to generate baud rate using the standard 450 UART baud rate generator. Reserved. M if FBM = 0, M = 4. N.
COMSTA0 is the line status register. Table 52. COMSTA0 MMR Bit Descriptions
Bit 7 6 Name TEMT Description Reserved. COMTX Empty Status Bit. Set automatically if COMTX is empty. Cleared automatically when writing to COMTX. COMTX and COMRX Empty. Set automatically if COMTX and COMRX are empty. Cleared automatically when one of the register receives data. Break Error. Set when SIN is held low for more than the maximum word length. Cleared automatically. Framing Error. Set when invalid stop bit. Cleared automatically. Parity Error. Set when a parity error occurs. Cleared automatically. Overrun Error. Set automatically if data is overwritten before being read. Cleared automatically. Data Ready. Set automatically when COMRX is full. Cleared by reading COMRX.
THRE
14, 13 12, 11 10 to 0
FBM[1-0] FBN[10-0]
4 3 2 1 0
BI FE PE OE DR
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Network Addressable UART Mode
This mode connects the MicroConverter to a 256-node serial network, either as a hardware single-master or via software in a multimaster network. Bit 7 of COMIEN1 (ENAM bit) must be set to enable UART in network addressable mode. Note that there is no parity check in this mode; the parity bit is used for address.
Bit 3:1 Status Bits 000 110 101 Bit 0 NINT 1 0 0
Priority 2 3
0 0 0
1 2 3
Definition No interrupt Matching network address Address transmitted, buffer empty Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt
COMIEN1 Register
Name COMIEN1 Address 0xFFFF0720 Default Value 0x04 Access R/W
000
COMADR Register
Name COMADR Address 0xFFFF0728 Default Value 0xAA Access R/W
COMIEN1 is an 8-bit network enable register. Table 55. COMIEN1 MMR Bit Descriptions
Bit 7 Name ENAM Description Network Address Mode Enable Bit. Set by user to enable network address mode. Cleared by user to disable network address mode. 9-Bit Transmit Enable Bit. Set by user to enable 9-bit transmit. ENAM must be set. Cleared by user to disable 9-bit transmit. 9-Bit Receive Enable Bit. Set by user to enable 9-bit receive. ENAM must be set. Cleared by user to disable 9-bit receive. Network Interrupt Enable Bit. Word Length. Set for 9-bit data. E9BT has to be cleared. Cleared for 8-bit data. Transmitter Pin Driver Enable Bit. Set by user to enable SOUT pin as an output in slave mode or multimaster mode. Cleared by user; SOUT is three-state. Network Address Bit. Interrupt polarity bit. Network Address Bit. Set by user to transmit the slaves address. Cleared by user to transmit data.
E9BT
COMADR is an 8-bit, read/write network address register that holds the address that the network addressable UART checks for. Upon receiving this address, the device interrupts the processor and/or sets the appropriate status bit in COMIID1.
E9BR
4 3 2
1 0
NABP NAB
COMIID1 Register
Name COMIID1 Address 0xFFFF0724 Default Value 0x01 Access R
COMIID1 is an 8-bit network interrupt register. Bit 7 to Bit 4 are reserved (see Table 56).
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SPISTA Register
Address 0xFFFF0A00 Default Value 0x00 Access R/W
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4 of this register generates an interrupt. Bit 6 of the SPICON register determines which bit generates the interrupt. Table 58. SPISTA MMR Bit Descriptions
Bit 7, 6 5 4 3 Description Reserved. SPIRX Data Register Overflow Status Bit. Set if SPIRX is overflowing. Cleared by reading SPISRX register. SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading SPIRX register. SPIRX Data Register Full Status Bit. Set automatically if a valid data is present in the SPIRX register. Cleared by reading SPIRX register. SPITX Data Register Underflow Status Bit. Set automatically if SPITX is under flowing. Cleared by writing in the SPITX register. SPITX Data Register IRQ. Set automatically if Bit 0 is clear or Bit 2 is set. Cleared by writing in the SPITX register or if finished transmission disabling the SPI. SPITX Data Register Empty Status Bit. Set by writing to SPITX to send data. This bit is set during transmission of data. Cleared when SPITX is empty.
f serial clock =
fUCLK 2 (1 + SPIDIV )
The maximum speed of the SPI clock is dependant on the clock divider bits and is summarized in Table 57. Table 57. SPI Speed vs. Clock Divider Bits in Master Mode CD Bits SPIDIV in hex SPI speed in MHz 0 0x05 3.482 1 0x0B 1.741 2 0x17 0.870 3 0x2F 0.435 4 0x5F 0.218 5 0xBF 0.109
In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10.4 Mb at CD = 0. The formula to determine the maximum speed is as follow:
SPIRX Register
Name SPIRX Address 0xFFFF0A04 Default Value 0x00 Access R
f serialclock =
f HCLK 4
In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices.
SPITX Register
Name SPITX Address 0xFFFF0A08 Default Value 0x00 Access W
SPIDIV Register
Name SPIDIV Address 0xFFFF0A0C Default Value 0x1B Access R/W
SPICON Register
Name SPICON Address 0xFFFF0A10 Default Value 0x0000 Access R/W
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Table 59. SPICON MMR Bit Descriptions
Bit 15 to 13 12 Description Reserved. Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period. Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output. Slave Select Input Enable. Set by user in master mode to enable the output. Cleared by user to disable master output. SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data. Transfer and Interrupt Mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full. LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. Reserved. Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode. SPI Enable Bit. Set by user to enable the SPI. Cleared by user to disable the SPI.
11 10 9 8 7 6 5 4 3 2 1 0
f serialclock =
where: fUCLK = clock before the clock divider. DIVH = the high period of the clock. DIVL = the low period of the clock. Thus, for 100 kHz operation, DIVH = DIVL = 0CF and for 400 kHz, DIVH = DIVL = 032 The I2CDIV register corresponds to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain the device IDs. The device compares the four I2C0IDx registers to the address byte. The seven most significant bits of either ID register must be identical to that of the seven most significant bits of the first address byte received to be correctly addressed. The LSB of the ID registers, the transfer direction bit, is ignored in the process of address recognition.
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Table 61. I2C0SSTA MMR Bit Descriptions
Bit 31 to 15 14 Value Description Reserved. These bits should be written as 0. START Decode Bit. Set by hardware if the device receives a valid START + matching address. Cleared by an I2C STOP condition or an I2C general call reset. Repeated START Decode Bit. Set by hardware if the device receives a valid repeated START + matching address. Cleared by an I2C STOP condition, a read of the I2CSSTA register, or an I2C general call reset. ID Decode Bits. Received Address Natched ID Register 0. Received Address Matched ID Register 1. Received Address Matched ID Register 2. Received Address Matched ID Register 3. Stop After Start and Matching Address Interrupt. Set by hardware if the slave device receives an I2C STOP condition after a previous I2C START condition and matching address. Cleared by a read of the I2C0SSTA register. General Call ID. No General Call. General Call Reset and Program Address. General Call Program Address. General Call Matching Alternative ID. General Call Interrupt. Set if the slave device receives a general call of any type. Cleared by setting Bit 8 of the I2CxCFG register. If it is a general call reset, then all registers are at their default values. If it is a hardware general call, then the Rx FIFO holds the second byte of the general call. This is similar to the I2C0ALT register (unless it is a general call to reprogram the device address). For more details, see I2C bus specification, version 2.1, Jan. 2000. Slave Busy. Set automatically if the slave is busy. Cleared automatically. No ACK. Set if master asking for data and no data is available. Cleared automatically by reading the I2C0SSTA register. Slave Receive FIFO Overflow. Set automatically if the slave receive FIFO is overflowing. Cleared automatically by reading the I2C0SSTA register. Slave Receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0SRX register or flushing the FIFO. Slave Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0STX register. Slave Transmit FIFO Underflow. Set automatically if the slave transmit FIFO is underflowing. Cleared automatically by writing to the I2C0SSTA MMR. Slave Transmit FIFO Empty. Set automatically if the slave transmit FIFO is empty. Cleared automatically by writing to the I2C0STX register.
I2CxMSTA Registers
Name I2C0MSTA I2C1MSTA Address 0xFFFF0800 0xFFFF0900 Default Value 0x00 0x00 Access R R
13
I2CxMSTA are status registers for the master channel. Table 60. I2C0MSTA MMR Bit Descriptions
Bit 7 Description Master Transmit FIFO Flush. Set by user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO. Master Busy. Set automatically if the master is busy. Cleared automatically. Arbitration Loss. Set in multimaster mode if another master has the bus. Cleared when the bus becomes available. No ACK. Set automatically if there is no acknowledge of the address by the slave device. Cleared automatically by reading the I2C0MSTA register. Master Receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0MRX register. Master Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0MTX register. Master Transmit FIFO Underflow. Set automatically if the master transmit FIFO is underflowing. Cleared automatically by writing to the I2C0MTX register. Master TX FIFO Empty. Set automatically if the master transmit FIFO is empty. Cleared automatically by writing to the I2C0MTX register. 12, 11 00 01 10 11 10
6 5 4
3 2 1
9, 8 00 01 10 11 7
I2CxSSTA Registers
Name I2C0SSTA I2C1SSTA Address 0xFFFF0804 0xFFFF0904 Default Value 0x01 0x01 Access R R
6 5
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I2CxSRX Registers
Name I2C0SRX I2C1SRX Address 0xFFFF0808 0xFFFF0908 Default Value 0x00 0x00 Access R R Name I2C0ADR I2C1ADR
I2CxSTX Registers
Name I2C0STX I2C1STX Address 0xFFFF080C 0xFFFF090C Default Value 0x00 0x00 Access W W
I2CxADR are master address byte registers. The I2CxADR value is the device address that the master wants to communicate with. It automatically transmits at the start of a master transfer sequence if there is no valid data in the I2CxMTX register when the master enable bit is set.
I2CxBYTE Registers
Name I2C0BYTE I2C1BYTE Address 0xFFFF0824 0xFFFF0924 Default Value 0x00 0x00 Access R/W R/W
I2CxMRX Registers
Name I2C0MRX I2C1MRX Address 0xFFFF0810 0xFFFF0910 Default Value 0x00 0x00 Access R R
I2CxMTX Registers
Name I2C0MTX I2C1MTX Address 0xFFFF0814 0xFFFF0914 Default Value 0x00 0x00 Access W W
I2CxBYTE are broadcast byte registers. Data written to these register do not go through the TxFIFO. This data is transmitted at the start of a transfer sequence before the address. Once the byte has been transmitted and acknowledged, the I2C expects another byte written in I2CxBYTE or an address written to the address register.
I2CxALT Registers
Name I2C0ALT I2C1ALT Address 0xFFFF0828 0xFFFF0928 Default Value 0x00 0x00 Access R/W R/W
I2CxCNT Registers
Name I2C0CNT I2C1CNT Address 0xFFFF0818 0xFFFF0918 Default Value 0x00 0x00 Access R/W R/W
I2CxCNT are 3-bit master receive data count registers. If a master read transfer sequence is initiated, then the I2CxCNT registers denote the number of bytes (1) to be read from the slave device. By default, this counter is 0, which corresponds to 1 byte expected.
I2CxCFG Registers
Name I2C0CFG I2C1CFG Address 0xFFFF082C 0xFFFF092C Default Value 0x00 0x00 Access R/W R/W
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Table 62. I2C0CFG MMR Bit Descriptions
Bit 31 to 15 14 13 12 11 10 9 Description Reserved. These bits should be written by the user as 0. Enable Stop Interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition + matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition. Reserved. Reserved. Enable Stretch SCL (Holds SCL Low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line. Reserved. Slave Tx FIFO Request Interrupt Enable. Set by the user to disable the slave Tx FIFO request interrupt. Cleared by the user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate action, taking interrupt latency into account. General Call Status Bit Clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general call status bits have been cleared. Master Serial Clock Enable Bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial clock in master mode. Loop Back Enable Bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate in normal mode. Start Back-Off Disable Bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit. Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit. Hardware General Call Enable. When this bit and the general call enable bit are set, and have received a general call (address 0x00) and a data byte, the device checks the contents of the I2C0ALT against the receive register. If they match, then the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a "to whom it may concern" call. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 watch for these addresses. The device that requires attention embeds its own address into the message. All masters listen and the master that knows how to handle the device contacts its slave and acts appropriately. The LSB of the I2C0ALT register should always be written to a 1, as per I2C January 2000 specification. General Call Enable Bit. Set this bit to enable the slave device to ACK an I2C general call, address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 as the data byte, Reset and write programmable part of slave address by hardware, then the I2C interface resets as per the I2C January 2000 specification. This command can be used to reset an entire I2C system. The general call interrupt status bit sets on any general call. It is up to the user to take correct action by setting up the I2C interface after a reset. If it receives a 0x04 as the data byte, Write programmable part of slave address by hardware, then the general call interrupt status bit sets on any general call. It is up to the user to take correct action by reprogramming the device address. Reserved. Master Enable Bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel. Slave Enable Bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence. Cleared by user to disable the slave I2C channel.
8 7 6 5 4
2 1 0
I2CxDIV Registers
Name I2C0DIV I2C1DIV Address 0xFFFF0830 0xFFFF0930 Default Value 0x1F1F 0x1F1F Access R/W R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address device ID registers of I2Cx.
I2CxCCNT Registers
Name I2C0CCNT I2C1CCNT Address 0xFFFF0848 0xFFFF0948 Default Value 0x01 0x01 Access R/W R/W
I2CxIDx Registers
Name I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 Address 0xFFFF0838 0xFFFF083C 0xFFFF0840 0xFFFF0844 0xFFFF0938 0xFFFF093C 0xFFFF0940 0xFFFF0944 Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W
I2CxCCNT are 8-bit start/stop generation counters. They hold off SDA low for start and stop conditions.
I2CxFSTA Registers
Name I2C0FSTA I2C1FSTA Address 0xFFFF084C 0xFFFF094C Default Value 0x0000 0x0000 Access R R
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Table 63. I2C0FSTA MMR Bit Descriptions
Bit 15 to 10 9 Value Description Reserved. Master Transmit FIFO Flush. Set by the user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO. Slave Transmit FIFO Flush. Set by the user to flush the slave Tx FIFO. Cleared automatically once the slave Tx FIFO is flushed. Master Rx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Master Tx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Slave Rx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Slave Tx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full.
7, 6 00 01 10 11 5, 4 00 01 10 11 3, 2 00 01 10 11 1, 0 00 01 10 11
PLAELMx Registers
Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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PLACLK Register
Address 0xFFFF0B40 Default Value 0x00 Access R/W
PLACLK is a clock selection for the flip-flops of Block 0 and clock selection for the flip-flops of Block 1. Table 66. PLACLK MMR Bit Descriptions
Bit 7 6 to 4 Value Description Reserved Block 1 Clock Source Selection GPIO Clock on P0.5 GPIO Clock on P0.0 GPIO Clock on P0.7 HCLK OCLK (32.768 kHz) Timer1 Overflow Reserved Reserved Block 0 Clock Source Selection GPIO Clock on P0.5 GPIO Clock on P0.0 GPIO Clock on P0.7 HCLK OCLK (32.768 kHz) Timer1 Overflow Reserved
4 to 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0
000 001 010 011 100 101 Other 3 2 to 0 000 001 010 011 100 101 Other
8 to 7
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PLAIRQ Register
Name PLAIRQ Address 0xFFFF0B44 Default Value 0x00000000 Access R/W 0000 0001 1111
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ. Table 68. PLAIRQ MMR Bit Descriptions
Bit 15 to 13 12 Value Description Reserved. PLA IRQ1 Enable Bit. Set by user to enable IRQ1 output from PLA. Cleared by user to disable IRQ1 output from PLA. PLA IRQ1 Source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 Enable Bit. Set by user to enable IRQ0 output from PLA. Cleared by user to disable IRQ0 output from PLA. PLA IRQ0 Source. PLA Element 0. PLA Element 1. PLA Element 15.
PLADIN Register
Name PLADIN Address 0xFFFF0B4C Default Value 0x00000000 Access R/W
PLADIN is a data input MMR for PLA. Table 70. PLADIN MMR Bit Descriptions
Bit 31 to 16 15 to 0 Description Reserved Input Bit to Element 15 to Element 0
PLADOUT Register
Name PLADOUT Address 0xFFFF0B50 Default Value 0x00000000 Access R
PLADOUT is a data output MMR for PLA. This register is always updated. Table 71. PLADOUT MMR Bit Descriptions
Bit 31 to 16 15 to 0 Name PLALCK Description Reserved Output Bit from Element 15 to Element 0 Address 0xFFFF0B54 Default Value 0x00 Access W
PLAADC Register
Name PLAADC Address 0xFFFF0B48 Default Value 0x00000000 Access R/W
PLAADC is a PLA source from the ADC start conversion signal. Table 69. PLAADC MMR Bit Descriptions
Bit 31 to 5 4 Value Description Reserved. ADC Start Conversion Enable Bit. Set by user to enable ADC start conversion from PLA. Cleared by user to disable ADC start conversion from PLA. ADC Start Conversion Source.
PLALCK Register
PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMR, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA.
3 to 0
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IRQSTA Register
Name IRQSTA Address 0xFFFF0000 Default Value 0x00000000 Access R
IRQSTA (read-only register) provides the current enabled IRQ source status. When set to 1 that source should generate an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. All 32 bits are logically ORed to create the IRQ signal to the ARM7TDMI core.
IRQSIG Register
Name IRQSIG Address 0xFFFF0004 Default Value 0x00XXX000 Access R
IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, then the corresponding bit in the IRQSIG is set; otherwise it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read-only.
IRQEN Register
Name IRQEN Address 0xFFFF0008 Default Value 0x00000000 Access R/W
IRQEN provides the value of the current enable mask. When bit is set to 1, the source request is enabled to create an IRQ exception. When bit is set to 0, the source request is disabled or masked, which does not create an IRQ exception.
IRQCLR Register
Name IRQCLR Address 0xFFFF000C Default Value 0x00000000 Access W
IRQCLR (write-only register) clears the IRQEN register in order to mask an interrupt source. Each bit set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, independently manipulates the enable mask without requiring an atomic read-modify-write.
FIQ
The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface providing the second-level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
IRQ
The interrupt request (IRQ) is the exception signal to enter the IRQ mode of the processor. It is used to service generalpurpose interrupt handling of internal and external events. The four 32-bit registers dedicated to IRQ are: IRQSTA, IRQSIG, IRQEN, and IRQCLR.
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FIQSTA Register
Name FIQSTA Address 0xFFFF0100 Default Value 0x00000000 Access R
FIQSIG Register
Name FIQSIG Address 0xFFFF0104 Default Value 0x00XXX000 Access R
FIQEN Register
Name FIQEN Address 0xFFFF0108 Default Value 0x00000000 Access R/W
FIQCLR Register
Name FIQCLR Address 0xFFFF010C Default Value 0x00000000 Access W
These four timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale and starts again at the minimum value. (It also increases from the minimum value until full scale and starts again at the maximum value.) In periodic mode, the counter decrements/increments from the value in the load register (TLD MMR) until zero/full scale and starts again at the value stored in the load register. The timer interval is calculated as follow:
Bit 31 to Bit 1 of FIQSTA are logically ORed to create the FIQ signal to the core and Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN does, as a side effect, clear the same bit in IRQEN. Also, a bit set to 1 in IRQEN does, as a side effect, clear the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks.
Interval =
( T LD ) prescaler
source clock
Programmed Interrupts
Because the programmed interrupts are nonmaskable, they are controlled by another register, SWICFG, which simultaneously writes into the IRQSTA and IRQSIG registers, and/or the FIQSTA and FIQSIG registers. The 32-bit register dedicated to software interrupt is SWICFG described in Table 73. This MMR allows the control of programmed source interrupt.
The value of a counter can be read at any time by accessing its value register (TVAL). Note that when a timer is being clocked from a clock other than core clock, an incorrect value could be read (due to asynchronous clock system). In this configuration, TVAL should always be read twice. If the two readings are different, then it should be read a third time to get the correct value. Timers are started by writing in the control register of the corresponding timer (TCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TCLRI). When using an asynchronous clock-to-clock timer, the interrupt in the timer block could take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared before leaving the interrupt service routine. This can be done by checking the IRQSTA MMR.
SWICFG Register
Name SWICFG Address 0xFFFF0010 Default Value 0x00000000 Access W
Note that any interrupt signal must be active for at least the equivalent of the interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register.
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T0CLRI Register
Name T0CLRI Address 0xFFFF030C Default Value 0xFF Access W
T0CLRI is an 8-bit register. Writing any value to this register clears the interrupt.
HCLK
TIMER0 VALUE
Timer1 is a general-purpose, 32-bit timer (count down or count up) with a programmable prescaler. The source can be the 32 kHz external crystal, the core clock frequency, or an external GPIO, P1.0 or P0.6. This source can be scaled by a factor of 1, 16, 256, or 32768. The counter can be formatted as a standard 32-bit value or as Hours: Minutes: Seconds: Hundredths. Timer1 has a capture register (T1CAP), which can be triggered by a selected IRQ source initial assertion. This feature can be used to determine the assertion of an event more accurately than the precision allowed by the RTOS timer when the IRQ is serviced. Timer1 can be used to start ADC conversions as shown in the block diagram in Figure 64.
32-BIT LOAD 32kHz OSCILLATOR HCLK P0.6 P1.0
Timer0s interface consists of four MMRS: T0LD, T0VAL, T0CON, and T0CLRI.
T0LD Register
Name T0LD Address 0xFFFF0300 Default Value 0x0000 Access R/W
T0VAL Register
Name T0VAL Address 0xFFFF0304 Default Value 0xFFFF Access R
T0VAL is a 16-bit read-only register representing the current state of the counter.
T0CON Register
Name T0CON Address 0xFFFF0308 Default Value 0x0000 Access R/W
IRQ[31:0] CAPTURE
T0CON is the configuration MMR described in Table 74. Table 74. T0CON MMR Bit Descriptions
Bit 31 to 8 7 6 Value Description Reserved. Timer0 Enable Bit. Set by user to enable Timer0. Cleared by user to disable Timer0 by default. Timer0 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode. Default mode. Reserved. Prescale. Core Clock/1. Default value. Core Clock/16. Core Clock/256. Undefined. Equivalent to 00. Reserved.
Timer1s interface consists of five MMRS: T1LD, T1VAL, T1CON, T1CLRI, and T1CAP.
T1LD Register
Name T1LD Address 0xFFFF0320 Default Value 0x00000000 Access R/W
5, 4 3, 2 00 01 10 11 1, 0
T1VAL Register
Name T1VAL Address 0xFFFF0324 Default Value 0xFFFFFFFF Access R
T1VAL is a 16-bit read-only register that represents the current state of the counter.
T1CON Register
Name T1CON Address 0xFFFF0328 Default Value 0x0000 Access R/W
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Table 75. T1CON MMR Bit Descriptions
Bit 31 to 18 17 Value Description Reserved. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event Event Select Range, 0 to 31. These events are as described in Table 72. All events are offset by two, that is, event 2 in Table 72 becomes event zero for the purposes of Timer1. Clock Select. Core Clock (HCLK). External 32.768 kHz Crystal. P1.0 Raising Edge Triggered. P0.6 Raising Edge Triggered. Count Up. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down by default. Timer1 enable bit. Set by user to enable Timer1. Cleared by user to disable Timer1 by default. Timer1 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode. Default mode. Format. Binary. Reserved. Hr:Min:Sec:Hundredths (23 hours to 0 hour). Hr:Min:Sec:Hundredths (255 hours to 0 hour). Prescale: Source Clock/1. Source Clock/16. Source Clock/256. Source Clock/32768.
T1CAP is a 32-bit register. It holds the value contained in T1VAL when a particular event occurred. This event must be selected in T1CON.
16 to 12
TIMER2 IRQ
Timer2 interface consists in four MMRS: T2LD, T2VAL, T2CON, and T2CLRI.
T2LD Register
Name T2LD Address 0xFFFF0340 Default Value 0x00000000 Access R/W
T1CLRI Register
Name T1CLRI Address 0xFFFF032C Default Value 0xFF Access W
T2VAL Register
Name T2VAL Address 0xFFFF0344 Default Value 0xFFFFFFFF Access R
T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
T2VAL is a 16-bit read-only register that represents the current state of the counter.
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16-BIT LOAD WATCHDOG RESET TIMER3 IRQ
04955-037
32.768kHz
T2CON is the configuration MMR described in Table 76. Table 76. T2CON MMR Bit Descriptions
Bit 31 to 11 10, 9 Value Description Reserved. Clock Source. External Crystal. External Crystal. Internal Oscillator. Core Clock (41 MHz/2CD). Count Up. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down by default. Timer2 Enable Bit. Set by user to enable Timer2. Cleared by user to disable Timer2 by default. Timer2 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode. Default mode. Format. Binary. Reserved. Hr:Min:Sec:Hundredths (23 hours to 0 hour). Hr:Min:Sec:Hundredths (255 hours to 0 hour). Prescale: Source Clock/1 by Default. Source Clock/16. Source Clock/256 Expected for Format 2 and 3. Source Clock/32768.
TIMER3 VALUE
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in T3CON MMR. Timer3 decreases from the value present in T3LD register until zero. T3LD is used as timeout. The maximum timeout can be 512 seconds using the prescaler/256, and full-scale in T3LD. Timer3 is clocked by the internal 32 kHz crystal when operating in the watchdog mode. Note that to enter watchdog mode successfully, Bit 5 in the T3CON MMR must be set after writing to the T3LD MMR. If the timer reaches 0, a reset or an interrupt occurs, depending on Bit 1 in T3CON register. To avoid reset or interrupt, any value must be written to T3ICLR before the expiration period. This reloads the counter with T3LD and begins a new timeout period. As soonas watchdog mode is entered, T3LD and T3CON are write-protected. These two registers cannot be modified until a reset clears the watchdog enable bit, which causes Timer3 to exit watchdog mode. The Timer3 interface consists of four MMRS: T3LD, T3VAL, T3CON, and T3CLRI.
00 01 10 11 8
7 6
T3LD Register
Name T3LD Address 0xFFFF0360 Default Value 0x0000 Access R/W
T2CLRI Register
Name T2CLRI Address 0xFFFF034C Default Value 0xFF Access W
T2CLRI is an 8-bit register. Writing any value to this register clears the Timer2 interrupt.
T3VAL Register
Name T3VAL Address 0xFFFF0364 Default Value 0xFFFF Access R
T3VAL is a 16-bit read-only register that represents the current state of the counter.
T3CON Register
Name T3CON Address 0xFFFF0368 Default Value 0x0000 Access R/W
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the clock source and the count-up functionality. The clock source is 32 kHz from the PLL and can be scaled by a factor of 1, 16, or 256 (see Figure 66).
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Table 77. T3CON MMR Bit Descriptions
Bit 31 to 9 8 Value Description Reserved. Count Up. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down by default. Timer3 Enable Bit. Set by user to enable Timer3. Cleared by user to disable Timer3 by default. Timer3 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode. Default mode. Watchdog Mode Enable Bit. Set by user to enable watchdog mode. Cleared by user to disable watchdog mode by default. Secure Clear Bit. Set by user to use the secure clear option. Cleared by user to disable the secure clear option by default. Prescale: Source Clock/1 by Default. Source Clock/16. Source Clock/256. Undefined. Equivalent to 00. Watchdog IRQ Option Bit. Set by user to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user to disable the IRQ option. Reserved.
3, 2 00 01 10 11 1
T3CLRI Register
Name T3CLRI Address 0xFFFF036C Default Value 0x00 Access W
T3CLRI is an 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode.
Q 7 CLOCK
Q 6
Q 5
Q 4
Q 3
Q 2
Q 1
Q 0
D
04955-038
There are four external memory regions available as described in Table 79. Associated with each region are the pins MS[3:0]. These signals allow access to the particular region of external memory. The size of each memory region can be 128 kB maximum, 64 k 16 or 128 k 8. To access 128 k with an 8-bit memory, an extra address line (A16) is provided. (See the example in Figure 68.) The four regions are configured independently. Table 79. Memory Regions
Address Start 0x10000000 0x20000000 0x30000000 0x40000000 Address End 0x1000FFFF 0x2000FFFF 0x3000FFFF 0x4000FFFF Contents External Memory 0 External Memory 1 External Memory 2 External Memory 3
The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3ICLR must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired.
Each external memory region can be controlled through three MMRs: XMCFG, XMxCON, and XMxPAR.
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XMxPAR Registers
Name XM0PAR XM1PAR XM2PAR XM3PAR Address 0xFFFFF020 0xFFFFF024 0xFFFFF028 0xFFFFF02C Default Value 0x70FF 0x70FF 0x70FF 0x70FF Access R/W R/W R/W R/W
XMxPAR are registers that define the protocol used for accessing the external memory for each memory region. Table 81. XMxPAR MMR Bit Descriptions
Bit 15 Description Enable Byte Write Strobe. This bit is only used for two, 8bit memory sharing the same memory region. Set by the user to gate the A0 output with the WR output. This allows byte write capability without using BHE and BLE signals. Cleared by user to use BHE and BLE signals. Number of wait states on the address latch enable strobe. Reserved. Extra Address Hold Time. Set by the user to disable extra hold time. Cleared by the user to enable one clock cycle of hold on the address in read and write. Extra bus transition time on read. Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before and after the read strobe (RS). Extra Bus Transition Time On Write. Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before and after the write strobe (WS). Number of Write Wait States. Select the number of wait states added to the length of the WS pulse. 0x0 is 1clock; 0xF is 16 clock cycles (default value). Number of Read Wait States. Select the number of wait states added to the length of the RS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default value).
WE OE
XMCFG Register
Name XMCFG Address 0xFFFFF000 Default Value 0x00 Access R/W
14 to 12 11 10
XMCFG is set to 1 to enable external memory access. This must be set to 1 before any port pins function as external memory access pins. The port pins must also be individually enabled via the GPxCON MMR.
XMxCON Registers
Name XM0CON XM1CON XM2CON XM3CON Address 0xFFFFF010 0xFFFFF014 0xFFFFF018 0xFFFFF01C Default Value 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W
7 to 4
3 to 0
XMxCON are the control registers for each memory region. They allow the enabling/disabling of a memory region and control the data bus width of the memory region. Table 80. XMxCON MMR Bit Descriptions
Bit 1 Description Selects Between 8-Bit and 16-Bit Data Bus Width. Set by the user to select a 16-bit data bus. Cleared by the user to select an 8-bit data bus. Enables Memory Region. Set by the user to enable memory region. Cleared by the user to disable the memory region.
Figure 69, Figure 70, Figure 71, and Figure 72 show the timing for a read cycle, a read cycle with address hold and bus turn cycles, a write cycle with address and write hold cycles, and a write cycle with wait sates, respectively.
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MCLK
AD16:0
ADDRESS
DATA
MSx
AE
RS
MCLK
AD16:0
DATA
MSx
AE
RS BUS TURN OUT CYCLE (BIT-9) BUS TURN OUT CYCLE (BIT-9)
04955-041
Figure 70. External Memory Read Cycle with Address Hold and Bus Turn Cycles
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ADDRESS
DATA
AE
WS WRITE HOLD ADDRESS AND DATA CYCLES (BIT-8) WRITE HOLD ADDRESS AND DATA CYCLES (BIT-8)
04955-042 04955-043
Figure 71. External Memory Write Cycle with Address and Write Hold Cycles
MCLK
AD16:0
ADDRESS
DATA
MSx
WS
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Notice that in both Figure 73 and Figure 74, a large value (10 F) reservoir capacitor sits on IOVDD, and a separate 10 F capacitor sits on AVDD. In addition, local small-value (0.1 F) capacitors are located at each AVDD and IOVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, note that the analog and digital ground pins on the ADuC7019/7020/7021/7022/ 7024/7025/7026/7027 must be referenced to the same system ground reference point at all times.
ADuC7026
26 54
73
IOVDD
0.1F
0.1F
25 53
IOGND
As an alternative to providing two separate power supplies, the user can reduce noise on AVDD by placing a small series resistor and/or ferrite bead between AVDD and IOVDD, and then decouple AVDD separately to ground. An example of this configuration is shown in Figure 74. With this configuration, other analog circuitry (such as op amps, voltage reference, and others) can be powered from the AVDD supply line as well.
DIGITAL SUPPLY + 10F BEAD 1.6 10F
0.47F
28 DGND
ADuC7026
26 54
73
IOVDD
The LVDD pin should not be used for any other chip. It is also recommended to use excellent power supply decoupling on IOVDD to help improve line regulation performance of the onchip voltage regulator.
0.1F
0.1F
25 53
IOGND
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For example, do not power components on the analog side, as seen in Figure 76b, with IOVDD because that would force return currents from IOVDD to flow through AGND. Also, avoid digital currents flowing under analog circuitry, which could occur if a noisy digital chip is placed on the left half of the board shown in Figure 76c. If possible, avoid large discontinuities in the ground plane(s) (such as those formed by a long trace on the same layer), because they force return signals to travel a longer path. In addition, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. When connecting fast logic signals (rise/fall time < 5 ns) to any of the ADuC7019/7020/7021/7022/7024/7025/7026/7027s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC7019/7020/ 7021/7022/7024/7025/7026/7027 input pins. A value of 100 or 200 is usually sufficient enough to prevent high speed signals from coupling capacitively into the part and affecting the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/7020/7021/7022/ 7024/7025/7026/7027 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.768 kHz parallel resonant crystal between XCLKI and XCLKO, and connect a capacitor from each pin to ground as shown Figure 77. This crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator is used to give a frequency of 41.78 MHz 3% typically.
XCLKI 12pF 32.768kHz
45
a.
AGND
DGND
ADuC7026
b.
12pF
XCLKO
AGND
DGND
To use an external source clock input instead of the PLL (see Figure 78), Bit 1 and Bit 0 of PLLCON must be modified.The external clock uses P0.7 and XCLK.
c.
PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE
XCLKO
04955-047
ADuC7026
DGND
XCLK
In all of these scenarios, and in more complicated real-life applications, pay particular attention to the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations.
Using an external clock source, the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027s specified operational clock speed
Rev. A | Page 85 of 93
04955-049
04955-048
44
TO INTERNAL PLL
ADuC7019/20/21/22/24/25/26/27
range is 50 kHz to 44 MHz 1% to ensure correct operation of the analog peripherals and Flash/EE.
IOVDD
2.35V TYP
2.6V
2.35V TYP
128ms TYP
P1.0
AGND
AVDD
ADC0
VREF
P1.1
ADM3202
1 2 3 4 5 6 7
GNDREF DAC0
ADuC7020
26
32.768kHz
IOGND
DGND
IOVDD
TRST
TDI
22
LVDD
TDO
TCK
10 P0.0
RST
21 20
1k DVDD DVDD
11
12
13
14
15
16
17
18
19
0.47F
100k
100k
100k
Rev. A | Page 86 of 93
04955-051
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DVDD
AVDD 1.5
DVDD
JTAG CONNECTOR
ADuC7019/20/21/22/24/25/26/27
Software
Integrated development environment, incorporating assembler, compiler, and nonintrusive JTAG-based debugger Serial downloader software Example code CD-ROM documentation
Miscellaneous
These systems consist of the following PC-based (Windows compatible) hardware and software development tools:
Hardware
ADuC7019/7020/7021/7022/7024/7025/7026/7027 evaluation board Serial port programming cable RDI compliant JTAG emulator (included in the ADuC7026 QuickStart Plus only)
Rev. A | Page 87 of 93
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
EXPOSED PAD
(BOTTOM VIEW)
21 20
12 MAX
SEATING PLANE
0.20 REF
COPLANARITY 0.08
Figure 81. 40-Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters
9.00 BSC SQ
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
33 32
16 17
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF
SEATING PLANE
Figure 82. 64-Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters
Rev. A | Page 88 of 93
112805-0
ADuC7019/20/21/22/24/25/26/27
12.00 BSC SQ
49 48
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
0.15 0.05
SEATING PLANE
16 17 32
33
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
VIEW A
Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
1.60 MAX
1
14.00 BSC SQ
80 61 60 PIN 1
(PINS DOWN)
TOP VIEW
12.00 BSC SQ
0.15 0.05
SEATING PLANE
20 21 40
41
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BDD
VIEW A
Figure 84. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters
Rev. A | Page 89 of 93
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ORDERING GUIDE
Model ADuC7019BCPZ62I1 ADuC7019BCPZ62I-RL1 ADuC7019BCPZ62IRL71 ADuC7020BCPZ621 ADuC7020BCPZ62-RL1 ADuC7020BCPZ62-RL71 ADuC7020BCPZ62I1 ADuC7020BCPZ62I-RL1 ADuC7020BCPZ62IRL71 ADuC7021BCPZ621 ADuC7021BCPZ62-RL1 ADuC7021BCPZ62-RL71 ADuC7021BCPZ62I1 ADuC7021BCPZ62I-RL1 ADuC7021BCPZ62IRL71 ADuC7021BCPZ321 ADuC7021BCPZ32-RL1 ADuC7021BCPZ32-RL71 ADuC7022BCPZ621 ADuC7022BCPZ62-RL1 ADuC7022BCPZ62-RL71 ADuC7022BCPZ321 ADuC7022BCPZ32-RL1 ADuC7022BCPZ32-RL71 ADuC7024BCPZ621 ADuC7024BCPZ62-RL1 ADuC7024BCPZ62-RL71 ADuC7024BSTZ621 ADuC7024BSTZ62-RL1 ADC Channels 52 52 52 5 5 5 5 5 5 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 10 10 10 10 2 2 2 2 2 DAC Channels 3 3 3 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 FLASH/RAM 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 32 kB/4 kB 32 kB/4 kB 32 kB/4 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 32 kB/4 kB 32 kB/4 kB 32 kB/4 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB 62 kB/8 kB PWM Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Single Three Phase Three Phase Three Phase Three Phase Three Phase GPIO 14 14 14 14 14 14 14 14 14 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 30 30 30 30 30 Downloader I2C I2C I2C UART UART UART I 2C I 2C I 2C UART UART UART I 2C I 2C I 2C UART UART UART UART UART UART UART UART UART UART UART UART UART UART Temperature Range 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LQFP 64-Lead LQFP Package Option CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-64-1 CP-64-1 CP-64-1 ST-64-2 ST-64-2
Rev. A | Page 90 of 93
ADuC7019/20/21/22/24/25/26/27
Downloader UART UART UART UART UART UART UART UART UART UART I2 C I2 C UART UART Temperature Range 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ 64-Lead LQFP 64-Lead LQFP 80-Lead LQFP 80-Lead LQFP 80-Lead LQFP 80-Lead LQFP 80-Lead LQFP 80-Lead LQFP ADuC7020 MiniKit ADuC7020 QuickStart Development System ADuC7024 QuickStart Development System ADuC7026 QuickStart Development System ADuC7026 QuickStart Plus Development System Package Option CP-64-1 CP-64-1 CP-64-1 CP-64-1 CP-64-1 CP-64-1 ST-64-2 ST-64-2 ST-80-1 ST-80-1 ST-80-1 ST-80-1 ST-80-1 ST-80-1
EVAL-ADuC7024QS
EVAL-ADuC7026QS
EVAL-ADuC7026QSP
1 2
Z = Pb-free part. One of the ADC channels is internally buffered. 3 Includes external memory interface.
Rev. A | Page 91 of 93
ADuC7019/20/21/22/24/25/26/27 NOTES
Rev. A | Page 92 of 93
ADuC7019/20/21/22/24/25/26/27
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04955-0-1/06(A)
Rev. A | Page 93 of 93