You are on page 1of 50

Lecture # 01

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011


2

http://lms.nust.edu.pk/ Key: EE803


Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan

Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

Mine On-going Projects & Research opportunities

Introduction

Introduction - Mine
4

PhD, The University of Manchester: Reconfigurable signal processing techniques for optical tomography

Area

Digital System Design for complex algorithms Digital Image Processing, Video Registration, Immersive Displays

Activities

Group Director : Vision Imaging & Signal Processing Research Group (VISPRO)
Head: Digital Systems & Signal Processing Knowledge Group (Summer 2009-2011) Ultra High Definition Panorama Generation & Rendering (Funded by ETRI Korea) Digital Image Calibration for Multi Projector Displays (Funded by Epic Technologies)

Projects

A Multi View Imaging (MVI) Processing Platform: Real Time Panoramic Mosaic Generation (Funded by ICT R&D Fund)
Have been part of the project Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0) with Dr. Nazar (Funded by ICT R&D Fund)

VISpro: Vision Imaging & Signal Processing Research Group

VISpro
Current Research Projects by various members
UHD Panorama & Rendering (ETRI) Digital Image Calibration for Multi-Projector System (EPICTechnologies) Multi View Imaging Object Tracking & Tagging (Silicon Valley Company) Texture Analysis based Population Estimation (HEC Funded) Pico-Projection Systems

Total Research Grants: 21 Million (PKR)

Dr. Rehan Hafiz (Lead) Dr. M. Murtaza Dr. Hammad Qureshi (DOC) Dr. Shahzad (CSE) Dr. Khawer Khurshid

Collaborations ETRI Korea EPIC Technologies Computer Vision LAB, LUMS Image Processing Research Group, Warwick
5

http://vispro.seecs.nust.edu.pk/

Research Opportunities 2010


VISpro -- Multi-View Imaging (MVI)

MVI: Videos acquired from multiple video sources Enormous video data Enormous information Enormous applications

Multimedia/ Surveillance/ Inspection Immersive Multimedia Applications Sports/ Cricket Match Video Conferencing
Camera-1 Camera-2

Research Theme

Real Time Panoramic View Generation Real Time View Point Generation

I(x,y) T(x,y)

I`(x,y)
Overlapping region

Opportunities
7

Volunteer RA-Ship Do explore research groups at SEECS Try out before your thesis begins

Introduction-Aims
8

Name Area of interest Where u see yourself in future


Industry

? Academia ? Research ? Development ? Any where else ?

What you expect to learn in this couse ?

ADSD Fall 2011 Course Description

Relevant Books
10

(Sho.) Digital Design of Signal Processing Systems (Cil.) Advanced Digital Design with the Verilog HDL, M D. Ciletti

(Stv) Advanced FPGA Design, Steve Kilts

Useful Books
11

Verilog HDL, Samir Palnitkar Synthesis of Arithmetic Circuits VLSI Signal Processing Systems, Parhi

Course Evolution
ADSD-Fall-2009 Course outline
12

Introduction

Digital design methodology (Cil.)

Architectures for Arithmetic Processors (Cil.)


Combinational & Sequential Logic (Cil.)


Adders, Multipliers, Dividers Coordinate Rotation Digital Computer (CORDIC Algorithm)

Common structures HDL review Synthesis

Advanced FPGA Design Concepts (Stv.)


Design & Synthesis of Datapath controllers (Cil.)

Architecting Speed, Area & Power Clock Domains Reset Circuits Coding for synthesis Timing Analysis

Micro-Architecture

Fixed point & Floating point Arithmetic

ADSD Fall 2011 Course Outline


Week 1 Topic Introduction Description/ Lecture Breakdown Outline & Introduction Initial Assessment of students Digital design methodology & design flow Verilog+ Combinational Logic Review + Verilog Introduction Combinational Logic Combinational Building Blocks in Verilog
Verilog + Sequential Logic Synthesis in Verilog Micro-Architecture Optimizing Speed Optimizing Area Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS) Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements Design Partitioning + RISC Microprocessor + Micro architecture Document Architecting Speed in Digital System Design: [Throughput, Latency, Timing] Architecting Area in Digital System Design: [Area Optimization]

2 3 4 5 6 7 8 9

FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs MID EXAM

ADSD Fall 2011 Course Outline


Week Topic 10 CDC Issues
11 12 13 Fixed-Point Arithmetic Adders Multipliers

Description/ Lecture Breakdown Cross-Clock Domain Issues & RESET circuits


Arithmetic Operations: Review Fixed Point Representation Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers

13
14

CORDIC
Algorithmic Transformations for System Design Algorithmic Transformations for System Design Project Project

15

CORDIC (sine, cosine, magnitude, division, etc) CORDIC implementation in HW DFG representation of DSP Algorithms Iteration Bound Retiming Unfolding Look ahead transformations
Course Review & Project Presentations Project Presentations

16 17

18

END SEMESTER EXAM

Distribution
15

Quizzes Assignment Research Project Mid Final

10% 10% 15% 30% 35%

*There can be slight modifications & shall be notified earlier

Furthermore
16

After successful completion of this course the students shall be able to port complex algorithms to hardware by designing efficient data-paths and controllers; handle cross clock domain issues and shall have the desired knowledge to design for meeting specifications (speed, logic optimization).

The related relevant courses in your stream are:


ASIC Design Methodology Advanced VLSI System Design

The course has NO associated LAB credit hours. However, interested students can contact.

Relevant Conferences
17

IEEE International Symposium on Circuits and Systems ISCAS DATE - Design, Automation, and Test in Europe IEEE Symposium on Computer Arithmetic ISCA Applied Reconfigurable Computing ARC Engineering of Reconfigurable Systems and Algorithms ERSA Design Automation Conference DAC International Symposium on High-Performance Computer Architecture - HPCA

Relevant Journals
18

IEEE Transactions on Circuits and Systems for Video Technology TCSV IEEE Transactions on Very Large Scale Integration Systems VLSI ACM Transactions on Architecture and Code Optimization TACO Journal of Systems Architecture - Elsevier Microprocessors and Microsystems Elsevier Journal of Signal Processing Systems - Springer AIP Review Scientific Instruments ACM Transactions on Design Automation of Electronic Systems (TODAES)

Relevant Links
19

Verilog Tutorial

http://www.asic-world.com/verilog/veritut.html
http://www1.cs.columbia.edu/~hgs/etc/writing-style.html

Writing Technical Paper

20

Class Ethics

Class Ethics &.. Other stuff


21

Attendance Respect for all & classroom discipline Quizzes

Anytime

Never cheat

Better fail NOW or else will fail sometime LATER in life

Hard work always pays. Assignments

References (IEEE Indexing [1],[2],) No copying

Plagiarism

PLAGIARISM

22

Adapted from What is Plagiarism PowerPoint http://mciu.org/~spjvweb/plagiarism.ppt

Sir jeeby chance we had the same variable name 23

Oh ! I forgot to replace-all the variable names..

Questions.

25

Assessment Status quo Where we stand?

Lecture # 01

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

27

Design Space Exploration


More & Powerful design options are getting available to the developer. Design Space Options : GPPs, DSPs, FPGAs, Application Specific Processors,ASICs Design Space Exploration deals with deciding the best from the available options for the design.

For Further Reading : [SHO] Chapter-1

Moores Law (1965) is fueling the DSP Market


28

The number of transistors on a chip was doubling every 18 to 24 months and made the prediction for future 32nm => Sandy Bridge (2011) 11 nm => approx. 2015

More & Powerful Design Options are now available

[SHO]

Design Options
29

Programmable Processors (& Microcontrollers)

Programming flexibility Optimized - Architectures with so much design effort put in their designs Examples: Intel, Atmel, ARM Processors Programming flexibility Optimized - Architectures with so much design effort put in their designs Examples: DSP from Texas Instruments Reconfigurable Hardware Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design, e.g Unfied Serial Bus Controller for USB 3 PCI Expres 3.0 Also offer: Soft Processors [Microblaze, NIOS] Lower cost, low power No flexibility of programming Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design

Digital Signal Processors


FPGA

ASIC

Design Space Options


30

[SHO]

Design Decision depends on the nature & complexity of applications


31

Applications are characterized by amount of data, parallelism, real time requirements.

Analyzing your application for design space exploration


32

Computationally intensive (number crunching) tasks

Standard Tasks/Protocols/Interfaces/Encoding

Commercial off the shelf ASICs are available Memory Controllers, Firewire interfaces
Consist of code that has loops or nested loops with a few instructions being repeated a number of times. Suitable for FPGAs Examples: FFT Butterflies More Code intensive & complex to port to H/W. Suitable for DSPs Adaptive Algorithms with multiple IF/Else such as Motion Vector Estimation

Non Standard Structured Tasks


Non Standard Non Structured Tasks


Control Oriented Tasks


User interfaces, control processes, system controllers and other code intensive protocols are usually mapped on GPPs or microcontrollers. Multiple interrupts & Complex Scheduling are conveniently handled by Operating Systems so better handled by instruction based Processors

A typical system
33

For complex systems HW/SW co design may be the only optimal choice.

Soft processors like NIOS even allow you to make custom instructions ! Use a processor with FPGA/SICS as Hardware Accelerators

A little exercise
34

http://www.openmoko.com/freerunner.html

Display- 480 x 640 pixels, VGA, resistance type touch


User Interface Navigation- Touch screen on LCD, 2 control buttons, 1 Power button, 1 Aux for 911 emergency call

Wifi, Bluetooth,
Supports camera & JPEG compression Built-in GPS Radio Need support to run Mobile Applications What components you shall be using for your system ? Group of 3 On a paper & submit

An examples
35

Good Resources Must Read


36

Where are we focusing


37

Digital Design Methodology


38

From concept to reality


A

long tiring process

http://nigamanth.net/vlsi/category/asic-design-flow/

Design Methodology: Big Picture


MRD Marketing Requirement 39 Document Arch. Spec. (Macro Architecture) Design SpecificationMicro -Architecture & Design Partition

Design Entry HDL

Pre synthesis Sign-Off

Design Integration & Verification

Functional Verification

Simulation

Synthesize & Map Gate-Level Netlist

Post synthesis Design Verification

Test Generation & Fault Generation

Clock Trees Cell Routing

Design Sign-Off

Extract Parasitic

Verify Physical & Electrical Design Rules

Design Methodology
Marketing Requirement Document (MRD)

Architecture Specification Macro Architecture

A list of desirable features Studies


Customers expectations Competing Products Add-ons Market opportunities Time to market Projects revenue estimates Profit Margins

Architecture at a very high and abstract level Usually a transaction level model (TLM) Defines communicating processes Events may not be defined

Evaluation

Sample Architecture
41

Architectural Spec : Another Example.

Design Methodology
Design Spec/Micro Architecture / Design Partition

Going deeper into design Partitioning of functions into blocks Clock/reset requirements, Pipelining of registers Memory buffers Algorithm State Machines (like flowcharts) State machines and interface details. State Transition Graphs Timing Charts

FUs defined by their behavior

Interacting functional units Control vs. datapath separation Interconnection structures within datapath Top-down design method Exploiting hierarchy Design Reuse
This document is very crucial, for a large team working on various modules of the same design.

Design Methodology
Design Entry/ HDL
44

Simulation and Functional Verification

HDL

Higher productivity than schematic based gate level implementation Easier to Debug, Modify & Update De-burdens gate level optimizations Allows this stage to be technology independent (e.g., FPGA LUTs or ASIC standard cell libraries)

Simulation vs. Formal Methods Test Plan Development


What to test & how ? E.g: Instruction set for a range of data Testing of independent modules

Testbench Development

Behavioral descriptions

Test Execution and Model Verification

Meets Specification ?

Design Methodology
Design Integration and Verification
45

Pre synthesis sign-off

Integrate Bugs lurking in the interface behavior among modules The Testbench
I/O

Full functionality Demonstrated Make sure that the behavior specification meets the design specification

interfacing with top level module Monitor port & bus activity across module boundaries

Design Methodology
Gate-Level Synthesis and Technology Mapping
46

Post-synthesis Design Validation

Synthesize the design from the behavior description Optimized Boolean description Map onto target technology Optimizations

Minimize logic Reduce area Reduce power Balance speed vs. other resources consumed

Comparing Synthesized gatelevel description to the verified behavioral model A testbench that instantiates both models & drive them via common stimulus

Produces netlist of standard cells or database to configure target FPGA

Design Methodology
Post synthesis Timing Verification Are the timing specifications met? Are the speeds adequate on the critical paths? Re-synthesis may be required to achieve timing goals
47

ASIC Specific

Test Generation and Fault Simulation Placement and Routing

Clock distribution trees to minimize skew

Resize

transistors Modify architecture Choose a different target device or technology

Physical and Electrical Design Rule Check Determining Parastics Extract geometric information

Design Methodology: Big Picture


MRD Marketing Requirement 48 Document Arch. Spec. (Macro Architecture) Micro-Architecture & Design Partition

Design Entry HDL

Pre synthesis Sign-Off

Design Integration & Verification

Functional Verification

Simulation

Synthesize & Map Gate-Level Netlist

Post synthesis Design Verification

Test Generation & Fault Generation ASIC Specific

Clock Trees Cell Routing

Design Sign-Off

Extract Parasitic

Verify Physical & Electrical Design Rules

Reading Assignment
49

Relevant sections of Chapter-1 [SHO]

Questions.

You might also like