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<rehan.hafiz@seecs.edu.pk>
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library
Introduction
Introduction - Mine
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PhD, The University of Manchester: Reconfigurable signal processing techniques for optical tomography
Area
Digital System Design for complex algorithms Digital Image Processing, Video Registration, Immersive Displays
Activities
Group Director : Vision Imaging & Signal Processing Research Group (VISPRO)
Head: Digital Systems & Signal Processing Knowledge Group (Summer 2009-2011) Ultra High Definition Panorama Generation & Rendering (Funded by ETRI Korea) Digital Image Calibration for Multi Projector Displays (Funded by Epic Technologies)
Projects
A Multi View Imaging (MVI) Processing Platform: Real Time Panoramic Mosaic Generation (Funded by ICT R&D Fund)
Have been part of the project Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0) with Dr. Nazar (Funded by ICT R&D Fund)
VISpro
Current Research Projects by various members
UHD Panorama & Rendering (ETRI) Digital Image Calibration for Multi-Projector System (EPICTechnologies) Multi View Imaging Object Tracking & Tagging (Silicon Valley Company) Texture Analysis based Population Estimation (HEC Funded) Pico-Projection Systems
Dr. Rehan Hafiz (Lead) Dr. M. Murtaza Dr. Hammad Qureshi (DOC) Dr. Shahzad (CSE) Dr. Khawer Khurshid
Collaborations ETRI Korea EPIC Technologies Computer Vision LAB, LUMS Image Processing Research Group, Warwick
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http://vispro.seecs.nust.edu.pk/
MVI: Videos acquired from multiple video sources Enormous video data Enormous information Enormous applications
Multimedia/ Surveillance/ Inspection Immersive Multimedia Applications Sports/ Cricket Match Video Conferencing
Camera-1 Camera-2
Research Theme
Real Time Panoramic View Generation Real Time View Point Generation
I(x,y) T(x,y)
I`(x,y)
Overlapping region
Opportunities
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Volunteer RA-Ship Do explore research groups at SEECS Try out before your thesis begins
Introduction-Aims
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Relevant Books
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(Sho.) Digital Design of Signal Processing Systems (Cil.) Advanced Digital Design with the Verilog HDL, M D. Ciletti
Useful Books
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Verilog HDL, Samir Palnitkar Synthesis of Arithmetic Circuits VLSI Signal Processing Systems, Parhi
Course Evolution
ADSD-Fall-2009 Course outline
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Introduction
Architecting Speed, Area & Power Clock Domains Reset Circuits Coding for synthesis Timing Analysis
Micro-Architecture
2 3 4 5 6 7 8 9
FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs MID EXAM
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CORDIC
Algorithmic Transformations for System Design Algorithmic Transformations for System Design Project Project
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CORDIC (sine, cosine, magnitude, division, etc) CORDIC implementation in HW DFG representation of DSP Algorithms Iteration Bound Retiming Unfolding Look ahead transformations
Course Review & Project Presentations Project Presentations
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Distribution
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Furthermore
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After successful completion of this course the students shall be able to port complex algorithms to hardware by designing efficient data-paths and controllers; handle cross clock domain issues and shall have the desired knowledge to design for meeting specifications (speed, logic optimization).
The course has NO associated LAB credit hours. However, interested students can contact.
Relevant Conferences
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IEEE International Symposium on Circuits and Systems ISCAS DATE - Design, Automation, and Test in Europe IEEE Symposium on Computer Arithmetic ISCA Applied Reconfigurable Computing ARC Engineering of Reconfigurable Systems and Algorithms ERSA Design Automation Conference DAC International Symposium on High-Performance Computer Architecture - HPCA
Relevant Journals
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IEEE Transactions on Circuits and Systems for Video Technology TCSV IEEE Transactions on Very Large Scale Integration Systems VLSI ACM Transactions on Architecture and Code Optimization TACO Journal of Systems Architecture - Elsevier Microprocessors and Microsystems Elsevier Journal of Signal Processing Systems - Springer AIP Review Scientific Instruments ACM Transactions on Design Automation of Electronic Systems (TODAES)
Relevant Links
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Verilog Tutorial
http://www.asic-world.com/verilog/veritut.html
http://www1.cs.columbia.edu/~hgs/etc/writing-style.html
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Class Ethics
Anytime
Never cheat
Plagiarism
PLAGIARISM
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Questions.
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Lecture # 01
<rehan.hafiz@seecs.edu.pk>
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The number of transistors on a chip was doubling every 18 to 24 months and made the prediction for future 32nm => Sandy Bridge (2011) 11 nm => approx. 2015
[SHO]
Design Options
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Programming flexibility Optimized - Architectures with so much design effort put in their designs Examples: Intel, Atmel, ARM Processors Programming flexibility Optimized - Architectures with so much design effort put in their designs Examples: DSP from Texas Instruments Reconfigurable Hardware Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design, e.g Unfied Serial Bus Controller for USB 3 PCI Expres 3.0 Also offer: Soft Processors [Microblaze, NIOS] Lower cost, low power No flexibility of programming Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design
FPGA
ASIC
[SHO]
Standard Tasks/Protocols/Interfaces/Encoding
Commercial off the shelf ASICs are available Memory Controllers, Firewire interfaces
Consist of code that has loops or nested loops with a few instructions being repeated a number of times. Suitable for FPGAs Examples: FFT Butterflies More Code intensive & complex to port to H/W. Suitable for DSPs Adaptive Algorithms with multiple IF/Else such as Motion Vector Estimation
User interfaces, control processes, system controllers and other code intensive protocols are usually mapped on GPPs or microcontrollers. Multiple interrupts & Complex Scheduling are conveniently handled by Operating Systems so better handled by instruction based Processors
A typical system
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For complex systems HW/SW co design may be the only optimal choice.
Soft processors like NIOS even allow you to make custom instructions ! Use a processor with FPGA/SICS as Hardware Accelerators
A little exercise
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http://www.openmoko.com/freerunner.html
Wifi, Bluetooth,
Supports camera & JPEG compression Built-in GPS Radio Need support to run Mobile Applications What components you shall be using for your system ? Group of 3 On a paper & submit
An examples
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http://nigamanth.net/vlsi/category/asic-design-flow/
Functional Verification
Simulation
Design Sign-Off
Extract Parasitic
Design Methodology
Marketing Requirement Document (MRD)
Architecture at a very high and abstract level Usually a transaction level model (TLM) Defines communicating processes Events may not be defined
Evaluation
Sample Architecture
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Design Methodology
Design Spec/Micro Architecture / Design Partition
Going deeper into design Partitioning of functions into blocks Clock/reset requirements, Pipelining of registers Memory buffers Algorithm State Machines (like flowcharts) State machines and interface details. State Transition Graphs Timing Charts
Interacting functional units Control vs. datapath separation Interconnection structures within datapath Top-down design method Exploiting hierarchy Design Reuse
This document is very crucial, for a large team working on various modules of the same design.
Design Methodology
Design Entry/ HDL
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HDL
Higher productivity than schematic based gate level implementation Easier to Debug, Modify & Update De-burdens gate level optimizations Allows this stage to be technology independent (e.g., FPGA LUTs or ASIC standard cell libraries)
What to test & how ? E.g: Instruction set for a range of data Testing of independent modules
Testbench Development
Behavioral descriptions
Meets Specification ?
Design Methodology
Design Integration and Verification
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Integrate Bugs lurking in the interface behavior among modules The Testbench
I/O
Full functionality Demonstrated Make sure that the behavior specification meets the design specification
interfacing with top level module Monitor port & bus activity across module boundaries
Design Methodology
Gate-Level Synthesis and Technology Mapping
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Synthesize the design from the behavior description Optimized Boolean description Map onto target technology Optimizations
Minimize logic Reduce area Reduce power Balance speed vs. other resources consumed
Comparing Synthesized gatelevel description to the verified behavioral model A testbench that instantiates both models & drive them via common stimulus
Design Methodology
Post synthesis Timing Verification Are the timing specifications met? Are the speeds adequate on the critical paths? Re-synthesis may be required to achieve timing goals
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ASIC Specific
Resize
Physical and Electrical Design Rule Check Determining Parastics Extract geometric information
Functional Verification
Simulation
Design Sign-Off
Extract Parasitic
Reading Assignment
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Questions.