Lecture # 03

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011

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http://lms.nust.edu.pk/ Key: EE803

Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan

Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010 Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

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Introduction Verilog+ Combinational Logic Verilog + Sequential Logic Synthesis in Verilog

Outline & Introduction, Initial Assessment of students, Digital design methodology & design flow Combinational Logic Review + Verilog Introduction, Combinational Building Blocks in Verilog Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS), Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements

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Micro-Architecture
Optimizing Speed

Design Partitioning + RISC Microprocessor + Micro architecture Document

Architecting Speed in Digital System Design: [Throughput, Latency, Timing]

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8

Optimizing Area
FIR Implementation

Architecting Area in Digital System Design: [Area Optimization]

FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs

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11

CDC Issues
Fixed-Point Arithmetic

Cross-Clock Domain Issues & RESET circuits

Arithmetic Operations: Review Fixed Point Representation

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Adders Multipliers CORDIC

Algorithmic Transformations for System Design Algorithmic Transformations for System Design Project Project

Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW
DFG representation of DSP Algorithms, Iteration Bound & Retiming Unfolding Look ahead transformations Course Review & Project Presentations Project Presentations

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Suggested Reading
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Sequential Logic
Section 3.1-3.3

Sequential Logic Using Verilog - Review

digital circuits that have memory/storage .the output is dependent not only on the present inputs, but also on past inputs;

Why avoid latches ?

Storage Elements
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SR Latch Non Transparent D-Latch D-Latch (Transparent)

Edge Triggered D Flip Flop

Register

Latches Level sensitive storage elements

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NOR
0 0 1 1 x 0

Feedback structure of cross coupled Nor/Nand Gates Two Stable outputs depending on S & R Note: Q & Q are not logical complements Problem
When S=R=1 Transition from 11 to 00 causes race condition (oscillations)

SR Latch

Why avoid latches ?

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NOR 0 0 1 1 x 0 1

0 0

0
0

1 1 Prev. Values 1 0 0 0

1 0 0 0 0 1

1
1 0 1 0 0 0 0 1

0
1 0

0
0 1

1
0 0

0 0 1

Ideally the oscillations never stop Practically due to gate delays oscillations will come to halt

Race Condition Oscillations

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0 0

0 1

0 0 1

1 0 0

Q Q Assignment: Simulate the SR latch with different gate delays (2 different cases). Apply a sequence of SR values to demonstrate the race condition. Case a: Equal Gate Delays Case b: Experiment with such a value of gate that demonstrates how the oscillation may end due to different gat delays LMS + Print of timing diagrams http://www.verilogtutorial.info/chapter_2.htm

A solution Non Transparent D-Latch

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Gate delays can still cause race condition (S=R=1)

A Transparent D-Latch or simply D-Latch

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Non Transparent:

Data input

Reset input connected with inverted Data (Set) input Gate delays can still cause race condition (S=R=1) Latch is transparent to input only when Enable is set

Transparent

So what's the problem now ?

D

S D=R

En

When to set enable ??

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An enable signal that pulses at a constant rate

The

Clock Signal
elements that can update value only at a

Synchronous Sequential Circuit

Storage

clock

Asynchronous Sequential Circuit

A

sequential circuit (or storage element) that does not uses clock

So now we have a synchronous enable Clock Any problem now ?

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D E

D E

D E

D E

Clk

How many D-Latches the data will pass through --- while the clock is high
Clk-A Clk-B

Solution : D-Flip Flop Edge Triggered

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Storage Elements Review

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SR Latch
Race Conditions

Simple D-Latch
Gate delays can still cause race condition

Transparent D-Latch
Defining the length of enable signal

Edge Triggered D Flip Flop

The MOST used storage element

Register
Multiple parallel D Flip Flops

D Latch in Verilog
(Asynchronous Sequential Logic)
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module d_latch ( input E, input DATA, output reg Q, ); always @ (E or DATA) begin if (E == 1'b1) Q <= DATA; end // End Latch endmodule

D Latch in Verilog with Asynchronous Reset

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module d_latch ( input E, input reset, input DATA, output reg Q, ); always @ (E or DATA or rst_n) Begin if (~rst_n) begin Q<= 1b0 end else if (E == 1'b1) begin Q <= DATA; end end // End Latch endmodule

Active Low Reset Available in most technology libraries

Most logic families can sink more current than they can source, so fanout issues increases with active high resets !

D Flip Flop in Verilog Synchronous Sequential Logic

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module d_register
( input CLK, input DATA, output Q, reg Q ); always @ (posedge CLK) begin: Q <= DATA; end endmodule

D Flip Flop in Verilog

Synchronous & Asynchronous Resets
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(Always use reset with feedback registers)

module d_register (rst_n, CLK, DATA, Q); input CLK, DATA, rst_n; output reg Q; always @ (posedge CLK) begin: if (rst_n == 1b0) Q <= 1b0; else Q <= DATA; end endmodule module d_register (rst_n, CLK, DATA, Q); input CLK, DATA, rst_n; output reg Q; always @ (posedge CLK or negedge rst_n) begin: if (rst_n == 1b0) Q <= 1b0; else Q <= DATA; end endmodule

Rule for sensitivity list: When one item in the list has an edge qualifier all items in the list must have edge qualifie as well

Generating Clock in stimulus

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Clock is not a normal signal Not to be treated like a normal reg/wire Code

timescale 1ns/1ns define PERIOD 5 // 100MHz clock reg clk; initial clk = 1b0; always @ (clk) #PERIOD clk = ~clk; initial #1000 $finish;

Example : `timescale 1 ns / 10 ps

Indicates delays are in 1 nanosecond units with 2 decimal points of precision (10 ps is .01 ns).

The Verilog hardware description language, Volume 1 By Donald E. Thomas, Philip R. Moorby
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Generating RESET in stimulus

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We must reset all the feedback registers in the design. Example Code
Reset

(active low) the system after 5 time units:

initial begin

rst_n = 1b0; # 5 rst_n = 1b1; end

Coding Guideline
ALWAYS RESET Feedback Registers else there shall be uncertainties in your design !

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[SHO]

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Instantiating Memory Elements

Block RAM Vs. Distributed RAM

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Distributed RAM

Custom Memories created using LUT (for Xilinx) Good for storing small amounts of data, making registers, shift registers, etc. Dedicated, configurable memory with address, data, and control ports. For large data storage
For larger memory; MUST use BRAM else the synthesizer will consume logic area of FPGA meant for your actual LOGIC design.

Block RAM

TIP

Example: BRAM in Xilinxs Virtex-4 FPGAs

Consists of 16 kbits, blocks (16k single bits, 8k 2 bit words, up to 512 36-bit words) Blocks can be chained together to form large memories

Register File
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We need to have an addressable Register File May be synthesized as Flip Flops or Distributed RAM Depending standard or non-standard accessing ! Not used for mass storage because they occupy significantly more silicon area than compiled memory
Look

for on-chip resources (Xilinx Block RAM & Distributed RAM)

Register File Synthesis

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Example: 5.47 [CIL]

Remember Verilog 2001 allows Multi-Dimentional Arrays

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Xilinx allows supports upto 3D arrays Declaring 3D array

////////////////

3 D Array reg [7:0] d [0:3][0:1][0:1];

Accessing 3D Array
d[i1][i2][i3]

<= data; e <= d[3][1][0][3:0];

http://www.sutherland-hdl.com/papers/2000HDLCon-paper_Verilog-2000.pdf

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Blocking vs. Non Blocking Statements

Always Block

Non Blocking Statement

Concurrent procedural assignments - Do not block the procedural flow Behaviour of every statement needs to be implemented independently in parallel Use -- whenever you want to make several parallel register assignments within the same 31 time step without regard to order or dependence upon each other Dependencies define the connectivity - only !

module blockingnonblocking ( output reg out, input clk, in1, in2, in3); reg logicfun;

always @(posedge clk) begin logicfun <= in1 & in2; out <= logicfun | in3; end endmodule

In the implementation shown in Figure 12.9,both the signals logicfun and out are ip-ops, and any changes on in1 or in2 will take two clock cycles to propagate to out.

Blocking Statement

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Future operations are blocked until current operation has been completed. Behaviour: All future operations are under the assumption that all previous operations have completed and all variables have been updated

Dependencies define the number of registers inferred

module blockingnonblocking ( output reg out, input clk, in1, in2, in3); reg logicfun; always @(posedge clk) begin logicfun = in1 & in2; out = logicfun | in3; end endmodule There is a dependency. out will not be updated until logicfun has been updated, and both updates must occur on one event of the clock & this is a confusing style of coding Do Not Do This !

Blocking Statement

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Future operations are blocked until current operation has been completed. Behaviour: All future operations are under the assumption that all previous operations have completed and all variables have been updated

Dependencies define the number of registers inferred

module blockingnonblocking ( output reg out, input clk, in1, in2, in3); reg logicfun; always @(posedge clk) begin out = logicfun | in3; logicfun = in1 & in2; end endmodule There is no dependency within the always block !

we force the out register to be updated before logicfun, which forces a 2-clock cycle delay for the inputs in1 and in2 to propagate to out.

Some more Examples

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always @ (posedge c) Begin p <= a ; x <= q ; q <= p ; end

always @ (b,r,c) Begin r=b; s=r; z=s; end

Posedge/negedge clk is must for generating registers Blocking statements CAN result into registers if used with edge triggered clock BUT Blocking statements SHOULD NOT be used for generating sequential logic In blocking statements order is important
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always @ (b) Begin z = b; end always @ (posedge c) Begin z = b; end always @ (posedge c) Begin r = b; s=r; z = s; end always @ (posedge c) Begin r = b; z = s; s=r; end

Confusing Very Simple Way out ?????

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Use blocking assignments to model combinatorial logic Use non-blocking assignments to model sequential logic (Also Latches) Never mix blocking and non-blocking assignments in one always block Think HARDWARE

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More Sequential Circuits

This Lecture
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LFSR Linear Feedback Shift Register

RTL Example: shift Register

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Data_in
D Q D Q D Q D Q

Data_out

clock reset

module Shift_reg4 ( output Data_out, input Data_in, input clock, input reset); reg [3: 0] Data_reg; assign Data_out = Data_reg[3]; always @ (negedge reset or posedge clock) begin if (reset == 1'b0) Data_reg <= 4'b0; else Data_reg <= {Data_reg[2:0], Data_in}; end endmodule

LFSR Linear Feedback Shift Register

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Efficient design for

One to Many Test Pattern Generators / Output Response Analyzers is better over Data Encryption Many to One Considered efficient than counters High Speed Memory Addressing when order is not important !

Loaded with pre-defined values on reset

Fig:4-2: A designer's guide to built-in self-test---- By Charles E. Stroud

LFSR Characteristic Polynomial

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Characteristic polynomial
Defined by

XOR positions Deg. of polynomial = No. of FF For a degree 4 LFSR with all possible connections P(x) = x4+x3+x2+x+1
Always present terms: Primary Feedback (x4) &

Principle Input (1 = x0 )

P(x) = x4+x3+ x+1

coefficient =

0 if no connection coefficient = 1 if connection

Primitive Polynomials: Ensure all possible cases <But one less >
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Autonomous LFSR Pseudo Random Number Generation

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Registers are preloaded with an initial seed Taps Coefficients: C1, C2, C3,.., CN

C0=1

Autonomous LFSR
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Eight-Cell Autonomous LFSR Parameterized

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Serial Input Hardware Implementation of CRC-32

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LFSR Taps/Coefficients
1,2,4,5,7,8,10,11,12,16,22,23,26,32

Example CRC32 for a Network Packet Receiver

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Using LOOPs
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Useful for writing compact systematic code that is easy to be de-bugged Loops available: Repeat, While & For Loop

Syntax

For (initial_statement; control_expression; index_statement)

Statement_for_exeecution

The loop determination must be a constant

If

its a variable, the size of the loop can not be determined statically and thus the loop may not be synthesize

Example- For loop based Decoder

module forloop( output reg 49 input input ); always@(aIn or enable) begin [7:0] yOut, [2:0] aIn, enable module forloop( output reg input input ); integer k; always@(aIn or enable) begin for(k=0;k<8;k=k+1) yOut[k] = (aIn == k)? 1'b1:1'b0; end endmodule [7:0] yOut, [2:0] aIn, enable

yOut = 8'b00000000;
case (aIn) 3'b000 : 3'b001 : 3'b010 : 3'b011 : 3'b100 : 3'b101 : 3'b110 : 3'b111 : endcase end endmodule yOut[0] = 1'b1; yOut[1] = 1'b1; yOut[2] = 1'b1; yOut[3] = 1'b1; yOut[4] = 1'b1; yOut[5] = 1'b1; yOut[6] = 1'b1; yOut[7] = 1'b1;

Example FOR Loops as an exhaustive test vector generator

50 // Illustrates efficient way to exhaustively test // a combinational circuit

module CombinationalCircuit_TB; reg a,b,d,c; wire y; // Instantiate the device-under-test CombinationalCircuit DUT ( .a(a), .b(b), .c(c), .d(d), .y(y) ); // Declare loop index variable integer k; // Apply input stimulus initial begin {a,b,c,d} = 0; for (k=0; k<=16; k=k+1) #5 {a,b,c,d} = k;

module CombinationalCircuit (a,b,c,d,y); input a,b,c,d; output y; reg y; always @ (a or b or c or d) y <= (a==0) ? (a & b & c) : (a ^ b ^ c); endmodule

#20 end endmodule

$finish;

Modelling Digital Machines with Repetitive Algorithms Repeat, While & For Loop
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[CIL]

Coding Guidelines for LOOP

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Do not put a semicolon after for loop Do not use same control variable for multiple loops Use int for control variable

Good Resources MUST READ

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3 Articles related to LFSR by Clive Maxfield Good discussion on Blocking/Non Blocking Statement
Nonblocking

Assignments in Verilog Synthesis, Coding, Styles That Kill!, Clifford E. Cummings Sunburst Design, Inc.

All these shall be uploaded to LMS. Please let me know if this does not happens

Questions.