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Govinda Keshavdas

3131, Homestead Rd, SantaClara, 95051(352) 658-3066 EST govinda.keshavdas@gmail.com EDUCATION University of Florida, Gainesville, Fl Master of Science, Electrical and Computer Engineering. GPA: 3.3/4.0 MN National Institute of Technology, Allahabad, India July 2009 COMPUTER/PROGRAMMING SKILLS Languages Tools C, C++, VHDL,Verilog, System Verilog, Perl, UNIX, Hspice, GNUCAP, Msim Cadence Virtuoso, NI Labview, Modelsim. ACADEMIC PROJECTS
COMPUTER ARCH.

May 2011

Instruction Set Simulator Developed the Instruction Set Simulator for MIPS Processor in C++. Optimized the Simulator using various Adaptive Branch Prediction schemes. EPC C-1 Gen2 UHF RFID Protocol Controller (Digital Core) Controller with ultra low power consumption in 0.25 micron technology was implemented. Low power digital core of the RFID Tag in VHDL. The code was synthesized in Xilinx Virtex4 and Physical Design of the system was performed in Cadence. Vector Quantization Algorithm implementation on VIRTEX 4 FPGA. RAM interfaced. Maximum parallelism implemented using loop unrolling and parallel computation of independent variables. Used DIMETALK and VHDL. Designed a 4 bit SRAM circuit with Sense Amplifier, Row and Column decoder; Simulated in the Cadence and Layout drawn with minimal area. Measured Read, write access time, Noise Margin etc.

DIGITAL IC DESIGN

AUTOMATION Creation of perl script to generate skeleton test bench in VHDL given any entity declaration. ANALOG IC

Designed a 5 bit Flash ADC operating at 200 MHz with the encoder block coded in Verilog A PROFESSIONAL EXPERIENCE

Analog Rails / Get2Spec. Inc., Chandler, Az Chandler,Az Circuit Design Intern Jan - June 2011 Designed and simulated: 1.5 bit stage 10 bit pipelined ADC at 100kHz - demo at DAC(Design Automation Conference) 2011, Sandiego, CA. 1.5 bit stage cyclic ADC at 250 KHz- demo at DAC(Design Automation Conference) 2011, Sandiego, CA. 3rd order switch cascade filter Tested parasitic extraction (C and RC) post layout. Created measurement components for the tool using HSPICE, GNUCAP, and MSIM language syntaxes. Set simulator options on all simulators on Analog Rails design environment after thoroughly understanding SPICE simulation options. Indian Space Research Organization Engineering Intern,Radar-2 Lab Created prototype of a H bridge converter Testing and fault isolation on equipment UNDERGRADUATE PROJECTS Embedded speech recognition using AVR ATMEGA 32 microcontroller programmed on ANSI C using AVR Studio. 16-Bit Microprocessor design using VHDL. A Self Designed Microprocessor, consists of Register array of 16-bit, an ALU, a Shifter, a Program Counter, an Instruction register, Comparator. SriHarikota,A.P.,India April-July 2009

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