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Lecture # 12
<rehan.hafiz@seecs.edu.pk>
http://lms.nust.edu.pk/
Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti 2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan 3. [STV] Advanced FPGA Design, Steve Kilts 4. Ercegovacs Book: Digital Arithmetic 2004 5. Dr. Shoab A Khans CASE Lectures on Advanced Digital System Design
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
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Lecture Overview
3
Last Lecture
Multi-Operand Addition
This Lecture
Binary
Multiplication
Numbers
Signed/Unsigned
Architecture Q format
Binary Multiplication
4
[CIL]
Sequential Multiplier-1
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If Multiplying bit is 1 ADD Multiplicand & Shift If Multiplying bit is 0 Just Shift
http://www.parl.clemson.edu/~walt/ece327/mult.v
Sequential Multiplier-2
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Sequential Multiplier-2
8
Add 0 or Add 1
Sequential Multiplier-3
9
Fractional Numbers
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Multiplication of two numbers Qm.n & Qo.p result into a product with Q(m+o).(n+p) bits. Taking 2s complement of fractional number
Same
Negative Multiplicand, Positive Multiplier Sign Extend the Multiplicand equal to the product bits before the multiplication process
13
Signed Multiplicand, Positive Multiplier [Fractional Number] Align the bits & then forget about the fractional dot ! Sign Extend the Multiplicand equal to the product bits before the multiplication process
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Positive Multiplicand, Negative Multiplier Sign Extend the Multiplier equal to Multiplicand bit Last Partial Product needs to be subtracted OR Add 2s complement
15
Positive Multiplicand, Signed Multiplier [Fractional Number] Align the bits & then forget about the fractional dot ! Sign Extend the Multiplier equal to Multiplicand bit Last Partial Product needs to be subtracted OR Add 2s complement
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Signed Multiplicand, Signed Multiplier Sign Extend the Multiplier Last Partial Product needs to be subtracted OR Add 2s complement
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Signed Negative Multiplicand, Signed Negative Multiplier (Fractional Number) Align the bits & then forget about the fractional dot ! Sign Extend the Multiplier Last Partial Product needs to be subtracted OR Add 2s complement
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Signed Multiplier
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sign bit (keep the MS bit the same instead of shifting in a 0).
At each addition Perform 4 bit addition, Discard Carry out & Shift Right while replicating MSB
1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1
P Add = S Add =
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 0
S Add
= S
1 1
1 1
1 1
1 1 0 0
1 1
1 1 0 0
1 1
0 1 1 0
0
0 0
1
1 0
1
1 1
0
0 1
Add(2s 0 ) = 0
P Add = S Add =
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 0
1 1 1 1
0 0 1 1
1 1 0 0
1 1 1 1
S Add
= S
1 0
1 1
1 0
1 1 0 0
1 0
1 1 0 0
1 0
1 1 1 0
0
0 1
1
1 0
1
1 1
0
0 1
Add(2s 0 ) = 0
P Add = S Add =
0 0
0 0
0 0
0 1 1
1 1 1 1
S Add
= S Add(2s 1 ) = 1 1 1 1 1 1 1
1
1 0
1
1 1 1
Rather than following a selective sign extension for signed numbers we follow a common policy for all (+ve & -ve) numbers Policy
Complement the
sign bit Always extend with ONEs Add ONE to the sign bit
B is positive (S=0) B=0 0 0 0 0 0 . 1 1 0 1 0 1 1 B=1 1 1 1 1 0 . 1 1 0 1 0 1 1 + 1 000000.1101011 B is negative (S=1) B=1 1 1 1 1 1 . 1 1 0 1 0 1 1 B=1 1 1 1 1 1 . 1 1 0 1 0 1 1 1 + 111111.1101011
Example-Sign Extension
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(.)
(.)
(.)
(.)
(.)
1 1 1 1 1 1 1 (.) 1 1 1 (.) (.) 1 1 (.) (.) (.) 1 (.) (.) (.) (.) 1
(.)
(.) (.) (.)
(.)
(.) (.)
(.)
(.)
Policy Complement the sign bit Add ONE to the sign bit Always extend with ONEs
Do 2s Complement
(.)(.)(.)(.) 1+
1(.)(.)(.)(.) 1 1+
So
the MSB is complemented two times; first due to 2s complement & secondly due to sign extension. Since complement of complement is the original bit. MSB needs not to be complemented
1
1
1
(.) 1
(.)
(.) 1 0
(.)
(.) 1 1
(.)
(.) 1 1 0
(.)
Due to 2s complement
Exercise: -2 * -2 or -2 *2
2s Complement Example
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1 1 0 1
1 1 0 0
0 0 0
0
1 1 0 0 0 0 0 0
1
0 1 0
1
1 0 0
0
0 1 0 0 0 0
2s Complement Example
29
1 1 0 1
1 1 0 0
0 0 0 Add
0
1 1 0 0 0 0 0 0
1
0 1 0
1
1 0 0
0
0 1 0 0 0 0
Output
Discard the carries after the MSB Note the different Correction Vectors for +ve & -ve numbers
Multiplier
Multiplication
Addition of PP
Wallace/Dada
Compression Tree
Final Addition Stage
Product